[llvm] [AMDGPU] Simplify legalization of PHI operands (PR #177352)

[Jay Foad via llvm-commits]

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@@ -17310,51 +17318,49 @@ define void @flat_atomic_fadd_f32_saddr_ret_a_a(ptr inreg %ptr) #0 {
 ; GFX90A-NEXT:    ;;#ASMEND
 ; GFX90A-NEXT:    s_andn2_b64 vcc, exec, s[6:7]
 ; GFX90A-NEXT:    v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT:    s_cbranch_vccz .LBB223_4
+; GFX90A-NEXT:    s_cbranch_vccz .LBB223_3
 ; GFX90A-NEXT:  ; %bb.1: ; %atomicrmw.check.private
 ; GFX90A-NEXT:    s_mov_b64 s[6:7], src_private_base
 ; GFX90A-NEXT:    s_cmp_eq_u32 s5, s7
 ; GFX90A-NEXT:    s_cselect_b64 s[6:7], -1, 0
 ; GFX90A-NEXT:    s_andn2_b64 vcc, exec, s[6:7]
-; GFX90A-NEXT:    s_cbranch_vccz .LBB223_7
+; GFX90A-NEXT:    s_cbranch_vccz .LBB223_4
 ; GFX90A-NEXT:  ; %bb.2: ; %atomicrmw.global
 ; GFX90A-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX90A-NEXT:    global_atomic_add_f32 v1, v1, v0, s[4:5] glc
-; GFX90A-NEXT:    s_cbranch_execz .LBB223_8
-; GFX90A-NEXT:  ; %bb.3:
 ; GFX90A-NEXT:    s_waitcnt vmcnt(0)
 ; GFX90A-NEXT:    v_accvgpr_write_b32 a0, v1
 ; GFX90A-NEXT:    s_cbranch_execz .LBB223_5
 ; GFX90A-NEXT:    s_branch .LBB223_6
+; GFX90A-NEXT:  .LBB223_3:
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jayfoad wrote:

It is just arbitrary basic block reordering. With the patch we eliminate this instruction:
```
%76:vgpr_32 = COPY %5:av_32, implicit $exec
```
which leaves a basic block empty, which allows MachineSink to combine it into another block but switches the order of the successors, which cuases BranchFolding to make a different arbitrary layout decision.

https://github.com/llvm/llvm-project/pull/177352