[llvm] [SelectionDAG][ARM] Add lowering for strict fp16 nodes on systems without fullfp16 (PR #173666)

[Eli Friedman via llvm-commits]

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@@ -3412,13 +3422,54 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
   case ISD::FPOW:
   case ISD::FATAN2:
   case ISD::FREM:
-  case ISD::FSUB:        R = SoftPromoteHalfRes_BinOp(N); break;
+  case ISD::FSUB:
+  case ISD::STRICT_FADD:
+  case ISD::STRICT_FDIV:
+  case ISD::STRICT_FMUL:
+  case ISD::STRICT_FSUB:
+  case ISD::STRICT_FMAXIMUM:
+  case ISD::STRICT_FMINIMUM:
+    R = SoftPromoteHalfRes_BinOp(N);
+    break;
+    
+  // FIXME: we can't produce correct lowering for some strict f16
+  // operations, as promotion would violate the strict FP model
+  // and also there are no libcalls for them at the moment.
+  case ISD::STRICT_FPOW:
+  case ISD::STRICT_FATAN2:
+  case ISD::STRICT_FMAXNUM:
+  case ISD::STRICT_FMINNUM:
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efriedma-quic wrote:

What makes STRICT_FMAXNUM different from STRICT_FMAXIMUM, in this context?  

https://github.com/llvm/llvm-project/pull/173666