[llvm] [VPlan] Move tail folding out of VPlanPredicator. NFC (PR #176143)

[Andrei Elovikov via llvm-commits]

eas wrote:

> because the branch-on-cond doesn't use a scalar i1 condition but a vector mask instead.

How is this a problem? Isn't it what predicator sees for the original control flow from VPlan construction (modulo "vector mask" -> "varying i1 condition" renaming, which are essentially the same anyway)? I think explicit control flow while maintaining SSA is a better choice:

* VPlan is in consistent (and potentially verifiable) state
* There is no implicit state being passed anywhere, the information is explicit in the VPlan and can be printed/`CHECK`'ed
* We'd probably get phi->select transformation "for free", see my comment in https://github.com/llvm/llvm-project/pull/176143#discussion_r2710147443

https://github.com/llvm/llvm-project/pull/176143