[llvm] [AArch64] Use +0.0 for accumulator for FMUL -> BFMLAL lowering in more cases (PR #174423)

[Sander de Smalen via llvm-commits]

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@@ -7734,7 +7734,9 @@ SDValue AArch64TargetLowering::LowerFMUL(SDValue Op, SelectionDAG &DAG) const {
                                     : Intrinsic::aarch64_neon_bfmlalt);
 
   EVT AccVT = UseSVEBFMLAL ? MVT::nxv4f32 : MVT::v4f32;
-  SDValue Zero = DAG.getNeutralElement(ISD::FADD, DL, AccVT, Op->getFlags());
+  bool IgnoreZeroSign =
+      Op->getFlags().hasNoSignedZeros() || DAG.canIgnoreSignBitOfZero(Op);
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sdesmalen-arm wrote:

Fine with me, makes sense to do a follow-up patch as there's indeed a few more uses that need fixing up.

https://github.com/llvm/llvm-project/pull/174423