[llvm] [AArch64][SDAG] Combine vecreduce.add(ZExt(predicate)) into cntp(predicate) (PR #176935)

[Benjamin Maxwell via llvm-commits]

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@@ -19423,20 +19409,45 @@ performActiveLaneMaskCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   return DAG.getNode(ISD::CONCAT_VECTORS, DL, N->getValueType(0), Concats);
 }
 
-// Turn a v8i8/v16i8 extended vecreduce into a udot/sdot and vecreduce
-//   vecreduce.add(ext(A)) to vecreduce.add(DOT(zero, A, one))
-//   vecreduce.add(mul(ext(A), ext(B))) to vecreduce.add(DOT(zero, A, B))
-// If we have vectors larger than v16i8 we extract v16i8 vectors,
-// Follow the same steps above to get DOT instructions concatenate them
-// and generate vecreduce.add(concat_vector(DOT, DOT2, ..)).
+// Turn vecreduce.add(ZExt(predicate)) into cntp(predicate).
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MacDue wrote:

I don't think it's necessary. I believe the bits outside the `i4`  would be undefined, and it's only need to (e.g.) compare the value that you'd have to mask them out: https://godbolt.org/z/zGv7483Yq

https://github.com/llvm/llvm-project/pull/176935