[llvm] [AArch64][GlobalISel] FP Info implementation for AArch64. (PR #177158)
Ryan Cowan via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 21 04:57:02 PST 2026
https://github.com/HolyMolyCowMan created https://github.com/llvm/llvm-project/pull/177158
This work sits on top of https://github.com/llvm/llvm-project/pull/155107. The aim is to implement support for extended types in the AArch64 backend.
This features a change very similar to https://github.com/llvm/llvm-project/pull/170276, which I will exclude when https://github.com/llvm/llvm-project/pull/170276 is approved.
Much of the implementation just builds upon https://github.com/llvm/llvm-project/pull/155107 but features changes to the MatchTableExecutor to allow for matching multiple patterns to reduce the need for duplicated patterns.
Currently this is still a work in progress while https://github.com/llvm/llvm-project/pull/155107 stabilises, hence there may be some unpolished code.
>From 6baa709de27e3bcdf36e044b3f87b064857a83de Mon Sep 17 00:00:00 2001
From: Tim Gymnich <tim at gymni.ch>
Date: Fri, 4 Oct 2024 09:20:06 +0000
Subject: [PATCH 01/41] add isScalar and isFixedVector
---
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index d8e0848aff84d..d466dccd9e8df 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -147,6 +147,9 @@ class LLT {
constexpr bool isScalar() const { return IsScalar; }
constexpr bool isToken() const { return IsScalar && RawData == 0; };
constexpr bool isVector() const { return isValid() && IsVector; }
+ constexpr bool isScalar(unsigned Size) const {
+ return isScalar() && getScalarSizeInBits() == Size;
+ }
constexpr bool isPointer() const {
return isValid() && IsPointer && !IsVector;
}
@@ -177,6 +180,12 @@ class LLT {
/// if the LLT is not a vector type.
constexpr bool isFixedVector() const { return isVector() && !isScalable(); }
+ constexpr bool isFixedVector(unsigned NumElements,
+ unsigned ScalarSize) const {
+ return isFixedVector() && getNumElements() == NumElements &&
+ getScalarSizeInBits() == ScalarSize;
+ }
+
/// Returns true if the LLT is a scalable vector. Returns false otherwise,
/// even if the LLT is not a vector type.
constexpr bool isScalableVector() const { return isVector() && isScalable(); }
>From cc16885507e4d578f2c7d849428066acc826e291 Mon Sep 17 00:00:00 2001
From: Tim Gymnich <tim at gymni.ch>
Date: Thu, 6 Feb 2025 13:16:43 +0100
Subject: [PATCH 02/41] changeElementCount
---
.../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 2 +-
llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp | 6 ++----
.../CodeGen/GlobalISel/LegalizerInfoTest.cpp | 14 ++++++++------
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index fd72a3898562e..8412042a780e8 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -380,7 +380,7 @@ LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx,
/// Keep the same scalar or element type as \p TypeIdx, but take the number of
/// elements from \p Ty.
-LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx, LLT Ty);
+LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx, ElementCount EC);
/// Change the scalar size or element size to have the same scalar size as type
/// index \p FromIndex. Unlike changeElementTo, this discards pointer types and
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
index 25c1db91b05d8..ded4df4edc14c 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
@@ -55,12 +55,10 @@ LegalizeMutation LegalizeMutations::changeElementCountTo(unsigned TypeIdx,
}
LegalizeMutation LegalizeMutations::changeElementCountTo(unsigned TypeIdx,
- LLT NewEltTy) {
+ ElementCount EC) {
return [=](const LegalityQuery &Query) {
const LLT OldTy = Query.Types[TypeIdx];
- ElementCount NewEltCount = NewEltTy.isVector() ? NewEltTy.getElementCount()
- : ElementCount::getFixed(1);
- return std::make_pair(TypeIdx, OldTy.changeElementCount(NewEltCount));
+ return std::make_pair(TypeIdx, OldTy.changeElementCount(EC));
};
}
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
index 988e307909232..836c81b524672 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
@@ -420,12 +420,14 @@ TEST(LegalizerInfoTest, RuleSets) {
// Raw type form
LI.getActionDefinitionsBuilder(G_ADD)
- .fewerElementsIf(typeIs(0, v4s32), changeElementCountTo(0, v2s32))
- .fewerElementsIf(typeIs(0, v8s32), changeElementCountTo(0, s32))
- .fewerElementsIf(typeIs(0, LLT::scalable_vector(4, 16)),
- changeElementCountTo(0, LLT::scalable_vector(2, 16)))
- .fewerElementsIf(typeIs(0, LLT::scalable_vector(8, 16)),
- changeElementCountTo(0, s16));
+ .fewerElementsIf(typeIs(0, v4s32),
+ changeElementCountTo(0, ElementCount::getFixed(2)))
+ .fewerElementsIf(typeIs(0, v8s32),
+ changeElementCountTo(0, ElementCount::getFixed(1)))
+ .fewerElementsIf(typeIs(0, LLT::scalable_vector(4, s16)),
+ changeElementCountTo(0, ElementCount::getScalable(2)))
+ .fewerElementsIf(typeIs(0, LLT::scalable_vector(8, s16)),
+ changeElementCountTo(0, ElementCount::getFixed(1)));
LegacyInfo.computeTables();
>From f04aed6fb3b914a563074ebe27b6efd17d993317 Mon Sep 17 00:00:00 2001
From: Tim Gymnich <tim at gymni.ch>
Date: Wed, 12 Feb 2025 13:27:53 +0100
Subject: [PATCH 03/41] FPInfo: LLT changes
---
llvm/include/llvm/CodeGen/LowLevelTypeUtils.h | 2 +-
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 345 +++++++++++++-----
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 3 +-
llvm/lib/CodeGen/LowLevelTypeUtils.cpp | 75 +++-
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 102 ++++--
llvm/lib/CodeGenTypes/LowLevelType.cpp | 60 ++-
.../GlobalISel/GlobalISelMatchTable.cpp | 101 +++--
7 files changed, 490 insertions(+), 198 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h b/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
index 51a298eb8b247..f0c1758a4c9cc 100644
--- a/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
+++ b/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
@@ -41,6 +41,6 @@ LLVM_ABI LLT getLLTForMVT(MVT Ty);
/// Get the appropriate floating point arithmetic semantic based on the bit size
/// of the given scalar LLT.
LLVM_ABI const llvm::fltSemantics &getFltSemanticForLLT(LLT Ty);
-}
+} // namespace llvm
#endif // LLVM_CODEGEN_LOWLEVELTYPEUTILS_H
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index d466dccd9e8df..32572d6753c61 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -30,6 +30,7 @@
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include <cassert>
namespace llvm {
@@ -39,68 +40,150 @@ class raw_ostream;
class LLT {
public:
+ enum class FPVariant {
+ IEEE_FLOAT = 0x0,
+ BRAIN_FLOAT = 0x1, // BRAIN_FLOAT
+ VARIANT_FLOAT_2 = 0x2, // PPC_FLOAT
+ VARIANT_FLOAT_3 = 0x3, // FP80
+ VARIANT_FLOAT_4 = 0x4, // TENSOR_FLOAT
+ VARIANT_FLOAT_5 = 0x5, // UNASSIGNED
+ VARIANT_FLOAT_6 = 0x6, // UNASSIGNED
+ VARIANT_FLOAT_7 = 0x7, // UNASSIGNED
+ };
+
+ enum class Kind : uint64_t {
+ INVALID = 0b000,
+ INTEGER = 0b001,
+ FLOAT = 0b010,
+ POINTER = 0b011,
+ VECTOR_INTEGER = 0b101,
+ VECTOR_FLOAT = 0b110,
+ VECTOR_POINTER = 0b111,
+ };
+
+ constexpr static Kind toVector(Kind Ty) {
+ if (Ty == Kind::POINTER)
+ return Kind::VECTOR_POINTER;
+
+ if (Ty == Kind::INTEGER)
+ return Kind::VECTOR_INTEGER;
+
+ if (Ty == Kind::FLOAT)
+ return Kind::VECTOR_FLOAT;
+
+ llvm_unreachable("Type is already a vector type");
+ }
+
+ constexpr static Kind toScalar(Kind Ty) {
+ if (Ty == Kind::VECTOR_POINTER)
+ return Kind::POINTER;
+
+ if (Ty == Kind::VECTOR_INTEGER)
+ return Kind::INTEGER;
+
+ if (Ty == Kind::VECTOR_FLOAT)
+ return Kind::FLOAT;
+
+ llvm_unreachable("Type is already a scalar type");
+ }
+
/// Get a low-level scalar or aggregate "bag of bits".
- static constexpr LLT scalar(unsigned SizeInBits) {
- return LLT{/*isPointer=*/false, /*isVector=*/false, /*isScalar=*/true,
- ElementCount::getFixed(0), SizeInBits,
- /*AddressSpace=*/0};
+ [[deprecated("Use LLT::integer(unsigned) instead.")]] static constexpr LLT
+ scalar(unsigned SizeInBits) {
+ return LLT{Kind::INTEGER, ElementCount::getFixed(0), SizeInBits,
+ /*AddressSpace=*/0, static_cast<FPVariant>(0)};
+ }
+
+ static constexpr LLT integer(unsigned SizeInBits) {
+ return LLT{Kind::INTEGER, ElementCount::getFixed(0), SizeInBits,
+ /*AddressSpace=*/0, static_cast<FPVariant>(0)};
+ }
+
+ static constexpr LLT floatingPoint(unsigned SizeInBits, FPVariant FP) {
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), SizeInBits,
+ /*AddressSpace=*/0, FP};
}
/// Get a low-level token; just a scalar with zero bits (or no size).
static constexpr LLT token() {
- return LLT{/*isPointer=*/false, /*isVector=*/false,
- /*isScalar=*/true, ElementCount::getFixed(0),
+ return LLT{Kind::INTEGER, ElementCount::getFixed(0),
/*SizeInBits=*/0,
- /*AddressSpace=*/0};
+ /*AddressSpace=*/0, static_cast<FPVariant>(0)};
}
/// Get a low-level pointer in the given address space.
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits) {
assert(SizeInBits > 0 && "invalid pointer size");
- return LLT{/*isPointer=*/true, /*isVector=*/false, /*isScalar=*/false,
- ElementCount::getFixed(0), SizeInBits, AddressSpace};
+ return LLT{Kind::POINTER, ElementCount::getFixed(0), SizeInBits,
+ AddressSpace, static_cast<FPVariant>(0)};
}
/// Get a low-level vector of some number of elements and element width.
- static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits) {
+ [[deprecated("Use LLT::vector(EC, LLT) instead.")]] static constexpr LLT
+ vector(ElementCount EC, unsigned ScalarSizeInBits) {
assert(!EC.isScalar() && "invalid number of vector elements");
- return LLT{/*isPointer=*/false, /*isVector=*/true, /*isScalar=*/false,
- EC, ScalarSizeInBits, /*AddressSpace=*/0};
+ return LLT{Kind::VECTOR_INTEGER, EC, ScalarSizeInBits,
+ /*AddressSpace=*/0, static_cast<FPVariant>(0)};
}
/// Get a low-level vector of some number of elements and element type.
static constexpr LLT vector(ElementCount EC, LLT ScalarTy) {
assert(!EC.isScalar() && "invalid number of vector elements");
assert(!ScalarTy.isVector() && "invalid vector element type");
- return LLT{ScalarTy.isPointer(),
- /*isVector=*/true,
- /*isScalar=*/false,
- EC,
- ScalarTy.getSizeInBits().getFixedValue(),
- ScalarTy.isPointer() ? ScalarTy.getAddressSpace() : 0};
+
+ Kind Info = toVector(ScalarTy.Info);
+ return LLT{Info, EC, ScalarTy.getSizeInBits().getFixedValue(),
+ ScalarTy.isPointer() ? ScalarTy.getAddressSpace() : 0,
+ ScalarTy.isFloat() ? ScalarTy.getFPVariant()
+ : static_cast<FPVariant>(0)};
+ }
+ // Get a 8-bit brain float value.
+ static constexpr LLT bfloat8() {
+ return floatingPoint(8, FPVariant::BRAIN_FLOAT);
+ }
+
+ // Get a 16-bit brain float value.
+ static constexpr LLT bfloat16() {
+ return floatingPoint(16, FPVariant::BRAIN_FLOAT);
}
/// Get a 16-bit IEEE half value.
- /// TODO: Add IEEE semantics to type - This currently returns a simple `scalar(16)`.
static constexpr LLT float16() {
- return scalar(16);
+ return floatingPoint(16, FPVariant::IEEE_FLOAT);
}
/// Get a 32-bit IEEE float value.
static constexpr LLT float32() {
- return scalar(32);
+ return floatingPoint(32, FPVariant::IEEE_FLOAT);
}
/// Get a 64-bit IEEE double value.
static constexpr LLT float64() {
- return scalar(64);
+ return floatingPoint(64, FPVariant::IEEE_FLOAT);
+ }
+
+ /// Get a 80-bit X86 floating point value.
+ static constexpr LLT x86fp80() {
+ return floatingPoint(80, FPVariant::VARIANT_FLOAT_3);
+ }
+
+ /// Get a 128-bit IEEE quad value.
+ static constexpr LLT float128() {
+ return floatingPoint(128, FPVariant::IEEE_FLOAT);
+ }
+
+ /// Get a 128-bit PowerPC double double value.
+ static constexpr LLT ppcf128() {
+ return floatingPoint(128, FPVariant::VARIANT_FLOAT_2);
}
/// Get a low-level fixed-width vector of some number of elements and element
/// width.
- static constexpr LLT fixed_vector(unsigned NumElements,
- unsigned ScalarSizeInBits) {
- return vector(ElementCount::getFixed(NumElements), ScalarSizeInBits);
+ [[deprecated(
+ "Use LLT::fixed_vector(unsigned, LLT) instead.")]] static constexpr LLT
+ fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits) {
+ return vector(ElementCount::getFixed(NumElements),
+ LLT::integer(ScalarSizeInBits));
}
/// Get a low-level fixed-width vector of some number of elements and element
@@ -111,9 +194,11 @@ class LLT {
/// Get a low-level scalable vector of some number of elements and element
/// width.
- static constexpr LLT scalable_vector(unsigned MinNumElements,
- unsigned ScalarSizeInBits) {
- return vector(ElementCount::getScalable(MinNumElements), ScalarSizeInBits);
+ [[deprecated(
+ "Use LLT::scalable_vector(unsigned, LLT) instead.")]] static constexpr LLT
+ scalable_vector(unsigned MinNumElements, unsigned ScalarSizeInBits) {
+ return vector(ElementCount::getScalable(MinNumElements),
+ LLT::integer(ScalarSizeInBits));
}
/// Get a low-level scalable vector of some number of elements and element
@@ -126,36 +211,81 @@ class LLT {
return EC.isScalar() ? ScalarTy : LLT::vector(EC, ScalarTy);
}
- static constexpr LLT scalarOrVector(ElementCount EC, uint64_t ScalarSize) {
+ [[deprecated(
+ "Use LLT::scalarOrVector(EC, LLT) instead.")]] static constexpr LLT
+ scalarOrVector(ElementCount EC, uint64_t ScalarSize) {
assert(ScalarSize <= std::numeric_limits<unsigned>::max() &&
"Not enough bits in LLT to represent size");
- return scalarOrVector(EC, LLT::scalar(static_cast<unsigned>(ScalarSize)));
+ return scalarOrVector(EC, LLT::integer(static_cast<unsigned>(ScalarSize)));
}
- explicit constexpr LLT(bool isPointer, bool isVector, bool isScalar,
- ElementCount EC, uint64_t SizeInBits,
- unsigned AddressSpace)
+ explicit constexpr LLT(Kind Info, ElementCount EC, uint64_t SizeInBits,
+ unsigned AddressSpace, FPVariant FP)
: LLT() {
- init(isPointer, isVector, isScalar, EC, SizeInBits, AddressSpace);
+ init(Info, EC, SizeInBits, AddressSpace, FP);
}
- explicit constexpr LLT()
- : IsScalar(false), IsPointer(false), IsVector(false), RawData(0) {}
LLVM_ABI explicit LLT(MVT VT);
+ explicit constexpr LLT() : Info(static_cast<Kind>(0)), RawData(0) {}
- constexpr bool isValid() const { return IsScalar || RawData != 0; }
- constexpr bool isScalar() const { return IsScalar; }
- constexpr bool isToken() const { return IsScalar && RawData == 0; };
- constexpr bool isVector() const { return isValid() && IsVector; }
+ constexpr bool isValid() const { return isToken() || RawData != 0; }
+ constexpr bool isScalar() const { return Info == Kind::INTEGER || Info == Kind::FLOAT; }
constexpr bool isScalar(unsigned Size) const {
return isScalar() && getScalarSizeInBits() == Size;
}
+ constexpr bool isFloat() const { return isValid() && Info == Kind::FLOAT; }
+ constexpr bool isFloat(unsigned Size) const {
+ return isFloat() && getScalarSizeInBits() == Size;
+ }
+ constexpr bool isVariantFloat() const {
+ return isFloat() && getFPVariant() != FPVariant::IEEE_FLOAT;
+ }
+ constexpr bool isVariantFloat(FPVariant Variant) const {
+ return isFloat() && getFPVariant() == Variant;
+ }
+ constexpr bool isVariantFloat(unsigned Size, FPVariant Variant) const {
+ return isVariantFloat(Variant) && getScalarSizeInBits() == Size;
+ }
+ constexpr bool isFloatVector() const {
+ return isVector() && Info == Kind::VECTOR_FLOAT;
+ }
+ constexpr bool isIEEEFloat(unsigned Size) const {
+ return isVariantFloat(Size, FPVariant::IEEE_FLOAT);
+ }
+ constexpr bool isBFloat(unsigned Size) const {
+ return isVariantFloat(Size, FPVariant::BRAIN_FLOAT);
+ }
+ constexpr bool isX86FP80() const {
+ return isVariantFloat(80, FPVariant::VARIANT_FLOAT_3);
+ }
+ constexpr bool isPPCF128() const {
+ return isVariantFloat(128, FPVariant::VARIANT_FLOAT_2);
+ }
+ constexpr bool isToken() const {
+ return Info == Kind::INTEGER && RawData == 0;
+ }
+ constexpr bool isInteger() const {
+ return isValid() && Info == Kind::INTEGER;
+ }
+ constexpr bool isInteger(unsigned Size) const {
+ return isInteger() && getScalarSizeInBits() == Size;
+ }
+ constexpr bool isIntegerVector() const {
+ return isVector() && Info == Kind::VECTOR_INTEGER;
+ }
+ constexpr bool isVector() const {
+ return isValid() &&
+ (Info == Kind::VECTOR_INTEGER || Info == Kind::VECTOR_FLOAT ||
+ Info == Kind::VECTOR_POINTER);
+ }
constexpr bool isPointer() const {
- return isValid() && IsPointer && !IsVector;
+ return isValid() && Info == Kind::POINTER;
+ }
+ constexpr bool isPointerVector() const {
+ return isVector() && Info == Kind::VECTOR_POINTER;
}
- constexpr bool isPointerVector() const { return IsPointer && isVector(); }
constexpr bool isPointerOrPointerVector() const {
- return IsPointer && isValid();
+ return isPointer() || isPointerVector();
}
/// Returns the number of elements in a vector LLT. Must only be called on
@@ -191,7 +321,7 @@ class LLT {
constexpr bool isScalableVector() const { return isVector() && isScalable(); }
constexpr ElementCount getElementCount() const {
- assert(IsVector && "cannot get number of elements on scalar/aggregate");
+ assert(isVector() && "cannot get number of elements on scalar/aggregate");
return ElementCount::get(getFieldValue(VectorElementsFieldInfo),
isScalable());
}
@@ -216,6 +346,15 @@ class LLT {
return isVector() ? getElementType() : *this;
}
+ constexpr FPVariant getFPVariant() const {
+ assert((isFloat() || isFloatVector()) &&
+ "cannot get FP info for non float type");
+
+ return FPVariant(getFieldValue(FPFieldInfo));
+ }
+
+ constexpr Kind getKind() const { return Info; }
+
/// If this type is a vector, return a vector with the same number of elements
/// but the new element type. Otherwise, return the new element type.
constexpr LLT changeElementType(LLT NewEltTy) const {
@@ -226,10 +365,10 @@ class LLT {
/// but the new element size. Otherwise, return the new element type. Invalid
/// for pointer types. For pointer types, use changeElementType.
constexpr LLT changeElementSize(unsigned NewEltSize) const {
- assert(!isPointerOrPointerVector() &&
+ assert(!isPointerOrPointerVector() && !(isFloat() || isFloatVector()) &&
"invalid to directly change element size for pointers");
- return isVector() ? LLT::vector(getElementCount(), NewEltSize)
- : LLT::scalar(NewEltSize);
+ return isVector() ? LLT::vector(getElementCount(), LLT::integer(NewEltSize))
+ : LLT::integer(NewEltSize);
}
/// Return a vector or scalar with the same element type and the new element
@@ -238,6 +377,10 @@ class LLT {
return LLT::scalarOrVector(EC, getScalarType());
}
+ constexpr LLT changeElementCount(unsigned NumElements) const {
+ return changeElementCount(ElementCount::getFixed(NumElements));
+ }
+
/// Return a type that is \p Factor times smaller. Reduces the number of
/// elements if this is a vector, or the bitwidth for scalar/pointers. Does
/// not attempt to handle cases that aren't evenly divisible.
@@ -252,7 +395,7 @@ class LLT {
}
assert(getScalarSizeInBits() % Factor == 0);
- return scalar(getScalarSizeInBits() / Factor);
+ return integer(getScalarSizeInBits() / Factor);
}
/// Produce a vector type that is \p Factor times bigger, preserving the
@@ -286,10 +429,23 @@ class LLT {
/// Returns the vector's element type. Only valid for vector types.
constexpr LLT getElementType() const {
assert(isVector() && "cannot get element type of scalar/aggregate");
- if (IsPointer)
+ if (isPointerVector())
return pointer(getAddressSpace(), getScalarSizeInBits());
- else
- return scalar(getScalarSizeInBits());
+
+ if (isFloatVector())
+ return floatingPoint(getScalarSizeInBits(), getFPVariant());
+
+ return integer(getScalarSizeInBits());
+ }
+
+ constexpr LLT changeToInteger() const {
+ if (isPointer() || isPointerVector())
+ return *this;
+
+ if (isVector())
+ return vector(getElementCount(), LLT::integer(getScalarSizeInBits()));
+
+ return integer(getSizeInBits());
}
LLVM_ABI void print(raw_ostream &OS) const;
@@ -299,8 +455,7 @@ class LLT {
#endif
constexpr bool operator==(const LLT &RHS) const {
- return IsPointer == RHS.IsPointer && IsVector == RHS.IsVector &&
- IsScalar == RHS.IsScalar && RHS.RawData == RawData;
+ return Info == RHS.Info && RawData == RHS.RawData;
}
constexpr bool operator!=(const LLT &RHS) const { return !(*this == RHS); }
@@ -310,37 +465,33 @@ class LLT {
private:
/// LLT is packed into 64 bits as follows:
- /// isScalar : 1
- /// isPointer : 1
- /// isVector : 1
- /// with 61 bits remaining for Kind-specific data, packed in bitfields
- /// as described below. As there isn't a simple portable way to pack bits
- /// into bitfields, here the different fields in the packed structure is
+ /// Info : 3
+ /// RawData : 61
+ /// with 61 bits of RawData remaining for Kind-specific data, packed in
+ /// bitfields as described below. As there isn't a simple portable way to pack
+ /// bits into bitfields, here the different fields in the packed structure is
/// described in static const *Field variables. Each of these variables
/// is a 2-element array, with the first element describing the bitfield size
/// and the second element describing the bitfield offset.
///
- /// +--------+---------+--------+----------+----------------------+
- /// |isScalar|isPointer|isVector| RawData |Notes |
- /// +--------+---------+--------+----------+----------------------+
- /// | 0 | 0 | 0 | 0 |Invalid |
- /// +--------+---------+--------+----------+----------------------+
- /// | 0 | 0 | 1 | 0 |Tombstone Key |
- /// +--------+---------+--------+----------+----------------------+
- /// | 0 | 1 | 0 | 0 |Empty Key |
- /// +--------+---------+--------+----------+----------------------+
- /// | 1 | 0 | 0 | 0 |Token |
- /// +--------+---------+--------+----------+----------------------+
- /// | 1 | 0 | 0 | non-zero |Scalar |
- /// +--------+---------+--------+----------+----------------------+
- /// | 0 | 1 | 0 | non-zero |Pointer |
- /// +--------+---------+--------+----------+----------------------+
- /// | 0 | 0 | 1 | non-zero |Vector of non-pointer |
- /// +--------+---------+--------+----------+----------------------+
- /// | 0 | 1 | 1 | non-zero |Vector of pointer |
- /// +--------+---------+--------+----------+----------------------+
- ///
- /// Everything else is reserved.
+ /*
+ --- LLT ---
+
+ 63 56 47 39 31 23 15 7 0
+ | | | | | | | | |
+ |xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|
+ ................................... (1)
+ ***************** (2)
+ ~~~~~~~~~~~~~~~~~~~~~~~~~~ (3)
+ ^^^^^^^^^^^^^^^^^ (4)
+ @ (5)
+ ### (6)
+ %%% (7)
+
+ (1) ScalarSize (2) PointerSize (3) PointerAddressSpace
+ (4) VectorElements (5) VectorScalable (6) FPVariant (7) Kind
+
+ */
typedef int BitFieldInfo[2];
///
/// This is how the bitfields are packed per Kind:
@@ -350,6 +501,7 @@ class LLT {
/// * Non-pointer scalar (isPointer == 0 && isVector == 0):
/// SizeInBits: 32;
static const constexpr BitFieldInfo ScalarSizeFieldInfo{32, 29};
+ static const constexpr BitFieldInfo FPFieldInfo{3, 21};
/// * Pointer (isPointer == 1 && isVector == 0):
/// SizeInBits: 16;
/// AddressSpace: 24;
@@ -367,9 +519,7 @@ class LLT {
/// AddressSpace: 24;
/// Scalable: 1;
- uint64_t IsScalar : 1;
- uint64_t IsPointer : 1;
- uint64_t IsVector : 1;
+ Kind Info : 3;
uint64_t RawData : 61;
static constexpr uint64_t getMask(const BitFieldInfo FieldInfo) {
@@ -390,21 +540,21 @@ class LLT {
return getMask(FieldInfo) & (RawData >> FieldInfo[1]);
}
- constexpr void init(bool IsPointer, bool IsVector, bool IsScalar,
- ElementCount EC, uint64_t SizeInBits,
- unsigned AddressSpace) {
+ constexpr void init(Kind Info, ElementCount EC, uint64_t SizeInBits,
+ unsigned AddressSpace, FPVariant FP) {
assert(SizeInBits <= std::numeric_limits<unsigned>::max() &&
"Not enough bits in LLT to represent size");
- this->IsPointer = IsPointer;
- this->IsVector = IsVector;
- this->IsScalar = IsScalar;
- if (IsPointer) {
+ this->Info = Info;
+ if (Info == Kind::POINTER || Info == Kind::VECTOR_POINTER) {
RawData = maskAndShift(SizeInBits, PointerSizeFieldInfo) |
maskAndShift(AddressSpace, PointerAddressSpaceFieldInfo);
} else {
- RawData = maskAndShift(SizeInBits, ScalarSizeFieldInfo);
+ RawData = maskAndShift(SizeInBits, ScalarSizeFieldInfo) |
+ maskAndShift((uint64_t)FP, FPFieldInfo);
}
- if (IsVector) {
+
+ if (Info == Kind::VECTOR_INTEGER || Info == Kind::VECTOR_FLOAT ||
+ Info == Kind::VECTOR_POINTER) {
RawData |= maskAndShift(EC.getKnownMinValue(), VectorElementsFieldInfo) |
maskAndShift(EC.isScalable() ? 1 : 0, VectorScalableFieldInfo);
}
@@ -412,8 +562,7 @@ class LLT {
public:
constexpr uint64_t getUniqueRAWLLTData() const {
- return ((uint64_t)RawData) << 3 | ((uint64_t)IsScalar) << 2 |
- ((uint64_t)IsPointer) << 1 | ((uint64_t)IsVector);
+ return ((uint64_t)RawData) << 3 | ((uint64_t)Info);
}
};
@@ -422,15 +571,15 @@ inline raw_ostream& operator<<(raw_ostream &OS, const LLT &Ty) {
return OS;
}
-template<> struct DenseMapInfo<LLT> {
+template <> struct DenseMapInfo<LLT> {
static inline LLT getEmptyKey() {
LLT Invalid;
- Invalid.IsPointer = true;
+ Invalid.Info = static_cast<LLT::Kind>(2);
return Invalid;
}
static inline LLT getTombstoneKey() {
LLT Invalid;
- Invalid.IsVector = true;
+ Invalid.Info = static_cast<LLT::Kind>(3);
return Invalid;
}
static inline unsigned getHashValue(const LLT &Ty) {
@@ -442,6 +591,6 @@ template<> struct DenseMapInfo<LLT> {
}
};
-}
+} // namespace llvm
#endif // LLVM_CODEGEN_LOWLEVELTYPE_H
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 27df7e369436a..211809eacf4a7 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -581,7 +581,8 @@ MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
Op.getLLTTy(*getMRI()).getSizeInBits())
Opcode = TargetOpcode::G_TRUNC;
else
- assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
+ assert(Res.getLLTTy(*getMRI()).getSizeInBits() ==
+ Op.getLLTTy(*getMRI()).getSizeInBits());
return buildInstr(Opcode, Res, Op);
}
diff --git a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
index 936c9fbb2fff0..cf34bf71a8c3a 100644
--- a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
+++ b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
@@ -36,7 +36,37 @@ LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) {
// concerned.
auto SizeInBits = DL.getTypeSizeInBits(&Ty);
assert(SizeInBits != 0 && "invalid zero-sized type");
- return LLT::scalar(SizeInBits);
+
+ if (Ty.isFloatingPointTy()) {
+ if (Ty.isHalfTy())
+ return LLT::float16();
+
+ if (Ty.isBFloatTy())
+ return LLT::bfloat16();
+
+ if (Ty.isFloatTy())
+ return LLT::float32();
+
+ if (Ty.isDoubleTy())
+ return LLT::float64();
+
+ if (Ty.isX86_FP80Ty())
+ return LLT::x86fp80();
+
+ if (Ty.isFP128Ty())
+ return LLT::float128();
+
+ if (Ty.isPPC_FP128Ty())
+ return LLT::ppcf128();
+
+ llvm_unreachable("Unhandled LLVM IR floating point type");
+ }
+
+ if (Ty.isIntegerTy()) {
+ return LLT::integer(SizeInBits);
+ }
+
+ return LLT::integer(SizeInBits);
}
if (Ty.isTokenTy())
@@ -46,12 +76,25 @@ LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) {
}
MVT llvm::getMVTForLLT(LLT Ty) {
- if (!Ty.isVector())
- return MVT::getIntegerVT(Ty.getSizeInBits());
+ if (Ty.isVector()) {
+ return MVT::getVectorVT(getMVTForLLT(Ty.getElementType()),
+ Ty.getElementCount());
+ }
+
+ if (Ty.isFloat()) {
+ if (Ty == LLT::bfloat16())
+ return MVT::bf16;
+
+ if (Ty == LLT::x86fp80())
+ return MVT::f80;
+
+ if (Ty == LLT::ppcf128())
+ return MVT::ppcf128;
+
+ return MVT::getFloatingPointVT(Ty.getSizeInBits());
+ }
- return MVT::getVectorVT(
- MVT::getIntegerVT(Ty.getElementType().getSizeInBits()),
- Ty.getElementCount());
+ return MVT::getIntegerVT(Ty.getSizeInBits());
}
EVT llvm::getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx) {
@@ -63,16 +106,20 @@ EVT llvm::getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx) {
return EVT::getIntegerVT(Ctx, Ty.getSizeInBits());
}
-LLT llvm::getLLTForMVT(MVT Ty) {
- if (!Ty.isVector())
- return LLT::scalar(Ty.getSizeInBits());
-
- return LLT::scalarOrVector(Ty.getVectorElementCount(),
- Ty.getVectorElementType().getSizeInBits());
-}
+LLT llvm::getLLTForMVT(MVT Ty) { return LLT(Ty); }
const llvm::fltSemantics &llvm::getFltSemanticForLLT(LLT Ty) {
- assert(Ty.isScalar() && "Expected a scalar type.");
+ assert(Ty.isFloat() && "Expected a scalar type.");
+
+ if (Ty.isBFloat(16))
+ return APFloat::BFloat();
+ if (Ty.isX86FP80())
+ return APFloat::x87DoubleExtended();
+ if (Ty.isPPCF128())
+ return APFloat::PPCDoubleDouble();
+
+ assert(!Ty.isVariantFloat() && "Unhandled variant float type");
+
switch (Ty.getSizeInBits()) {
case 16:
return APFloat::IEEEhalf();
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 6a464d9dd6886..b0cd260fadd7e 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1929,26 +1929,33 @@ static bool verifyAddrSpace(uint64_t AddrSpace) {
}
bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
- if (Token.range().front() == 's' || Token.range().front() == 'p') {
- StringRef SizeStr = Token.range().drop_front();
- if (SizeStr.size() == 0 || !llvm::all_of(SizeStr, isdigit))
- return error("expected integers after 's'/'p' type character");
- }
-
- if (Token.range().front() == 's') {
- auto ScalarSize = APSInt(Token.range().drop_front()).getZExtValue();
- if (ScalarSize) {
- if (!verifyScalarSize(ScalarSize))
- return error("invalid size for scalar type");
- Ty = LLT::scalar(ScalarSize);
- } else {
+ StringRef TypeDigits = Token.range();
+ if (TypeDigits.consume_front("s") || TypeDigits.consume_front("i") ||
+ TypeDigits.consume_front("f") || TypeDigits.consume_front("p") ||
+ TypeDigits.consume_front("bf")) {
+ if (TypeDigits.empty() || !llvm::all_of(TypeDigits, isdigit))
+ return error("expected integers after 's'/'i'/'f'/'bf'/'p' type prefix");
+ }
+
+ if (Token.range().starts_with("s") || Token.range().starts_with("i")) {
+ auto ScalarSize = APSInt(TypeDigits).getZExtValue();
+ if (!ScalarSize) {
Ty = LLT::token();
+ lex();
+ return false;
}
+
+ if (!verifyScalarSize(ScalarSize))
+ return error("invalid size for scalar type");
+
+ Ty = LLT::integer(ScalarSize);
lex();
return false;
- } else if (Token.range().front() == 'p') {
+ }
+
+ if (Token.range().starts_with("p")) {
const DataLayout &DL = MF.getDataLayout();
- uint64_t AS = APSInt(Token.range().drop_front()).getZExtValue();
+ uint64_t AS = APSInt(TypeDigits).getZExtValue();
if (!verifyAddrSpace(AS))
return error("invalid address space number");
@@ -1957,6 +1964,23 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
return false;
}
+ if (Token.range().starts_with("f") || Token.range().starts_with("bf")) {
+ LLT::FPVariant FPVariant;
+ if (Token.range().starts_with("f")) {
+ FPVariant = LLT::FPVariant::IEEE_FLOAT;
+ } else if (Token.range().starts_with("bf")) {
+ FPVariant = LLT::FPVariant::BRAIN_FLOAT;
+ } else {
+ return error("unknown floating point type identifier");
+ }
+ auto ScalarSize = APSInt(TypeDigits).getZExtValue();
+ if (!ScalarSize || !verifyScalarSize(ScalarSize))
+ return error("invalid size for scalar type");
+ Ty = LLT::floatingPoint(ScalarSize, FPVariant);
+ lex();
+ return false;
+ }
+
// Now we're looking for a vector.
if (Token.isNot(MIToken::less))
return error(Loc, "expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, "
@@ -1991,25 +2015,39 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
return GetError();
lex();
- if (Token.range().front() != 's' && Token.range().front() != 'p')
+ StringRef VectorTyDigits = Token.range();
+ if (!VectorTyDigits.consume_front("s") &&
+ !VectorTyDigits.consume_front("i") &&
+ !VectorTyDigits.consume_front("f") &&
+ !VectorTyDigits.consume_front("p") && !VectorTyDigits.consume_front("bf"))
return GetError();
- StringRef SizeStr = Token.range().drop_front();
- if (SizeStr.size() == 0 || !llvm::all_of(SizeStr, isdigit))
- return error("expected integers after 's'/'p' type character");
+ if (VectorTyDigits.empty() || !llvm::all_of(VectorTyDigits, isdigit))
+ return error(
+ "expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
- if (Token.range().front() == 's') {
- auto ScalarSize = APSInt(Token.range().drop_front()).getZExtValue();
+ if (Token.range().starts_with("s") || Token.range().starts_with("i")) {
+ auto ScalarSize = APSInt(VectorTyDigits).getZExtValue();
if (!verifyScalarSize(ScalarSize))
return error("invalid size for scalar element in vector");
- Ty = LLT::scalar(ScalarSize);
- } else if (Token.range().front() == 'p') {
+ Ty = LLT::integer(ScalarSize);
+ } else if (Token.range().starts_with("p")) {
const DataLayout &DL = MF.getDataLayout();
- uint64_t AS = APSInt(Token.range().drop_front()).getZExtValue();
+ uint64_t AS = APSInt(VectorTyDigits).getZExtValue();
if (!verifyAddrSpace(AS))
return error("invalid address space number");
Ty = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
+ } else if (Token.range().starts_with("f")) {
+ auto ScalarSize = APSInt(VectorTyDigits).getZExtValue();
+ if (!verifyScalarSize(ScalarSize))
+ return error("invalid size for float element in vector");
+ Ty = LLT::floatingPoint(ScalarSize, LLT::FPVariant::IEEE_FLOAT);
+ } else if (Token.range().starts_with("bf")) {
+ auto ScalarSize = APSInt(VectorTyDigits).getZExtValue();
+ if (!verifyScalarSize(ScalarSize))
+ return error("invalid size for bfloat element in vector");
+ Ty = LLT::floatingPoint(ScalarSize, LLT::FPVariant::BRAIN_FLOAT);
} else
return GetError();
lex();
@@ -2025,14 +2063,14 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
bool MIParser::parseTypedImmediateOperand(MachineOperand &Dest) {
assert(Token.is(MIToken::Identifier));
- StringRef TypeStr = Token.range();
- if (TypeStr.front() != 'i' && TypeStr.front() != 's' &&
- TypeStr.front() != 'p')
- return error(
- "a typed immediate operand should start with one of 'i', 's', or 'p'");
- StringRef SizeStr = Token.range().drop_front();
- if (SizeStr.size() == 0 || !llvm::all_of(SizeStr, isdigit))
- return error("expected integers after 'i'/'s'/'p' type character");
+ StringRef TypeDigits = Token.range();
+ if (!TypeDigits.consume_front("i") && !TypeDigits.consume_front("s") &&
+ !TypeDigits.consume_front("p") && !TypeDigits.consume_front("f") &&
+ !TypeDigits.consume_front("bf"))
+ return error("a typed immediate operand should start with one of 'i', "
+ "'s','f','bf', or 'p'");
+ if (TypeDigits.empty() || !llvm::all_of(TypeDigits, isdigit))
+ return error("expected integers after 'i'/'s'/'f'/'bf'/'p' type character");
auto Loc = Token.location();
lex();
diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index 4785f2652b00e..925b4efaf0edf 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -16,22 +16,45 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+static std::optional<LLT::FPVariant> deriveFPInfo(MVT VT) {
+ if (!VT.isFloatingPoint())
+ return std::nullopt;
+
+ switch (VT.getScalarType().SimpleTy) {
+ case MVT::bf16:
+ return LLT::FPVariant::BRAIN_FLOAT;
+ case MVT::f80:
+ return LLT::FPVariant::VARIANT_FLOAT_3;
+ case MVT::ppcf128:
+ return LLT::FPVariant::VARIANT_FLOAT_2;
+ default:
+ return LLT::FPVariant::IEEE_FLOAT;
+ }
+}
+
LLT::LLT(MVT VT) {
+ auto FP = deriveFPInfo(VT);
+ bool AsVector = VT.isVector() &&
+ (VT.getVectorMinNumElements() > 1 || VT.isScalableVector());
+
+ Kind Info;
+ if (FP.has_value())
+ Info = AsVector ? Kind::VECTOR_FLOAT : Kind::FLOAT;
+ else
+ Info = AsVector ? Kind::VECTOR_INTEGER : Kind::INTEGER;
+
if (VT.isVector()) {
- bool asVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector();
- init(/*IsPointer=*/false, asVector, /*IsScalar=*/!asVector,
- VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(),
- /*AddressSpace=*/0);
+ init(Info, VT.getVectorElementCount(),
+ VT.getVectorElementType().getSizeInBits(),
+ /*AddressSpace=*/0, FP.value_or(FPVariant::IEEE_FLOAT));
} else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
// Aggregates are no different from real scalars as far as GlobalISel is
// concerned.
- init(/*IsPointer=*/false, /*IsVector=*/false, /*IsScalar=*/true,
- ElementCount::getFixed(0), VT.getSizeInBits(), /*AddressSpace=*/0);
+ init(Info, ElementCount::getFixed(0), VT.getSizeInBits(),
+ /*AddressSpace=*/0, FP.value_or(FPVariant::IEEE_FLOAT));
} else {
- IsScalar = false;
- IsPointer = false;
- IsVector = false;
- RawData = 0;
+ this->Info = static_cast<Kind>(0);
+ this->RawData = 0;
}
}
@@ -39,13 +62,23 @@ void LLT::print(raw_ostream &OS) const {
if (isVector()) {
OS << "<";
OS << getElementCount() << " x " << getElementType() << ">";
- } else if (isPointer())
+ } else if (isPointer()) {
OS << "p" << getAddressSpace();
- else if (isValid()) {
+ } else if (isBFloat(16)) {
+ OS << "bf16";
+ } else if (isPPCF128()) {
+ OS << "ppcf128";
+ } else if (isFloat()) {
+ assert(!isVariantFloat() && "unknown float variant");
+ OS << "f" << getScalarSizeInBits();
+ } else if (isInteger()) {
+ OS << "i" << getScalarSizeInBits();
+ } else if (isValid()) {
assert(isScalar() && "unexpected type");
OS << "s" << getScalarSizeInBits();
- } else
+ } else {
OS << "LLT_invalid";
+ }
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
@@ -56,6 +89,7 @@ LLVM_DUMP_METHOD void LLT::dump() const {
#endif
const constexpr LLT::BitFieldInfo LLT::ScalarSizeFieldInfo;
+const constexpr LLT::BitFieldInfo LLT::FPFieldInfo;
const constexpr LLT::BitFieldInfo LLT::PointerSizeFieldInfo;
const constexpr LLT::BitFieldInfo LLT::PointerAddressSpaceFieldInfo;
const constexpr LLT::BitFieldInfo LLT::VectorElementsFieldInfo;
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index efaf05adc8f06..16a12cabce4c5 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -360,42 +360,95 @@ std::string LLTCodeGen::getCxxEnumValue() const {
void LLTCodeGen::emitCxxEnumValue(raw_ostream &OS) const {
if (Ty.isScalar()) {
- OS << "GILLT_s" << Ty.getSizeInBits();
+ if (Ty.isBFloat(16))
+ OS << "GILLT_bf16";
+ else if (Ty.isPPCF128())
+ OS << "GILLT_ppcf128";
+ else if (Ty.isX86FP80())
+ OS << "GILLT_x86fp80";
+ else if (Ty.isFloat())
+ OS << "GILLT_f" << Ty.getSizeInBits();
+ else if (Ty.isInteger())
+ OS << "GILLT_i" << Ty.getSizeInBits();
+ else
+ OS << "GILLT_s" << Ty.getSizeInBits();
return;
}
if (Ty.isVector()) {
OS << (Ty.isScalable() ? "GILLT_nxv" : "GILLT_v")
- << Ty.getElementCount().getKnownMinValue() << "s"
- << Ty.getScalarSizeInBits();
+ << Ty.getElementCount().getKnownMinValue();
+
+ LLT ElemTy = Ty.getElementType();
+ if (ElemTy.isBFloat(16))
+ OS << "bf16";
+ else if (ElemTy.isPPCF128())
+ OS << "ppcf128";
+ else if (ElemTy.isX86FP80())
+ OS << "x86fp80";
+ else if (ElemTy.isFloat())
+ OS << "f" << ElemTy.getSizeInBits();
+ else if (Ty.isInteger())
+ OS << "i" << ElemTy.getSizeInBits();
+ else
+ OS << "s" << ElemTy.getSizeInBits();
return;
}
+
if (Ty.isPointer()) {
OS << "GILLT_p" << Ty.getAddressSpace();
if (Ty.getSizeInBits() > 0)
OS << "s" << Ty.getSizeInBits();
return;
}
+
llvm_unreachable("Unhandled LLT");
}
void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
if (Ty.isScalar()) {
- OS << "LLT::scalar(" << Ty.getSizeInBits() << ")";
+ if (Ty.isInteger())
+ OS << "LLT::integer(" << Ty.getScalarSizeInBits() << ")";
+ else if (Ty.isBFloat(16))
+ OS << "LLT::bfloat()";
+ else if (Ty.isPPCF128())
+ OS << "LLT::ppcf128()";
+ else if (Ty.isX86FP80())
+ OS << "LLT::x86fp80()";
+ else if (Ty.isFloat())
+ OS << "LLT::floatingPoint(" << Ty.getScalarSizeInBits()
+ << ", LLT::FPVariant::IEEE_FLOAT)";
return;
}
+
if (Ty.isVector()) {
OS << "LLT::vector("
<< (Ty.isScalable() ? "ElementCount::getScalable("
: "ElementCount::getFixed(")
- << Ty.getElementCount().getKnownMinValue() << "), "
- << Ty.getScalarSizeInBits() << ")";
+ << Ty.getElementCount().getKnownMinValue() << "), ";
+
+ LLT ElemTy = Ty.getElementType();
+ if (ElemTy.isInteger())
+ OS << "LLT::integer(" << ElemTy.getScalarSizeInBits() << ")";
+ else if (ElemTy.isBFloat(16))
+ OS << "LLT::bfloat()";
+ else if (ElemTy.isPPCF128())
+ OS << "LLT::ppcf128()";
+ else if (ElemTy.isX86FP80())
+ OS << "LLT::x86fp80()";
+ else if (ElemTy.isFloat())
+ OS << "LLT::floatingPoint(" << ElemTy.getScalarSizeInBits()
+ << ", LLT::FPVariant::IEEE_FLOAT)";
+
+ OS << ")";
return;
}
+
if (Ty.isPointer() && Ty.getSizeInBits() > 0) {
OS << "LLT::pointer(" << Ty.getAddressSpace() << ", " << Ty.getSizeInBits()
<< ")";
return;
}
+
llvm_unreachable("Unhandled LLT");
}
@@ -403,36 +456,7 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
/// particular logic behind the order but either A < B or B < A must be
/// true if A != B.
bool LLTCodeGen::operator<(const LLTCodeGen &Other) const {
- if (Ty.isValid() != Other.Ty.isValid())
- return Ty.isValid() < Other.Ty.isValid();
- if (!Ty.isValid())
- return false;
-
- if (Ty.isVector() != Other.Ty.isVector())
- return Ty.isVector() < Other.Ty.isVector();
- if (Ty.isScalar() != Other.Ty.isScalar())
- return Ty.isScalar() < Other.Ty.isScalar();
- if (Ty.isPointer() != Other.Ty.isPointer())
- return Ty.isPointer() < Other.Ty.isPointer();
-
- if (Ty.isPointer() && Ty.getAddressSpace() != Other.Ty.getAddressSpace())
- return Ty.getAddressSpace() < Other.Ty.getAddressSpace();
-
- if (Ty.isVector() && Ty.getElementCount() != Other.Ty.getElementCount())
- return std::tuple(Ty.isScalable(),
- Ty.getElementCount().getKnownMinValue()) <
- std::tuple(Other.Ty.isScalable(),
- Other.Ty.getElementCount().getKnownMinValue());
-
- assert((!Ty.isVector() || Ty.isScalable() == Other.Ty.isScalable()) &&
- "Unexpected mismatch of scalable property");
- return Ty.isVector()
- ? std::tuple(Ty.isScalable(),
- Ty.getSizeInBits().getKnownMinValue()) <
- std::tuple(Other.Ty.isScalable(),
- Other.Ty.getSizeInBits().getKnownMinValue())
- : Ty.getSizeInBits().getFixedValue() <
- Other.Ty.getSizeInBits().getFixedValue();
+ return Ty.getUniqueRAWLLTData() < Other.Ty.getUniqueRAWLLTData();
}
//===- LLTCodeGen Helpers -------------------------------------------------===//
@@ -441,11 +465,10 @@ std::optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) {
MVT VT(SVT);
if (VT.isVector() && !VT.getVectorElementCount().isScalar())
- return LLTCodeGen(
- LLT::vector(VT.getVectorElementCount(), VT.getScalarSizeInBits()));
+ return LLTCodeGen(LLT(VT));
if (VT.isInteger() || VT.isFloatingPoint())
- return LLTCodeGen(LLT::scalar(VT.getSizeInBits()));
+ return LLTCodeGen(LLT(VT));
return std::nullopt;
}
>From 79ba6eb82ba370025a4d90da8e3b4a050620e95b Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Fri, 22 Aug 2025 19:13:47 +0300
Subject: [PATCH 04/41] Return default logic for LLT::scalar. Allow target to
enable and disable extended types for llvm-ir lowering in TargetLoweringBase.
Added flag for GISel emitter to enable/disable extended types in matcher
tables
---
llvm/include/llvm/CodeGen/Analysis.h | 3 +-
llvm/include/llvm/CodeGen/LowLevelTypeUtils.h | 4 +-
llvm/include/llvm/CodeGen/TargetLowering.h | 3 +
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 134 ++++++++++--------
llvm/include/llvm/Target/TargetMachine.h | 1 +
llvm/include/llvm/Target/TargetOptions.h | 7 +-
llvm/lib/CodeGen/Analysis.cpp | 10 +-
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 13 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 50 +++----
llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp | 2 +-
llvm/lib/CodeGen/LowLevelTypeUtils.cpp | 22 ++-
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 23 +--
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 +-
llvm/lib/CodeGen/TargetLoweringBase.cpp | 8 ++
llvm/lib/CodeGenTypes/LowLevelType.cpp | 35 +++--
llvm/lib/Support/TypeSize.cpp | 2 +-
.../AArch64/GISel/AArch64CallLowering.cpp | 4 +-
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 5 +-
.../Target/AMDGPU/AMDGPUCombinerHelper.cpp | 8 +-
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 17 +--
.../GlobalISel/GlobalISelMatchTable.cpp | 46 +++++-
22 files changed, 255 insertions(+), 148 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/Analysis.h b/llvm/include/llvm/CodeGen/Analysis.h
index 98b52579d03b7..2aadc27930b7a 100644
--- a/llvm/include/llvm/CodeGen/Analysis.h
+++ b/llvm/include/llvm/CodeGen/Analysis.h
@@ -101,7 +101,8 @@ inline void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL,
/// If Offsets is non-null, it points to a vector to be filled in
/// with the in-memory offsets of each of the individual values.
///
-void computeValueLLTs(const DataLayout &DL, Type &Ty,
+void computeValueLLTs(const TargetLowering &TLI,
+ const DataLayout &DL, Type &Ty,
SmallVectorImpl<LLT> &ValueTys,
SmallVectorImpl<uint64_t> *Offsets = nullptr,
uint64_t StartingOffset = 0);
diff --git a/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h b/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
index f0c1758a4c9cc..1c8f34b1a8518 100644
--- a/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
+++ b/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
@@ -27,7 +27,7 @@ class Type;
struct fltSemantics;
/// Construct a low-level type based on an LLVM type.
-LLVM_ABI LLT getLLTForType(Type &Ty, const DataLayout &DL);
+LLVM_ABI LLT getLLTForType(Type &Ty, const DataLayout &DL, bool AllowExtendedLLT = false);
/// Get a rough equivalent of an MVT for a given LLT. MVT can't distinguish
/// pointers, so these will convert to a plain integer.
@@ -36,7 +36,7 @@ LLVM_ABI EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx);
/// Get a rough equivalent of an LLT for a given MVT. LLT does not yet support
/// scalarable vector types, and will assert if used.
-LLVM_ABI LLT getLLTForMVT(MVT Ty);
+LLVM_ABI LLT getLLTForMVT(MVT Ty, bool AllowExtendedLLT = false);
/// Get the appropriate floating point arithmetic semantic based on the bit size
/// of the given scalar LLT.
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4480ced637456..f4fdd8c69ea9e 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -416,6 +416,9 @@ class LLVM_ABI TargetLoweringBase {
/// amounts, returns MVT::i32.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
+ virtual LLT getLLTForType(Type &Ty, const DataLayout &DL) const;
+ virtual LLT getLLTForMVT(MVT Ty) const;
+
/// Return the preferred type to use for a shift opcode, given the shifted
/// amount type is \p ShiftValueTy.
LLVM_READONLY
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 32572d6753c61..daec87ab536c0 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -30,7 +30,6 @@
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
#include <cassert>
namespace llvm {
@@ -52,13 +51,15 @@ class LLT {
};
enum class Kind : uint64_t {
- INVALID = 0b000,
- INTEGER = 0b001,
- FLOAT = 0b010,
- POINTER = 0b011,
- VECTOR_INTEGER = 0b101,
- VECTOR_FLOAT = 0b110,
- VECTOR_POINTER = 0b111,
+ INVALID = 0b0000,
+ ANY_SCALAR = 0b0001,
+ INTEGER = 0b0010,
+ FLOAT = 0b0011,
+ POINTER = 0b0100,
+ VECTOR_ANY = 0b0101,
+ VECTOR_INTEGER = 0b0110,
+ VECTOR_FLOAT = 0b0111,
+ VECTOR_POINTER = 0b1000,
};
constexpr static Kind toVector(Kind Ty) {
@@ -71,7 +72,7 @@ class LLT {
if (Ty == Kind::FLOAT)
return Kind::VECTOR_FLOAT;
- llvm_unreachable("Type is already a vector type");
+ return Kind::VECTOR_ANY;
}
constexpr static Kind toScalar(Kind Ty) {
@@ -84,13 +85,12 @@ class LLT {
if (Ty == Kind::VECTOR_FLOAT)
return Kind::FLOAT;
- llvm_unreachable("Type is already a scalar type");
+ return Kind::ANY_SCALAR;
}
/// Get a low-level scalar or aggregate "bag of bits".
- [[deprecated("Use LLT::integer(unsigned) instead.")]] static constexpr LLT
- scalar(unsigned SizeInBits) {
- return LLT{Kind::INTEGER, ElementCount::getFixed(0), SizeInBits,
+ static constexpr LLT scalar(unsigned SizeInBits) {
+ return LLT{Kind::ANY_SCALAR, ElementCount::getFixed(0), SizeInBits,
/*AddressSpace=*/0, static_cast<FPVariant>(0)};
}
@@ -106,7 +106,7 @@ class LLT {
/// Get a low-level token; just a scalar with zero bits (or no size).
static constexpr LLT token() {
- return LLT{Kind::INTEGER, ElementCount::getFixed(0),
+ return LLT{Kind::ANY_SCALAR, ElementCount::getFixed(0),
/*SizeInBits=*/0,
/*AddressSpace=*/0, static_cast<FPVariant>(0)};
}
@@ -119,10 +119,9 @@ class LLT {
}
/// Get a low-level vector of some number of elements and element width.
- [[deprecated("Use LLT::vector(EC, LLT) instead.")]] static constexpr LLT
- vector(ElementCount EC, unsigned ScalarSizeInBits) {
+ static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits) {
assert(!EC.isScalar() && "invalid number of vector elements");
- return LLT{Kind::VECTOR_INTEGER, EC, ScalarSizeInBits,
+ return LLT{Kind::VECTOR_ANY, EC, ScalarSizeInBits,
/*AddressSpace=*/0, static_cast<FPVariant>(0)};
}
@@ -179,11 +178,9 @@ class LLT {
/// Get a low-level fixed-width vector of some number of elements and element
/// width.
- [[deprecated(
- "Use LLT::fixed_vector(unsigned, LLT) instead.")]] static constexpr LLT
- fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits) {
+ static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits) {
return vector(ElementCount::getFixed(NumElements),
- LLT::integer(ScalarSizeInBits));
+ LLT::scalar(ScalarSizeInBits));
}
/// Get a low-level fixed-width vector of some number of elements and element
@@ -194,11 +191,9 @@ class LLT {
/// Get a low-level scalable vector of some number of elements and element
/// width.
- [[deprecated(
- "Use LLT::scalable_vector(unsigned, LLT) instead.")]] static constexpr LLT
- scalable_vector(unsigned MinNumElements, unsigned ScalarSizeInBits) {
+ static constexpr LLT scalable_vector(unsigned MinNumElements, unsigned ScalarSizeInBits) {
return vector(ElementCount::getScalable(MinNumElements),
- LLT::integer(ScalarSizeInBits));
+ LLT::scalar(ScalarSizeInBits));
}
/// Get a low-level scalable vector of some number of elements and element
@@ -211,12 +206,10 @@ class LLT {
return EC.isScalar() ? ScalarTy : LLT::vector(EC, ScalarTy);
}
- [[deprecated(
- "Use LLT::scalarOrVector(EC, LLT) instead.")]] static constexpr LLT
- scalarOrVector(ElementCount EC, uint64_t ScalarSize) {
+ static constexpr LLT scalarOrVector(ElementCount EC, uint64_t ScalarSize) {
assert(ScalarSize <= std::numeric_limits<unsigned>::max() &&
"Not enough bits in LLT to represent size");
- return scalarOrVector(EC, LLT::integer(static_cast<unsigned>(ScalarSize)));
+ return scalarOrVector(EC, LLT::scalar(static_cast<unsigned>(ScalarSize)));
}
explicit constexpr LLT(Kind Info, ElementCount EC, uint64_t SizeInBits,
@@ -225,11 +218,11 @@ class LLT {
init(Info, EC, SizeInBits, AddressSpace, FP);
}
- LLVM_ABI explicit LLT(MVT VT);
+ LLVM_ABI explicit LLT(MVT VT, bool AllowExtendedLLT = false);
explicit constexpr LLT() : Info(static_cast<Kind>(0)), RawData(0) {}
constexpr bool isValid() const { return isToken() || RawData != 0; }
- constexpr bool isScalar() const { return Info == Kind::INTEGER || Info == Kind::FLOAT; }
+ constexpr bool isScalar() const { return Info == Kind::ANY_SCALAR || Info == Kind::INTEGER || Info == Kind::FLOAT; }
constexpr bool isScalar(unsigned Size) const {
return isScalar() && getScalarSizeInBits() == Size;
}
@@ -262,7 +255,13 @@ class LLT {
return isVariantFloat(128, FPVariant::VARIANT_FLOAT_2);
}
constexpr bool isToken() const {
- return Info == Kind::INTEGER && RawData == 0;
+ return Info == Kind::ANY_SCALAR && RawData == 0;
+ }
+ constexpr bool isAnyScalar() const {
+ return isValid() && Info == Kind::ANY_SCALAR;
+ }
+ constexpr bool isVectorAny() const {
+ return isVector() && Info == Kind::VECTOR_ANY;
}
constexpr bool isInteger() const {
return isValid() && Info == Kind::INTEGER;
@@ -275,8 +274,8 @@ class LLT {
}
constexpr bool isVector() const {
return isValid() &&
- (Info == Kind::VECTOR_INTEGER || Info == Kind::VECTOR_FLOAT ||
- Info == Kind::VECTOR_POINTER);
+ (Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER||
+ Info == Kind::VECTOR_FLOAT || Info == Kind::VECTOR_POINTER);
}
constexpr bool isPointer() const {
return isValid() && Info == Kind::POINTER;
@@ -367,8 +366,12 @@ class LLT {
constexpr LLT changeElementSize(unsigned NewEltSize) const {
assert(!isPointerOrPointerVector() && !(isFloat() || isFloatVector()) &&
"invalid to directly change element size for pointers");
- return isVector() ? LLT::vector(getElementCount(), LLT::integer(NewEltSize))
- : LLT::integer(NewEltSize);
+ return isVector()
+ ? LLT::vector(getElementCount(), getElementType().isInteger()
+ ? LLT::integer(NewEltSize)
+ : LLT::scalar(NewEltSize))
+ : isInteger() ? LLT::integer(NewEltSize)
+ : LLT::scalar(NewEltSize);
}
/// Return a vector or scalar with the same element type and the new element
@@ -395,7 +398,10 @@ class LLT {
}
assert(getScalarSizeInBits() % Factor == 0);
- return integer(getScalarSizeInBits() / Factor);
+ if (isInteger())
+ return integer(getScalarSizeInBits() / Factor);
+
+ return scalar(getScalarSizeInBits() / Factor);
}
/// Produce a vector type that is \p Factor times bigger, preserving the
@@ -435,7 +441,10 @@ class LLT {
if (isFloatVector())
return floatingPoint(getScalarSizeInBits(), getFPVariant());
- return integer(getScalarSizeInBits());
+ if (isIntegerVector())
+ return integer(getScalarSizeInBits());
+
+ return scalar(getScalarSizeInBits());
}
constexpr LLT changeToInteger() const {
@@ -455,6 +464,13 @@ class LLT {
#endif
constexpr bool operator==(const LLT &RHS) const {
+ if (isAnyScalar() || RHS.isAnyScalar()) {
+ return isScalar() == RHS.isScalar() && RawData == RHS.RawData;
+ }
+ if (isVector() && RHS.isVector()) {
+ return getElementType() == RHS.getElementType() &&
+ getElementCount() == RHS.getElementCount();
+ }
return Info == RHS.Info && RawData == RHS.RawData;
}
@@ -465,8 +481,8 @@ class LLT {
private:
/// LLT is packed into 64 bits as follows:
- /// Info : 3
- /// RawData : 61
+ /// Info : 4
+ /// RawData : 60
/// with 61 bits of RawData remaining for Kind-specific data, packed in
/// bitfields as described below. As there isn't a simple portable way to pack
/// bits into bitfields, here the different fields in the packed structure is
@@ -480,13 +496,13 @@ class LLT {
63 56 47 39 31 23 15 7 0
| | | | | | | | |
|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|
- ................................... (1)
- ***************** (2)
- ~~~~~~~~~~~~~~~~~~~~~~~~~~ (3)
- ^^^^^^^^^^^^^^^^^ (4)
- @ (5)
+ ........ ........ ........ ........ (1)
+ ******** ******** (2)
+ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ (3)
+ ^^^^^^^^ ^^^^^^^^ (4)
+ @ (5)
### (6)
- %%% (7)
+ %%%% (7)
(1) ScalarSize (2) PointerSize (3) PointerAddressSpace
(4) VectorElements (5) VectorScalable (6) FPVariant (7) Kind
@@ -500,18 +516,20 @@ class LLT {
/// valid encodings, SizeInBits/SizeOfElement must be larger than 0.
/// * Non-pointer scalar (isPointer == 0 && isVector == 0):
/// SizeInBits: 32;
- static const constexpr BitFieldInfo ScalarSizeFieldInfo{32, 29};
- static const constexpr BitFieldInfo FPFieldInfo{3, 21};
+ /// FPInfoField: 3;
+ static const constexpr BitFieldInfo ScalarSizeFieldInfo{32, 28};
+ static const constexpr BitFieldInfo FPFieldInfo{3, 20};
/// * Pointer (isPointer == 1 && isVector == 0):
/// SizeInBits: 16;
/// AddressSpace: 24;
- static const constexpr BitFieldInfo PointerSizeFieldInfo{16, 45};
- static const constexpr BitFieldInfo PointerAddressSpaceFieldInfo{24, 21};
+ static const constexpr BitFieldInfo PointerSizeFieldInfo{16, 44};
+ static const constexpr BitFieldInfo PointerAddressSpaceFieldInfo{24, 20};
/// * Vector-of-non-pointer (isPointer == 0 && isVector == 1):
/// NumElements: 16;
/// SizeOfElement: 32;
+ /// FPInfoField: 3;
/// Scalable: 1;
- static const constexpr BitFieldInfo VectorElementsFieldInfo{16, 5};
+ static const constexpr BitFieldInfo VectorElementsFieldInfo{16, 4};
static const constexpr BitFieldInfo VectorScalableFieldInfo{1, 0};
/// * Vector-of-pointer (isPointer == 1 && isVector == 1):
/// NumElements: 16;
@@ -519,8 +537,8 @@ class LLT {
/// AddressSpace: 24;
/// Scalable: 1;
- Kind Info : 3;
- uint64_t RawData : 61;
+ Kind Info : 4;
+ uint64_t RawData : 60;
static constexpr uint64_t getMask(const BitFieldInfo FieldInfo) {
const int FieldSizeInBits = FieldInfo[0];
@@ -553,8 +571,8 @@ class LLT {
maskAndShift((uint64_t)FP, FPFieldInfo);
}
- if (Info == Kind::VECTOR_INTEGER || Info == Kind::VECTOR_FLOAT ||
- Info == Kind::VECTOR_POINTER) {
+ if (Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER ||
+ Info == Kind::VECTOR_FLOAT || Info == Kind::VECTOR_POINTER) {
RawData |= maskAndShift(EC.getKnownMinValue(), VectorElementsFieldInfo) |
maskAndShift(EC.isScalable() ? 1 : 0, VectorScalableFieldInfo);
}
@@ -562,7 +580,7 @@ class LLT {
public:
constexpr uint64_t getUniqueRAWLLTData() const {
- return ((uint64_t)RawData) << 3 | ((uint64_t)Info);
+ return ((uint64_t)RawData) << 4 | ((uint64_t)Info);
}
};
@@ -574,12 +592,12 @@ inline raw_ostream& operator<<(raw_ostream &OS, const LLT &Ty) {
template <> struct DenseMapInfo<LLT> {
static inline LLT getEmptyKey() {
LLT Invalid;
- Invalid.Info = static_cast<LLT::Kind>(2);
+ Invalid.Info = LLT::Kind::POINTER;
return Invalid;
}
static inline LLT getTombstoneKey() {
LLT Invalid;
- Invalid.Info = static_cast<LLT::Kind>(3);
+ Invalid.Info = LLT::Kind::VECTOR_ANY;
return Invalid;
}
static inline unsigned getHashValue(const LLT &Ty) {
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index bf4e490554723..5671318a8586d 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -295,6 +295,7 @@ class LLVM_ABI TargetMachine {
bool getO0WantsFastISel() { return O0WantsFastISel; }
void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; }
void setGlobalISel(bool Enable) { Options.EnableGlobalISel = Enable; }
+ void setGlobalISelExtendedLLT(bool Enable) { Options.EnableGlobalISelExtendedLLT = Enable; }
void setGlobalISelAbort(GlobalISelAbortMode Mode) {
Options.GlobalISelAbort = Mode;
}
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index db90f2e4cc7cc..839412cd151bf 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -123,7 +123,8 @@ class TargetOptions {
ApproxFuncFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
+ EnableFastISel(false), EnableGlobalISel(false),
+ EnableGlobalISelExtendedLLT(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -235,6 +236,10 @@ class TargetOptions {
/// EnableGlobalISel - This flag enables global instruction selection.
unsigned EnableGlobalISel : 1;
+ /// EnableGlobalISelExtendedLLT - This flag enables LLTs with extenden type info
+ /// so target may distinguish different formats of equal sized scalars.
+ unsigned EnableGlobalISelExtendedLLT : 1;
+
/// EnableGlobalISelAbort - Control abort behaviour when global instruction
/// selection fails to lower/select an instruction.
GlobalISelAbortMode GlobalISelAbort = GlobalISelAbortMode::Enable;
diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp
index 2ef96cc4400f7..61d509db7f14a 100644
--- a/llvm/lib/CodeGen/Analysis.cpp
+++ b/llvm/lib/CodeGen/Analysis.cpp
@@ -146,8 +146,8 @@ void llvm::ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL,
}
}
-void llvm::computeValueLLTs(const DataLayout &DL, Type &Ty,
- SmallVectorImpl<LLT> &ValueTys,
+void llvm::computeValueLLTs(const TargetLowering &TLI, const DataLayout &DL,
+ Type &Ty, SmallVectorImpl<LLT> &ValueTys,
SmallVectorImpl<uint64_t> *Offsets,
uint64_t StartingOffset) {
// Given a struct type, recursively traverse the elements.
@@ -158,7 +158,7 @@ void llvm::computeValueLLTs(const DataLayout &DL, Type &Ty,
const StructLayout *SL = Offsets ? DL.getStructLayout(STy) : nullptr;
for (unsigned I = 0, E = STy->getNumElements(); I != E; ++I) {
uint64_t EltOffset = SL ? SL->getElementOffset(I) : 0;
- computeValueLLTs(DL, *STy->getElementType(I), ValueTys, Offsets,
+ computeValueLLTs(TLI, DL, *STy->getElementType(I), ValueTys, Offsets,
StartingOffset + EltOffset);
}
return;
@@ -168,7 +168,7 @@ void llvm::computeValueLLTs(const DataLayout &DL, Type &Ty,
Type *EltTy = ATy->getElementType();
uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue();
for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
- computeValueLLTs(DL, *EltTy, ValueTys, Offsets,
+ computeValueLLTs(TLI, DL, *EltTy, ValueTys, Offsets,
StartingOffset + i * EltSize);
return;
}
@@ -176,7 +176,7 @@ void llvm::computeValueLLTs(const DataLayout &DL, Type &Ty,
if (Ty.isVoidTy())
return;
// Base case: we can get an LLT for this LLVM IR type.
- ValueTys.push_back(getLLTForType(Ty, DL));
+ ValueTys.push_back(TLI.getLLTForType(Ty, DL));
if (Offsets != nullptr)
Offsets->push_back(StartingOffset * 8);
}
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 90a18b86c1b1f..41609dae1b156 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -159,7 +159,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
if (const Function *F = dyn_cast<Function>(CalleeV)) {
if (F->hasFnAttribute(Attribute::NonLazyBind)) {
- LLT Ty = getLLTForType(*F->getType(), DL);
+ LLT Ty = TLI->getLLTForType(*F->getType(), DL);
Register Reg = MIRBuilder.buildGlobalValue(Ty, F).getReg(0);
Info.Callee = MachineOperand::CreateReg(Reg, false);
} else {
@@ -781,11 +781,11 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
const MVT ValVT = VA.getValVT();
const MVT LocVT = VA.getLocVT();
- const LLT LocTy(LocVT);
- const LLT ValTy(ValVT);
+ const LLT LocTy = TLI->getLLTForMVT(LocVT);
+ const LLT ValTy = TLI->getLLTForMVT(ValVT);
const LLT NewLLT = Handler.isIncomingArgumentHandler() ? LocTy : ValTy;
const EVT OrigVT = EVT::getEVT(Args[i].Ty);
- const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
+ const LLT OrigTy = TLI->getLLTForType(*Args[i].Ty, DL);
const LLT PointerTy = LLT::pointer(
AllocaAddressSpace, DL.getPointerSizeInBits(AllocaAddressSpace));
@@ -1004,7 +1004,7 @@ void CallLowering::insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy,
Align BaseAlign = DL.getPrefTypeAlign(RetTy);
Type *RetPtrTy =
PointerType::get(RetTy->getContext(), DL.getAllocaAddrSpace());
- LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetPtrTy), DL);
+ LLT OffsetLLTy = TLI->getLLTForType(*DL.getIndexType(RetPtrTy), DL);
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
@@ -1035,7 +1035,8 @@ void CallLowering::insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy,
unsigned NumValues = SplitVTs.size();
Align BaseAlign = DL.getPrefTypeAlign(RetTy);
unsigned AS = DL.getAllocaAddrSpace();
- LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetTy->getContext(), AS), DL);
+ LLT OffsetLLTy =
+ TLI->getLLTForType(*DL.getIndexType(RetTy->getContext(), AS), DL);
MachinePointerInfo PtrInfo(AS);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 8424a8108d76e..4484a0769ad2a 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -193,7 +193,7 @@ IRTranslator::allocateVRegs(const Value &Val) {
auto *Regs = VMap.getVRegs(Val);
auto *Offsets = VMap.getOffsets(Val);
SmallVector<LLT, 4> SplitTys;
- computeValueLLTs(*DL, *Val.getType(), SplitTys,
+ computeValueLLTs(*TLI, *DL, *Val.getType(), SplitTys,
Offsets->empty() ? Offsets : nullptr);
for (unsigned i = 0; i < SplitTys.size(); ++i)
Regs->push_back(0);
@@ -217,7 +217,7 @@ ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
"Don't know how to create an empty vreg");
SmallVector<LLT, 4> SplitTys;
- computeValueLLTs(*DL, *Val.getType(), SplitTys,
+ computeValueLLTs(*TLI, *DL, *Val.getType(), SplitTys,
Offsets->empty() ? Offsets : nullptr);
if (!isa<Constant>(Val)) {
@@ -858,7 +858,7 @@ void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
MIB.setDebugLoc(CurBuilder->getDebugLoc());
Type *PtrIRTy = PointerType::getUnqual(MF->getFunction().getContext());
- const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
+ const LLT PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
auto Table = MIB.buildJumpTable(PtrTy, JT.JTI);
MIB.buildBrJT(Table.getReg(0), JT.JTI, JT.Reg);
@@ -873,7 +873,7 @@ bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
const Value &SValue = *JTH.SValue;
// Subtract the lowest switch case value from the value being switched on.
- const LLT SwitchTy = getLLTForType(*SValue.getType(), *DL);
+ const LLT SwitchTy = TLI->getLLTForType(*SValue.getType(), *DL);
Register SwitchOpReg = getOrCreateVReg(SValue);
auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First);
auto Sub = MIB.buildSub({SwitchTy}, SwitchOpReg, FirstCst);
@@ -1106,7 +1106,7 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
auto RangeSub = MIB.buildSub(SwitchOpTy, SwitchOpReg, MinValReg);
Type *PtrIRTy = PointerType::getUnqual(MF->getFunction().getContext());
- const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
+ const LLT PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
LLT MaskTy = SwitchOpTy;
if (MaskTy.getSizeInBits() > PtrTy.getSizeInBits() ||
@@ -1159,7 +1159,7 @@ void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB,
MachineIRBuilder &MIB = *CurBuilder;
MIB.setMBB(*SwitchBB);
- LLT SwitchTy = getLLTForMVT(BB.RegVT);
+ LLT SwitchTy = TLI->getLLTForMVT(BB.RegVT);
Register Cmp;
unsigned PopCount = llvm::popcount(B.Mask);
if (PopCount == 1) {
@@ -1386,7 +1386,7 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
const Value *Ptr = LI.getPointerOperand();
Type *OffsetIRTy = DL->getIndexType(Ptr->getType());
- LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
+ LLT OffsetTy = TLI->getLLTForType(*OffsetIRTy, *DL);
if (CLI->supportSwiftError() && isSwiftError(Ptr)) {
assert(Regs.size() == 1 && "swifterror should be single pointer");
@@ -1433,7 +1433,7 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
Register Base = getOrCreateVReg(*SI.getPointerOperand());
Type *OffsetIRTy = DL->getIndexType(SI.getPointerOperandType());
- LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
+ LLT OffsetTy = TLI->getLLTForType(*OffsetIRTy, *DL);
if (CLI->supportSwiftError() && isSwiftError(SI.getPointerOperand())) {
assert(Vals.size() == 1 && "swifterror should be single pointer");
@@ -1555,8 +1555,8 @@ bool IRTranslator::translateCopy(const User &U, const Value &V,
bool IRTranslator::translateBitCast(const User &U,
MachineIRBuilder &MIRBuilder) {
// If we're bitcasting to the source type, we can reuse the source vreg.
- if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
- getLLTForType(*U.getType(), *DL)) {
+ if (TLI->getLLTForType(*U.getOperand(0)->getType(), *DL) ==
+ TLI->getLLTForType(*U.getType(), *DL)) {
// If the source is a ConstantInt then it was probably created by
// ConstantHoisting and we should leave it alone.
if (isa<ConstantInt>(U.getOperand(0)))
@@ -1588,9 +1588,9 @@ bool IRTranslator::translateGetElementPtr(const User &U,
Value &Op0 = *U.getOperand(0);
Register BaseReg = getOrCreateVReg(Op0);
Type *PtrIRTy = Op0.getType();
- LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
+ LLT PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
Type *OffsetIRTy = DL->getIndexType(PtrIRTy);
- LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
+ LLT OffsetTy = TLI->getLLTForType(*OffsetIRTy, *DL);
uint32_t PtrAddFlags = 0;
// Each PtrAdd generated to implement the GEP inherits its nuw, nusw, inbounds
@@ -1627,9 +1627,9 @@ bool IRTranslator::translateGetElementPtr(const User &U,
BaseReg)
.getReg(0);
PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth);
- PtrTy = getLLTForType(*PtrIRTy, *DL);
+ PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
OffsetIRTy = DL->getIndexType(PtrIRTy);
- OffsetTy = getLLTForType(*OffsetIRTy, *DL);
+ OffsetTy = TLI->getLLTForType(*OffsetIRTy, *DL);
}
int64_t Offset = 0;
@@ -1679,7 +1679,7 @@ bool IRTranslator::translateGetElementPtr(const User &U,
Register GepOffsetReg;
if (ElementSize != 1) {
auto ElementSizeMIB = MIRBuilder.buildConstant(
- getLLTForType(*OffsetIRTy, *DL), ElementSize);
+ TLI->getLLTForType(*OffsetIRTy, *DL), ElementSize);
// The multiplication is NUW if the GEP is NUW and NSW if the GEP is
// NUSW.
@@ -2336,7 +2336,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
MIRBuilder.buildFMA(Dst, Op0, Op1, Op2,
MachineInstr::copyFlagsFromInstruction(CI));
} else {
- LLT Ty = getLLTForType(*CI.getType(), *DL);
+ LLT Ty = TLI->getLLTForType(*CI.getType(), *DL);
auto FMul = MIRBuilder.buildFMul(
Ty, Op0, Op1, MachineInstr::copyFlagsFromInstruction(CI));
MIRBuilder.buildFAdd(Dst, FMul, Op2,
@@ -2403,7 +2403,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
getStackGuard(getOrCreateVReg(CI), MIRBuilder);
return true;
case Intrinsic::stackprotector: {
- LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
+ LLT PtrTy = TLI->getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
Register GuardVal;
if (TLI->useLoadStackGuardNode(*CI.getModule())) {
GuardVal = MRI->createGenericVirtualRegister(PtrTy);
@@ -2650,7 +2650,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::vector_deinterleave2: {
// Both intrinsics have at least one operand.
Value *Op0 = CI.getOperand(0);
- LLT ResTy = getLLTForType(*Op0->getType(), MIRBuilder.getDataLayout());
+ LLT ResTy = TLI->getLLTForType(*Op0->getType(), MIRBuilder.getDataLayout());
if (!ResTy.isFixedVector())
return false;
@@ -2700,7 +2700,7 @@ bool IRTranslator::translateCallBase(const CallBase &CB,
for (const auto &Arg : CB.args()) {
if (CLI->supportSwiftError() && isSwiftError(Arg)) {
assert(SwiftInVReg == 0 && "Expected only one swift error argument");
- LLT Ty = getLLTForType(*Arg->getType(), *DL);
+ LLT Ty = TLI->getLLTForType(*Arg->getType(), *DL);
SwiftInVReg = MRI->createGenericVirtualRegister(Ty);
MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt(
&CB, &MIRBuilder.getMBB(), Arg));
@@ -2852,7 +2852,7 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
Align Alignment = Info.align.value_or(
DL->getABITypeAlign(Info.memVT.getTypeForEVT(F->getContext())));
LLT MemTy = Info.memVT.isSimple()
- ? getLLTForMVT(Info.memVT.getSimpleVT())
+ ? TLI->getLLTForMVT(Info.memVT.getSimpleVT())
: LLT::scalar(Info.memVT.getStoreSizeInBits());
// TODO: We currently just fallback to address space 0 if getTgtMemIntrinsic
@@ -3060,13 +3060,13 @@ bool IRTranslator::translateLandingPad(const User &U,
if (auto *RegMask = TRI.getCustomEHPadPreservedMask(*MF))
MF->getRegInfo().addPhysRegsUsedFromRegMask(RegMask);
- LLT Ty = getLLTForType(*LP.getType(), *DL);
+ LLT Ty = TLI->getLLTForType(*LP.getType(), *DL);
Register Undef = MRI->createGenericVirtualRegister(Ty);
MIRBuilder.buildUndef(Undef);
SmallVector<LLT, 2> Tys;
for (Type *Ty : cast<StructType>(LP.getType())->elements())
- Tys.push_back(getLLTForType(*Ty, *DL));
+ Tys.push_back(TLI->getLLTForType(*Ty, *DL));
assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
// Mark exception register as live in.
@@ -3111,7 +3111,7 @@ bool IRTranslator::translateAlloca(const User &U,
// Now we're in the harder dynamic case.
Register NumElts = getOrCreateVReg(*AI.getArraySize());
Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
- LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
+ LLT IntPtrTy = TLI->getLLTForType(*IntPtrIRTy, *DL);
if (MRI->getType(NumElts) != IntPtrTy) {
Register ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
@@ -3854,8 +3854,8 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
CurBuilder->setInsertPt(*ParentBB, ParentBB->end());
// First create the loads to the guard/stack slot for the comparison.
Type *PtrIRTy = PointerType::getUnqual(MF->getFunction().getContext());
- const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
- LLT PtrMemTy = getLLTForMVT(TLI->getPointerMemTy(*DL));
+ const LLT PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
+ LLT PtrMemTy = TLI->getLLTForMVT(TLI->getPointerMemTy(*DL));
MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
int FI = MFI.getStackProtectorIndex();
diff --git a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
index b2f84351c9a95..b1e134ce5ef9e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
@@ -952,7 +952,7 @@ void LoadStoreOpt::initializeStoreMergeTargetInfo(unsigned AddrSpace) {
const auto &LI = *MF->getSubtarget().getLegalizerInfo();
const auto &DL = MF->getFunction().getDataLayout();
Type *IRPtrTy = PointerType::get(MF->getFunction().getContext(), AddrSpace);
- LLT PtrTy = getLLTForType(*IRPtrTy, DL);
+ LLT PtrTy = TLI->getLLTForType(*IRPtrTy, DL);
// We assume that we're not going to be generating any stores wider than
// MaxStoreSizeToForm bits for now.
for (unsigned Size = 2; Size <= MaxStoreSizeToForm; Size *= 2) {
diff --git a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
index cf34bf71a8c3a..6a15b1748630d 100644
--- a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
+++ b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
@@ -17,16 +17,16 @@
#include "llvm/IR/DerivedTypes.h"
using namespace llvm;
-LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) {
- if (auto VTy = dyn_cast<VectorType>(&Ty)) {
+LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL, bool AllowExtendedLLT) {
+ if (auto *VTy = dyn_cast<VectorType>(&Ty)) {
auto EC = VTy->getElementCount();
- LLT ScalarTy = getLLTForType(*VTy->getElementType(), DL);
+ LLT ScalarTy = getLLTForType(*VTy->getElementType(), DL, AllowExtendedLLT);
if (EC.isScalar())
return ScalarTy;
return LLT::vector(EC, ScalarTy);
}
- if (auto PTy = dyn_cast<PointerType>(&Ty)) {
+ if (auto *PTy = dyn_cast<PointerType>(&Ty)) {
unsigned AddrSpace = PTy->getAddressSpace();
return LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace));
}
@@ -37,6 +37,11 @@ LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) {
auto SizeInBits = DL.getTypeSizeInBits(&Ty);
assert(SizeInBits != 0 && "invalid zero-sized type");
+ // Return simple scalar
+ if (!AllowExtendedLLT)
+ return LLT::scalar(SizeInBits);
+
+ // Choose more precise LLT variant
if (Ty.isFloatingPointTy()) {
if (Ty.isHalfTy())
return LLT::float16();
@@ -66,7 +71,7 @@ LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) {
return LLT::integer(SizeInBits);
}
- return LLT::integer(SizeInBits);
+ return LLT::scalar(SizeInBits);
}
if (Ty.isTokenTy())
@@ -106,10 +111,13 @@ EVT llvm::getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx) {
return EVT::getIntegerVT(Ctx, Ty.getSizeInBits());
}
-LLT llvm::getLLTForMVT(MVT Ty) { return LLT(Ty); }
+LLT llvm::getLLTForMVT(MVT VT, bool AllowExtendedLLT) {
+ return LLT(VT, AllowExtendedLLT);
+}
const llvm::fltSemantics &llvm::getFltSemanticForLLT(LLT Ty) {
- assert(Ty.isFloat() && "Expected a scalar type.");
+ assert((Ty.isAnyScalar() || Ty.isFloat()) &&
+ "Expected a any scalar or float type.");
if (Ty.isBFloat(16))
return APFloat::BFloat();
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index b0cd260fadd7e..699f4d3529b6e 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1934,10 +1934,11 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
TypeDigits.consume_front("f") || TypeDigits.consume_front("p") ||
TypeDigits.consume_front("bf")) {
if (TypeDigits.empty() || !llvm::all_of(TypeDigits, isdigit))
- return error("expected integers after 's'/'i'/'f'/'bf'/'p' type prefix");
+ return error("expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
}
if (Token.range().starts_with("s") || Token.range().starts_with("i")) {
+ bool ScalarOrInt = Token.range().starts_with("s");
auto ScalarSize = APSInt(TypeDigits).getZExtValue();
if (!ScalarSize) {
Ty = LLT::token();
@@ -1948,7 +1949,7 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
if (!verifyScalarSize(ScalarSize))
return error("invalid size for scalar type");
- Ty = LLT::integer(ScalarSize);
+ Ty = ScalarOrInt ? LLT::scalar(ScalarSize) : LLT::integer(ScalarSize);
lex();
return false;
}
@@ -1983,8 +1984,9 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
// Now we're looking for a vector.
if (Token.isNot(MIToken::less))
- return error(Loc, "expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, "
- "or <vscale x M x pA> for GlobalISel type");
+ return error(Loc, "expected tN, pA, <M x tN>, <M x pA>, <vscale x M x tN>, "
+ "or <vscale x M x pA> for GlobalISel type, "
+ "where t = {'s', 'i', 'f', 'bf'}");
lex();
bool HasVScale =
@@ -1992,15 +1994,15 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
if (HasVScale) {
lex();
if (Token.isNot(MIToken::Identifier) || Token.stringValue() != "x")
- return error("expected <vscale x M x sN> or <vscale x M x pA>");
+ return error("expected <vscale x M x tN>, where t = {'s', 'i', 'f', 'bf', 'p'}");
lex();
}
auto GetError = [this, &HasVScale, Loc]() {
if (HasVScale)
return error(
- Loc, "expected <vscale x M x sN> or <vscale M x pA> for vector type");
- return error(Loc, "expected <M x sN> or <M x pA> for vector type");
+ Loc, "expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}");
+ return error(Loc, "expected <M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}");
};
if (Token.isNot(MIToken::IntegerLiteral))
@@ -2027,10 +2029,11 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
"expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
if (Token.range().starts_with("s") || Token.range().starts_with("i")) {
+ bool ScalarOrInt = Token.range().starts_with("s");
auto ScalarSize = APSInt(VectorTyDigits).getZExtValue();
if (!verifyScalarSize(ScalarSize))
return error("invalid size for scalar element in vector");
- Ty = LLT::integer(ScalarSize);
+ Ty = ScalarOrInt ? LLT::scalar(ScalarSize) : LLT::integer(ScalarSize);
} else if (Token.range().starts_with("p")) {
const DataLayout &DL = MF.getDataLayout();
uint64_t AS = APSInt(VectorTyDigits).getZExtValue();
@@ -2068,9 +2071,9 @@ bool MIParser::parseTypedImmediateOperand(MachineOperand &Dest) {
!TypeDigits.consume_front("p") && !TypeDigits.consume_front("f") &&
!TypeDigits.consume_front("bf"))
return error("a typed immediate operand should start with one of 'i', "
- "'s','f','bf', or 'p'");
+ "'s', 'f', 'bf', or 'p'");
if (TypeDigits.empty() || !llvm::all_of(TypeDigits, isdigit))
- return error("expected integers after 'i'/'s'/'f'/'bf'/'p' type character");
+ return error("expected integers after 'i'/'s'/'f'/'bf'/'p' type identifier");
auto Loc = Token.location();
lex();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index ece50ed95fc49..ca75c42ee0a72 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2457,7 +2457,7 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
const MDString *RegStr = cast<MDString>(MD->getMD()->getOperand(0));
EVT VT = Op->getValueType(0);
- LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
+ LLT Ty = VT.isSimple() ? TLI->getLLTForMVT(VT.getSimpleVT()) : LLT();
const MachineFunction &MF = CurDAG->getMachineFunction();
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
@@ -2488,7 +2488,7 @@ void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
const MDString *RegStr = cast<MDString>(MD->getMD()->getOperand(0));
EVT VT = Op->getOperand(2).getValueType();
- LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
+ LLT Ty = VT.isSimple() ? TLI->getLLTForMVT(VT.getSimpleVT()) : LLT();
const MachineFunction &MF = CurDAG->getMachineFunction();
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 350948a92a3ae..ee95f9ea05c02 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -978,6 +978,14 @@ EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
return ShiftVT;
}
+LLT TargetLoweringBase::getLLTForType(Type &Ty, const DataLayout &DL) const {
+ return llvm::getLLTForType(Ty, DL, TM.Options.EnableGlobalISelExtendedLLT);
+}
+
+LLT TargetLoweringBase::getLLTForMVT(MVT Ty) const {
+ return llvm::getLLTForMVT(Ty, TM.Options.EnableGlobalISelExtendedLLT);
+}
+
bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
assert(isTypeLegal(VT));
switch (Op) {
diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index 925b4efaf0edf..35329793bd508 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -32,30 +32,47 @@ static std::optional<LLT::FPVariant> deriveFPInfo(MVT VT) {
}
}
-LLT::LLT(MVT VT) {
+LLT::LLT(MVT VT, bool AllowExtendedLLT) {
+ if (!AllowExtendedLLT) {
+ if (VT.isVector()) {
+ bool AsVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector();
+ Kind Info = AsVector ? Kind::VECTOR_ANY : Kind::ANY_SCALAR;
+ init(Info, VT.getVectorElementCount(),
+ VT.getVectorElementType().getSizeInBits(), 0, FPVariant::IEEE_FLOAT);
+ } else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
+ init(Kind::ANY_SCALAR, ElementCount::getFixed(0), VT.getSizeInBits(), 0,
+ FPVariant::IEEE_FLOAT);
+ } else {
+ this->Info = Kind::INVALID;
+ this->RawData = 0;
+ }
+ return;
+ }
+
auto FP = deriveFPInfo(VT);
bool AsVector = VT.isVector() &&
(VT.getVectorMinNumElements() > 1 || VT.isScalableVector());
- Kind Info;
+ LLT::Kind Info;
if (FP.has_value())
- Info = AsVector ? Kind::VECTOR_FLOAT : Kind::FLOAT;
+ Info = AsVector ? LLT::Kind::VECTOR_FLOAT : LLT::Kind::FLOAT;
else
- Info = AsVector ? Kind::VECTOR_INTEGER : Kind::INTEGER;
+ Info = AsVector ? LLT::Kind::VECTOR_INTEGER : LLT::Kind::INTEGER;
if (VT.isVector()) {
init(Info, VT.getVectorElementCount(),
- VT.getVectorElementType().getSizeInBits(),
- /*AddressSpace=*/0, FP.value_or(FPVariant::IEEE_FLOAT));
+ VT.getVectorElementType().getSizeInBits(), 0,
+ FP.value_or(LLT::FPVariant::IEEE_FLOAT));
} else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
// Aggregates are no different from real scalars as far as GlobalISel is
// concerned.
- init(Info, ElementCount::getFixed(0), VT.getSizeInBits(),
- /*AddressSpace=*/0, FP.value_or(FPVariant::IEEE_FLOAT));
+ init(Info, ElementCount::getFixed(0), VT.getSizeInBits(), 0,
+ FP.value_or(LLT::FPVariant::IEEE_FLOAT));
} else {
- this->Info = static_cast<Kind>(0);
+ this->Info = Kind::INVALID;
this->RawData = 0;
}
+ return;
}
void LLT::print(raw_ostream &OS) const {
diff --git a/llvm/lib/Support/TypeSize.cpp b/llvm/lib/Support/TypeSize.cpp
index 43346b81cd676..a96fced8eff30 100644
--- a/llvm/lib/Support/TypeSize.cpp
+++ b/llvm/lib/Support/TypeSize.cpp
@@ -44,7 +44,7 @@ void llvm::reportInvalidSizeRequest(const char *Msg) {
return;
}
#endif
- report_fatal_error("Invalid size request on a scalable vector.");
+ report_fatal_error(Twine("Invalid size request on a scalable vector.") + Msg);
}
TypeSize::operator TypeSize::ScalarTy() const {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 79bef76cf4c4f..c897a0f65084f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -457,7 +457,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
ExtendOp = TargetOpcode::G_ZEXT;
LLT NewLLT(NewVT);
- LLT OldLLT = getLLTForType(*CurArgInfo.Ty, DL);
+ LLT OldLLT = TLI.getLLTForType(*CurArgInfo.Ty, DL);
CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
// Instead of an extend, we might have a vector type which needs
// padding with more elements, e.g. <2 x half> -> <4 x half>.
@@ -1397,7 +1397,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// is set.
if (Info.Callee.isSymbol() && F.getParent()->getRtLibUseGOT()) {
auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_GLOBAL_VALUE);
- DstOp(getLLTForType(*F.getType(), DL)).addDefToMIB(MRI, MIB);
+ DstOp(TLI.getLLTForType(*F.getType(), DL)).addDefToMIB(MRI, MIB);
MIB.addExternalSymbol(Info.Callee.getSymbolName(), AArch64II::MO_GOT);
Info.Callee = MachineOperand::CreateReg(MIB.getReg(0), false);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 31954e7954c03..f4ab0190d223f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -569,7 +569,7 @@ bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
case Intrinsic::aarch64_neon_fcvtpu:
// Force FPR register bank for half types, as those types otherwise
// don't get legalized correctly resulting in fp16 <-> gpr32 COPY's.
- return MRI.getType(MI.getOperand(2).getReg()) == LLT::float16();
+ return MRI.getType(MI.getOperand(2).getReg()) == LLT::scalar(16); // TODO: Expected LLT::float16()
default:
break;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index d1a5b4e85da46..b5ef1a87a5abb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -332,7 +332,7 @@ bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
extOpcodeToISDExtOpcode(ExtendOp));
if (ExtVT != VT) {
RetInfo.Ty = ExtVT.getTypeForEVT(Ctx);
- LLT ExtTy = getLLTForType(*RetInfo.Ty, DL);
+ LLT ExtTy = TLI.getLLTForType(*RetInfo.Ty, DL);
Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0);
}
}
@@ -414,6 +414,7 @@ void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg,
MachineFunction &MF = B.getMF();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getDataLayout();
+ const SITargetLowering &TLI = *getTLI<SITargetLowering>();
MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
LLT PtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
@@ -427,7 +428,7 @@ void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg,
Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy);
lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]);
- LLT ArgTy = getLLTForType(*SplitArg.Ty, DL);
+ LLT ArgTy = TLI.getLLTForType(*SplitArg.Ty, DL);
if (SplitArg.Flags[0].isPointer()) {
// Compensate for losing pointeriness in splitValueTypes.
LLT PtrTy = LLT::pointer(SplitArg.Flags[0].getPointerAddrSpace(),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
index d23521c87e202..853f55278c667 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
@@ -464,8 +464,9 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(
LLT DestTy = MRI.getType(Dst);
LLT ScalarDestTy = DestTy.getScalarType();
- if ((ScalarDestTy != LLT::float64() && ScalarDestTy != LLT::float32() &&
- ScalarDestTy != LLT::float16()) ||
+ // TODO: Expected float type in ScalarDestTy
+ if ((ScalarDestTy != LLT::scalar(64) && ScalarDestTy != LLT::scalar(32) &&
+ ScalarDestTy != LLT::scalar(16)) ||
!MRI.hasOneNonDBGUse(Sel.getOperand(0).getReg()))
return false;
@@ -486,7 +487,8 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(
return false;
// For f32, only non-inline constants should be transformed.
- if (ScalarDestTy == LLT::float32() && TII.isInlineConstant(*SelectTrueVal) &&
+ // TODO: Expected float32
+ if (ScalarDestTy == LLT::scalar(32) && TII.isInlineConstant(*SelectTrueVal) &&
TII.isInlineConstant(*SelectFalseVal))
return false;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 600a13096f55d..ccc01ddfce777 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -295,9 +295,9 @@ constexpr LLT S1 = LLT::scalar(1);
constexpr LLT S8 = LLT::scalar(8);
constexpr LLT S16 = LLT::scalar(16);
constexpr LLT S32 = LLT::scalar(32);
-constexpr LLT F32 = LLT::float32();
+constexpr LLT F32 = LLT::scalar(32); // TODO: Expected float32
constexpr LLT S64 = LLT::scalar(64);
-constexpr LLT F64 = LLT::float64();
+constexpr LLT F64 = LLT::scalar(64); // TODO: Expected float64
constexpr LLT S96 = LLT::scalar(96);
constexpr LLT S128 = LLT::scalar(128);
constexpr LLT S160 = LLT::scalar(160);
@@ -317,7 +317,7 @@ constexpr LLT V10S16 = LLT::fixed_vector(10, 16);
constexpr LLT V12S16 = LLT::fixed_vector(12, 16);
constexpr LLT V16S16 = LLT::fixed_vector(16, 16);
-constexpr LLT V2F16 = LLT::fixed_vector(2, LLT::float16());
+constexpr LLT V2F16 = LLT::fixed_vector(2, LLT::scalar(16)); // TODO: Expected float16
constexpr LLT V2BF16 = V2F16; // FIXME
constexpr LLT V2S32 = LLT::fixed_vector(2, 32);
@@ -3344,11 +3344,12 @@ bool AMDGPULegalizerInfo::legalizeFMad(
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// TODO: Always legal with future ftz flag.
+ // TODO: Type is expected to be float32/float16
// FIXME: Do we need just output?
- if (Ty == LLT::float32() &&
+ if (Ty == LLT::scalar(32) &&
MFI->getMode().FP32Denormals == DenormalMode::getPreserveSign())
return true;
- if (Ty == LLT::float16() &&
+ if (Ty == LLT::scalar(16) &&
MFI->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign())
return true;
@@ -3900,8 +3901,8 @@ bool AMDGPULegalizerInfo::legalizeFPow(MachineInstr &MI,
Register Src1 = MI.getOperand(2).getReg();
unsigned Flags = MI.getFlags();
LLT Ty = B.getMRI()->getType(Dst);
- const LLT F16 = LLT::float16();
- const LLT F32 = LLT::float32();
+ const LLT F16 = LLT::scalar(16); // TODO: Expected float16
+ const LLT F32 = LLT::scalar(32); // TODO: Expected float32
if (Ty == F32) {
auto Log = B.buildFLog2(F32, Src0, Flags);
@@ -3944,7 +3945,7 @@ bool AMDGPULegalizerInfo::legalizeFFloor(MachineInstr &MI,
MachineIRBuilder &B) const {
const LLT S1 = LLT::scalar(1);
- const LLT F64 = LLT::float64();
+ const LLT F64 = LLT::scalar(64); // TODO: Expected float64
Register Dst = MI.getOperand(0).getReg();
Register OrigSrc = MI.getOperand(1).getReg();
unsigned Flags = MI.getFlags();
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 16a12cabce4c5..4af29cee0a3fe 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -10,6 +10,7 @@
#include "Common/CodeGenInstruction.h"
#include "Common/CodeGenRegisters.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/ScopedPrinter.h"
@@ -20,6 +21,11 @@
STATISTIC(NumPatternEmitted, "Number of patterns emitted");
+static llvm::cl::opt<bool> AllowExtendedLLT(
+ "gisel-extended-llt",
+ llvm::cl::desc("Generate an extended llt names in match tables"),
+ llvm::cl::init(false));
+
namespace llvm {
namespace gi {
@@ -417,6 +423,8 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
else if (Ty.isFloat())
OS << "LLT::floatingPoint(" << Ty.getScalarSizeInBits()
<< ", LLT::FPVariant::IEEE_FLOAT)";
+ else
+ OS << "LLT::scalar(" << Ty.getScalarSizeInBits() << ")";
return;
}
@@ -438,7 +446,8 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
else if (ElemTy.isFloat())
OS << "LLT::floatingPoint(" << ElemTy.getScalarSizeInBits()
<< ", LLT::FPVariant::IEEE_FLOAT)";
-
+ else
+ OS << "LLT::scalar(" << Ty.getScalarSizeInBits() << ")";
OS << ")";
return;
}
@@ -456,7 +465,36 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
/// particular logic behind the order but either A < B or B < A must be
/// true if A != B.
bool LLTCodeGen::operator<(const LLTCodeGen &Other) const {
- return Ty.getUniqueRAWLLTData() < Other.Ty.getUniqueRAWLLTData();
+ if (Ty.isValid() != Other.Ty.isValid())
+ return Ty.isValid() < Other.Ty.isValid();
+ if (!Ty.isValid())
+ return false;
+
+ if (Ty.isVector() != Other.Ty.isVector())
+ return Ty.isVector() < Other.Ty.isVector();
+ if (Ty.isScalar() != Other.Ty.isScalar())
+ return Ty.isScalar() < Other.Ty.isScalar();
+ if (Ty.isPointer() != Other.Ty.isPointer())
+ return Ty.isPointer() < Other.Ty.isPointer();
+
+ if (Ty.isPointer() && Ty.getAddressSpace() != Other.Ty.getAddressSpace())
+ return Ty.getAddressSpace() < Other.Ty.getAddressSpace();
+
+ if (Ty.isVector() && Ty.getElementCount() != Other.Ty.getElementCount())
+ return std::tuple(Ty.isScalable(),
+ Ty.getElementCount().getKnownMinValue()) <
+ std::tuple(Other.Ty.isScalable(),
+ Other.Ty.getElementCount().getKnownMinValue());
+
+ assert((!Ty.isVector() || Ty.isScalable() == Other.Ty.isScalable()) &&
+ "Unexpected mismatch of scalable property");
+ return Ty.isVector()
+ ? std::tuple(Ty.isScalable(),
+ Ty.getSizeInBits().getKnownMinValue()) <
+ std::tuple(Other.Ty.isScalable(),
+ Other.Ty.getSizeInBits().getKnownMinValue())
+ : Ty.getSizeInBits().getFixedValue() <
+ Other.Ty.getSizeInBits().getFixedValue();
}
//===- LLTCodeGen Helpers -------------------------------------------------===//
@@ -465,10 +503,10 @@ std::optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) {
MVT VT(SVT);
if (VT.isVector() && !VT.getVectorElementCount().isScalar())
- return LLTCodeGen(LLT(VT));
+ return LLTCodeGen(LLT(VT, AllowExtendedLLT));
if (VT.isInteger() || VT.isFloatingPoint())
- return LLTCodeGen(LLT(VT));
+ return LLTCodeGen(LLT(VT, AllowExtendedLLT));
return std::nullopt;
}
>From bc4b0ec59137b7effc2acdecabcbd0b179d64b35 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Fri, 22 Aug 2025 19:14:47 +0300
Subject: [PATCH 05/41] Fix MIR tests
---
.../CodeGen/MIR/AArch64/parse-low-level-type-invalid0.mir | 4 ++--
.../CodeGen/MIR/AArch64/parse-low-level-type-invalid1.mir | 4 ++--
.../CodeGen/MIR/AArch64/parse-low-level-type-invalid2.mir | 2 +-
.../CodeGen/MIR/AArch64/parse-low-level-type-invalid3.mir | 6 +++---
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err0.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err1.mir | 2 +-
.../test/CodeGen/MIR/Generic/scalable-vector-type-err10.mir | 2 +-
.../test/CodeGen/MIR/Generic/scalable-vector-type-err11.mir | 2 +-
.../test/CodeGen/MIR/Generic/scalable-vector-type-err12.mir | 2 +-
.../test/CodeGen/MIR/Generic/scalable-vector-type-err13.mir | 2 +-
.../test/CodeGen/MIR/Generic/scalable-vector-type-err14.mir | 2 +-
.../test/CodeGen/MIR/Generic/scalable-vector-type-err15.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err2.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err3.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err4.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err5.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err6.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err7.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err8.mir | 2 +-
llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err9.mir | 2 +-
.../MIR/WebAssembly/typed-immediate-operand-invalid0.mir | 4 ++--
.../MIR/WebAssembly/typed-immediate-operand-invalid1.mir | 4 ++--
22 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid0.mir b/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid0.mir
index cece3601dc1b2..95fd669a5d971 100644
--- a/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid0.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid0.mir
@@ -1,10 +1,10 @@
# RUN: not llc -mtriple=aarch64-- -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# When a low-level type is only a single 's'/'p' character
+# When a low-level type is only a single 's'/'i'/'f'/'bf'/'p' type identifier
---
name: test_low_level_type_is_single_s_p
body: |
bb.0:
liveins: $x0
- ; CHECK: [[@LINE+1]]:10: expected integers after 's'/'p' type character
+ ; CHECK: [[@LINE+1]]:10: expected integers after 's'/'i'/'f'/'bf'/'p' type identifier
%0:_(s) = COPY $x0
...
diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid1.mir b/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid1.mir
index 4a7b68dab623a..dd0bb73a6cf42 100644
--- a/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid1.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid1.mir
@@ -5,6 +5,6 @@ name: test_low_level_type_does_not_start_with_s_p_lt
body: |
bb.0:
liveins: $x0
- ; CHECK: [[@LINE+1]]:10: expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, or <vscale x M x pA> for GlobalISel type
- %0:_(i64) = COPY $x0
+ ; CHECK: [[@LINE+1]]:10: expected tN, pA, <M x tN>, <M x pA>, <vscale x M x tN>, or <vscale x M x pA> for GlobalISel type, where t = {'s', 'i', 'f', 'bf'}
+ %0:_(n64) = COPY $x0
...
diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid2.mir b/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid2.mir
index 1bff7a5ec9ced..6277d24aacab3 100644
--- a/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid2.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid2.mir
@@ -5,6 +5,6 @@ name: test_low_level_type_is_single_s_p
body: |
bb.0:
liveins: $q0
- ; CHECK: [[@LINE+1]]:15: expected integers after 's'/'p' type character
+ ; CHECK: [[@LINE+1]]:15: expected integers after 's'/'i'/'f'/'bf'/'p' type identifier
%0:_(<2 x p>) = COPY $q0
...
diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid3.mir b/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid3.mir
index ebb3d37f9dfa1..ba652329c5337 100644
--- a/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid3.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid3.mir
@@ -1,10 +1,10 @@
# RUN: not llc -mtriple=aarch64-- -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# When a low-level type is a vector which element type does not start with 's' or 'p'
+# When a low-level type is a vector which element type does not start with right type identifier
---
name: test_low_level_type_does_not_start_with_s_p
body: |
bb.0:
liveins: $q0
- ; CHECK: [[@LINE+1]]:10: expected <M x sN> or <M x pA> for vector type
- %0:_(<2 x i64>) = COPY $q0
+ ; CHECK: [[@LINE+1]]:10: expected <M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
+ %0:_(<2 x n64>) = COPY $q0
...
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err0.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err0.mir
index 5553d97acd003..6fc6640ea422a 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err0.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err0.mir
@@ -6,5 +6,5 @@ body: |
%0:_(<vscale) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale x M x pA>
+# CHECK: expected <vscale x M x tN>, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err1.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err1.mir
index 12bfb82ebcd12..0017e01be3b04 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err1.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err1.mir
@@ -6,4 +6,4 @@ body: |
%0:_(<vscale notanx) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale x M x pA>
+# CHECK: expected <vscale x M x tN>, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err10.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err10.mir
index 7d7d7e49f23fe..37a9a0d2c159b 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err10.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err10.mir
@@ -7,4 +7,4 @@ body: |
%0:_(<vscale x 4 x p) = IMPLICIT_DEF
...
-# CHECK: expected integers after 's'/'p' type character
+# CHECK: expected integers after 's'/'i'/'f'/'bf'/'p' type identifier
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err11.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err11.mir
index f8927c22ab45f..64296f624826e 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err11.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err11.mir
@@ -7,4 +7,4 @@ body: |
%0:_(<vscale x 4 x s32) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err12.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err12.mir
index 5ced1aea30c08..9c840d92ac967 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err12.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err12.mir
@@ -7,4 +7,4 @@ body: |
%0:_(<vscale x 4 x p0) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err13.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err13.mir
index 94b8230233fa6..982adfdf792c2 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err13.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err13.mir
@@ -7,4 +7,4 @@ body: |
%0:_(<vscale x 4 x s32 X) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err14.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err14.mir
index 323e2d975692f..8a3e86ecaaab9 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err14.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err14.mir
@@ -7,4 +7,4 @@ body: |
%0:_(<vscale x 4 x p0 X) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err15.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err15.mir
index d1613869bf671..228b367b06d40 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err15.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err15.mir
@@ -7,4 +7,4 @@ body: |
%0:_(notatype) = IMPLICIT_DEF
...
-# CHECK: expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, or <vscale x M x pA> for GlobalISel type
+# CHECK: expected tN, pA, <M x tN>, <M x pA>, <vscale x M x tN>, or <vscale x M x pA> for GlobalISel type, where t = {'s', 'i', 'f', 'bf'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err2.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err2.mir
index c504a7d6be249..b187bff218a75 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err2.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err2.mir
@@ -6,4 +6,4 @@ body: |
%0:_(<vscale x) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err3.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err3.mir
index c504a7d6be249..b187bff218a75 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err3.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err3.mir
@@ -6,4 +6,4 @@ body: |
%0:_(<vscale x) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err4.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err4.mir
index 654f534f4d301..1969f28b18d28 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err4.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err4.mir
@@ -6,5 +6,5 @@ body: |
%0:_(<vscale x notanint) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err5.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err5.mir
index 26be2868c522e..49823f7432ba9 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err5.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err5.mir
@@ -6,4 +6,4 @@ body: |
%0:_(<vscale x 4) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err6.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err6.mir
index 07a30f57139dc..7f8e421e76ae3 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err6.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err6.mir
@@ -7,5 +7,5 @@ body: |
%0:_(<vscale x 4 x) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err7.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err7.mir
index dba902efe6331..ae3c472e2557c 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err7.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err7.mir
@@ -6,4 +6,4 @@ body: |
%0:_(<vscale x 4 x notansorp) = IMPLICIT_DEF
...
-# CHECK: expected <vscale x M x sN> or <vscale M x pA> for vector type
+# CHECK: expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err8.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err8.mir
index 8bedeabaa7906..9044f77f84dc5 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err8.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err8.mir
@@ -7,4 +7,4 @@ body: |
%0:_(<vscale x 4 x s) = IMPLICIT_DEF
...
-# CHECK: expected integers after 's'/'p' type character
+# CHECK: expected integers after 's'/'i'/'f'/'bf'/'p' type identifier
diff --git a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err9.mir b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err9.mir
index fd0b9a4a054ab..9220715320d99 100644
--- a/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err9.mir
+++ b/llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err9.mir
@@ -6,6 +6,6 @@ body: |
%0:_(<vscale x 4 x pX) = IMPLICIT_DEF
...
-# CHECK: expected integers after 's'/'p' type character
+# CHECK: expected integers after 's'/'i'/'f'/'bf'/'p' type identifier
diff --git a/llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid0.mir b/llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid0.mir
index 72908711e9ee5..7a2e381372549 100644
--- a/llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid0.mir
+++ b/llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid0.mir
@@ -1,5 +1,5 @@
# RUN: not llc -mtriple=wasm32-unknown-unknown -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# When a typed immediate operand is only a single 'i'/'s'/'p' character
+# When a typed immediate operand is only a single type character
---
name: test_typed_immediate_operand_invalid0
liveins:
@@ -7,7 +7,7 @@ liveins:
body: |
bb.0:
liveins: $arguments
- ; CHECK: [[@LINE+1]]:24: expected integers after 'i'/'s'/'p' type character
+ ; CHECK: [[@LINE+1]]:24: expected integers after 'i'/'s'/'f'/'bf'/'p' type identifier
%0:i32 = CONST_I32 i 0, implicit-def dead $arguments
RETURN implicit-def dead $arguments
...
diff --git a/llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid1.mir b/llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid1.mir
index f5c16b52553bf..7f59a9e5eca0f 100644
--- a/llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid1.mir
+++ b/llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid1.mir
@@ -1,5 +1,5 @@
# RUN: not llc -mtriple=wasm32-unknown-unknown -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# When a typed immediate operand does not start with 'i', 's', or 'p'
+# When a typed immediate operand does not start with right type identifier
---
name: test_typed_immediate_operand_invalid1
liveins:
@@ -7,7 +7,7 @@ liveins:
body: |
bb.0:
liveins: $arguments
- ; CHECK: [[@LINE+1]]:24: a typed immediate operand should start with one of 'i', 's', or 'p'
+ ; CHECK: [[@LINE+1]]:24: a typed immediate operand should start with one of 'i', 's', 'f', 'bf', or 'p'
%0:i32 = CONST_I32 abc 0, implicit-def dead $arguments
RETURN implicit-def dead $arguments
...
>From 655b85ada6d0c441ad6e36d4474ad31f5326dc5a Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Fri, 22 Aug 2025 19:32:47 +0300
Subject: [PATCH 06/41] enable bfloat in IRTranslator for targets that support
it
---
.../llvm/CodeGen/GlobalISel/IRTranslator.h | 2 +
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 37 +++++++++++--------
2 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index 3d7ccd55ee042..5673fd5168477 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -642,6 +642,8 @@ class IRTranslator : public MachineFunctionPass {
StackProtectorDescriptor SPDescriptor;
+ bool mayTranslateUserTypes(const User &U) const;
+
/// Switch analysis and optimization.
class GISelSwitchLowering : public SwitchCG::SwitchLowering {
public:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 4484a0769ad2a..0abaeea482f24 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -295,19 +295,10 @@ void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
MachinePreds[Edge].push_back(NewPred);
}
-static bool containsBF16Type(const User &U) {
- // BF16 cannot currently be represented by LLT, to avoid miscompiles we
- // prevent any instructions using them. FIXME: This can be removed once LLT
- // supports bfloat.
- return U.getType()->getScalarType()->isBFloatTy() ||
- any_of(U.operands(), [](Value *V) {
- return V->getType()->getScalarType()->isBFloatTy();
- });
-}
bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
MachineIRBuilder &MIRBuilder) {
- if (containsBF16Type(U))
+ if (!mayTranslateUserTypes(U))
return false;
// Get or create a virtual register for each value.
@@ -329,7 +320,7 @@ bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
bool IRTranslator::translateUnaryOp(unsigned Opcode, const User &U,
MachineIRBuilder &MIRBuilder) {
- if (containsBF16Type(U))
+ if (!mayTranslateUserTypes(U))
return false;
Register Op0 = getOrCreateVReg(*U.getOperand(0));
@@ -349,7 +340,7 @@ bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
bool IRTranslator::translateCompare(const User &U,
MachineIRBuilder &MIRBuilder) {
- if (containsBF16Type(U))
+ if (!mayTranslateUserTypes(U))
return false;
auto *CI = cast<CmpInst>(&U);
@@ -1570,7 +1561,7 @@ bool IRTranslator::translateBitCast(const User &U,
bool IRTranslator::translateCast(unsigned Opcode, const User &U,
MachineIRBuilder &MIRBuilder) {
- if (containsBF16Type(U))
+ if (!mayTranslateUserTypes(U))
return false;
uint32_t Flags = 0;
@@ -2675,7 +2666,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
bool IRTranslator::translateInlineAsm(const CallBase &CB,
MachineIRBuilder &MIRBuilder) {
- if (containsBF16Type(CB))
+ if (!mayTranslateUserTypes(CB))
return false;
const InlineAsmLowering *ALI = MF->getSubtarget().getInlineAsmLowering();
@@ -2766,7 +2757,7 @@ bool IRTranslator::translateCallBase(const CallBase &CB,
}
bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
- if (containsBF16Type(U))
+ if (!mayTranslateUserTypes(U))
return false;
const CallInst &CI = cast<CallInst>(U);
@@ -3392,7 +3383,7 @@ bool IRTranslator::translateAtomicCmpXchg(const User &U,
bool IRTranslator::translateAtomicRMW(const User &U,
MachineIRBuilder &MIRBuilder) {
- if (containsBF16Type(U))
+ if (!mayTranslateUserTypes(U))
return false;
const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
@@ -3733,6 +3724,20 @@ bool IRTranslator::translate(const Constant &C, Register Reg) {
return true;
}
+bool IRTranslator::mayTranslateUserTypes(const User &U) const {
+ if (TLI->getTargetMachine().Options.EnableGlobalISelExtendedLLT) {
+ return true;
+ }
+
+ // BF16 cannot currently be represented by default LLT, to avoid miscompiles
+ // we prevent any instructions using them in targets with disabled
+ // TargetOptions::EnableGlobalISelExtendedLLT.
+ return !U.getType()->getScalarType()->isBFloatTy() &&
+ !any_of(U.operands(), [](Value *V) {
+ return V->getType()->getScalarType()->isBFloatTy();
+ });
+}
+
bool IRTranslator::finalizeBasicBlock(const BasicBlock &BB,
MachineBasicBlock &MBB) {
for (auto &BTB : SL->BitTestCases) {
>From b767e6ee5420427e5fa7769cdd30c40e66dce340 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sat, 23 Aug 2025 18:20:22 +0300
Subject: [PATCH 07/41] [unittest] Added simple IRTranslator test for bf16
---
.../CodeGen/GlobalISel/CMakeLists.txt | 1 +
.../GlobalISel/IRTranslatorBF16Test.cpp | 130 ++++++++++++++++++
2 files changed, 131 insertions(+)
create mode 100644 llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
diff --git a/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt b/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
index 4ef6aff943f73..e85a3aa72c961 100644
--- a/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
+++ b/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
@@ -14,6 +14,7 @@ set(LLVM_LINK_COMPONENTS
)
add_llvm_unittest(GlobalISelTests
+ IRTranslatorBF16Test.cpp
ConstantFoldingTest.cpp
CSETest.cpp
GIMatchTableExecutorTest.cpp
diff --git a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
new file mode 100644
index 0000000000000..31ec0e34a0661
--- /dev/null
+++ b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
@@ -0,0 +1,130 @@
+//===- IRTranslator.cpp - IRTranslator unit tests -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/AsmParser/Parser.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/IR/Module.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+#include "gtest/gtest.h"
+#include <memory>
+
+using namespace llvm;
+
+namespace {
+struct AArch64IRTranslatorTest : public ::testing::Test {
+ LLVMContext C;
+
+public:
+ AArch64IRTranslatorTest() {}
+ std::unique_ptr<TargetMachine> createTargetMachine() const {
+ Triple TargetTriple("aarch64--");
+ std::string Error;
+ const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
+ if (!T)
+ return nullptr;
+
+ TargetOptions Options;
+ return std::unique_ptr<TargetMachine>(
+ T->createTargetMachine(TargetTriple, "", "", Options, std::nullopt,
+ std::nullopt, CodeGenOptLevel::Aggressive));
+ }
+
+ std::unique_ptr<Module> parseIR(const char *IR) {
+ SMDiagnostic Err;
+ std::unique_ptr<Module> Mod = parseAssemblyString(IR, Err, C);
+ if (!Mod)
+ Err.print("Test TargetIRTranslator", errs());
+ return Mod;
+ }
+};
+} // namespace
+
+TEST_F(AArch64IRTranslatorTest, IRTranslateBfloat16) {
+ InitializeAllTargets();
+ InitializeAllTargetMCs();
+ InitializeAllAsmPrinters();
+ InitializeAllAsmParsers();
+
+ PassRegistry *Registry = PassRegistry::getPassRegistry();
+ initializeCore(*Registry);
+ initializeCodeGen(*Registry);
+ initializeGlobalISel(*Registry);
+
+ std::unique_ptr<Module> M = parseIR(R"(
+ define void @foo(ptr %p0) {
+ %ptr1 = getelementptr bfloat, ptr %p0, i64 0
+ %ptr2 = getelementptr bfloat, ptr %p0, i64 1
+ %ptr3 = getelementptr bfloat, ptr %p0, i64 2
+ %a = load bfloat, ptr %ptr1, align 2
+ %b = load bfloat, ptr %ptr2, align 2
+ %c = load bfloat, ptr %ptr3, align 2
+ %mul = fmul bfloat %a, %b
+ %res = fadd bfloat %mul, %c
+ %ptr4 = getelementptr bfloat, ptr %p0, i64 3
+ store bfloat %res, ptr %ptr4, align 2
+ ret void
+ }
+ )");
+
+ auto TM = createTargetMachine();
+ M->setDataLayout(TM->createDataLayout());
+
+ TM->setGlobalISel(true);
+ TM->setGlobalISelExtendedLLT(true);
+ TM->setGlobalISelAbort(GlobalISelAbortMode::DisableWithDiag);
+
+ legacy::PassManager PM;
+ TargetPassConfig *TPC(TM->createPassConfig(PM));
+
+ MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass(TM.get());
+ PM.add(TPC);
+ PM.add(MMIWP);
+ PM.add(new IRTranslator());
+ PM.run(*M);
+
+ auto *MMI = &MMIWP->getMMI();
+ Function *F = M->getFunction("foo");
+ auto *MF = MMI->getMachineFunction(*F);
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ ASSERT_FALSE(MF->getProperties().hasProperty(
+ llvm::MachineFunctionProperties::Property::FailedISel));
+ for (auto &MI : MF->front()) {
+ if (MI.getOpcode() == TargetOpcode::G_LOAD) {
+ ASSERT_EQ(MRI.getType(MI.getOperand(0).getReg()), LLT::bfloat16());
+ }
+
+ if (MI.getOpcode() == TargetOpcode::G_FADD ||
+ MI.getOpcode() == TargetOpcode::G_FMUL) {
+ for (auto &Op : MI.operands()) {
+ ASSERT_EQ(MRI.getType(Op.getReg()), LLT::bfloat16());
+ }
+ }
+ }
+ MMI->deleteMachineFunctionFor(*F);
+
+ // Run again without extended LLT
+ TM->setGlobalISelExtendedLLT(false);
+ PM.run(*M);
+ MF = MMI->getMachineFunction(*F);
+ ASSERT_TRUE(MF->getProperties().hasProperty(llvm::MachineFunctionProperties::Property::FailedISel));
+}
>From 82602b7ecdae957ef2349e36d16aecda91cfb2f0 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sat, 23 Aug 2025 18:45:53 +0300
Subject: [PATCH 08/41] fixed names
---
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 14 +++++++-------
llvm/lib/CodeGenTypes/LowLevelType.cpp | 4 ++--
llvm/lib/Support/TypeSize.cpp | 2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index daec87ab536c0..0c217ba1fcf7e 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -42,9 +42,9 @@ class LLT {
enum class FPVariant {
IEEE_FLOAT = 0x0,
BRAIN_FLOAT = 0x1, // BRAIN_FLOAT
- VARIANT_FLOAT_2 = 0x2, // PPC_FLOAT
- VARIANT_FLOAT_3 = 0x3, // FP80
- VARIANT_FLOAT_4 = 0x4, // TENSOR_FLOAT
+ PPC128_FLOAT = 0x2, // PPC128_FLOAT
+ EXTENDED_FP80 = 0x3, // FP80
+ TENSOR_FLOAT32 = 0x4, // TENSOR_FLOAT32
VARIANT_FLOAT_5 = 0x5, // UNASSIGNED
VARIANT_FLOAT_6 = 0x6, // UNASSIGNED
VARIANT_FLOAT_7 = 0x7, // UNASSIGNED
@@ -163,7 +163,7 @@ class LLT {
/// Get a 80-bit X86 floating point value.
static constexpr LLT x86fp80() {
- return floatingPoint(80, FPVariant::VARIANT_FLOAT_3);
+ return floatingPoint(80, FPVariant::EXTENDED_FP80);
}
/// Get a 128-bit IEEE quad value.
@@ -173,7 +173,7 @@ class LLT {
/// Get a 128-bit PowerPC double double value.
static constexpr LLT ppcf128() {
- return floatingPoint(128, FPVariant::VARIANT_FLOAT_2);
+ return floatingPoint(128, FPVariant::PPC128_FLOAT);
}
/// Get a low-level fixed-width vector of some number of elements and element
@@ -249,10 +249,10 @@ class LLT {
return isVariantFloat(Size, FPVariant::BRAIN_FLOAT);
}
constexpr bool isX86FP80() const {
- return isVariantFloat(80, FPVariant::VARIANT_FLOAT_3);
+ return isVariantFloat(80, FPVariant::EXTENDED_FP80);
}
constexpr bool isPPCF128() const {
- return isVariantFloat(128, FPVariant::VARIANT_FLOAT_2);
+ return isVariantFloat(128, FPVariant::PPC128_FLOAT);
}
constexpr bool isToken() const {
return Info == Kind::ANY_SCALAR && RawData == 0;
diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index 35329793bd508..6025f3fedafa1 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -24,9 +24,9 @@ static std::optional<LLT::FPVariant> deriveFPInfo(MVT VT) {
case MVT::bf16:
return LLT::FPVariant::BRAIN_FLOAT;
case MVT::f80:
- return LLT::FPVariant::VARIANT_FLOAT_3;
+ return LLT::FPVariant::EXTENDED_FP80;
case MVT::ppcf128:
- return LLT::FPVariant::VARIANT_FLOAT_2;
+ return LLT::FPVariant::PPC128_FLOAT;
default:
return LLT::FPVariant::IEEE_FLOAT;
}
diff --git a/llvm/lib/Support/TypeSize.cpp b/llvm/lib/Support/TypeSize.cpp
index a96fced8eff30..43346b81cd676 100644
--- a/llvm/lib/Support/TypeSize.cpp
+++ b/llvm/lib/Support/TypeSize.cpp
@@ -44,7 +44,7 @@ void llvm::reportInvalidSizeRequest(const char *Msg) {
return;
}
#endif
- report_fatal_error(Twine("Invalid size request on a scalable vector.") + Msg);
+ report_fatal_error("Invalid size request on a scalable vector.");
}
TypeSize::operator TypeSize::ScalarTy() const {
>From 6485b50cfdea9a41c11b294b70c30b35d22ee845 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sat, 23 Aug 2025 19:21:30 +0300
Subject: [PATCH 09/41] code style fixes
---
llvm/include/llvm/CodeGen/Analysis.h | 3 +--
.../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 3 ++-
llvm/include/llvm/CodeGen/LowLevelTypeUtils.h | 3 ++-
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 13 +++++++++----
llvm/include/llvm/Target/TargetMachine.h | 4 +++-
llvm/include/llvm/Target/TargetOptions.h | 4 ++--
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 1 -
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 16 ++++++++++------
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 3 ++-
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 5 +++--
.../CodeGen/GlobalISel/IRTranslatorBF16Test.cpp | 10 ++++++----
11 files changed, 40 insertions(+), 25 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/Analysis.h b/llvm/include/llvm/CodeGen/Analysis.h
index 2aadc27930b7a..5c36ecd26719e 100644
--- a/llvm/include/llvm/CodeGen/Analysis.h
+++ b/llvm/include/llvm/CodeGen/Analysis.h
@@ -101,8 +101,7 @@ inline void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL,
/// If Offsets is non-null, it points to a vector to be filled in
/// with the in-memory offsets of each of the individual values.
///
-void computeValueLLTs(const TargetLowering &TLI,
- const DataLayout &DL, Type &Ty,
+void computeValueLLTs(const TargetLowering &TLI, const DataLayout &DL, Type &Ty,
SmallVectorImpl<LLT> &ValueTys,
SmallVectorImpl<uint64_t> *Offsets = nullptr,
uint64_t StartingOffset = 0);
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 8412042a780e8..7b6b5dbf0be05 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -380,7 +380,8 @@ LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx,
/// Keep the same scalar or element type as \p TypeIdx, but take the number of
/// elements from \p Ty.
-LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx, ElementCount EC);
+LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx,
+ ElementCount EC);
/// Change the scalar size or element size to have the same scalar size as type
/// index \p FromIndex. Unlike changeElementTo, this discards pointer types and
diff --git a/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h b/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
index 1c8f34b1a8518..4092509948ae6 100644
--- a/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
+++ b/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
@@ -27,7 +27,8 @@ class Type;
struct fltSemantics;
/// Construct a low-level type based on an LLVM type.
-LLVM_ABI LLT getLLTForType(Type &Ty, const DataLayout &DL, bool AllowExtendedLLT = false);
+LLVM_ABI LLT getLLTForType(Type &Ty, const DataLayout &DL,
+ bool AllowExtendedLLT = false);
/// Get a rough equivalent of an MVT for a given LLT. MVT can't distinguish
/// pointers, so these will convert to a plain integer.
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 0c217ba1fcf7e..3378baf680230 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -178,7 +178,8 @@ class LLT {
/// Get a low-level fixed-width vector of some number of elements and element
/// width.
- static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits) {
+ static constexpr LLT fixed_vector(unsigned NumElements,
+ unsigned ScalarSizeInBits) {
return vector(ElementCount::getFixed(NumElements),
LLT::scalar(ScalarSizeInBits));
}
@@ -191,7 +192,8 @@ class LLT {
/// Get a low-level scalable vector of some number of elements and element
/// width.
- static constexpr LLT scalable_vector(unsigned MinNumElements, unsigned ScalarSizeInBits) {
+ static constexpr LLT scalable_vector(unsigned MinNumElements,
+ unsigned ScalarSizeInBits) {
return vector(ElementCount::getScalable(MinNumElements),
LLT::scalar(ScalarSizeInBits));
}
@@ -222,7 +224,10 @@ class LLT {
explicit constexpr LLT() : Info(static_cast<Kind>(0)), RawData(0) {}
constexpr bool isValid() const { return isToken() || RawData != 0; }
- constexpr bool isScalar() const { return Info == Kind::ANY_SCALAR || Info == Kind::INTEGER || Info == Kind::FLOAT; }
+ constexpr bool isScalar() const {
+ return Info == Kind::ANY_SCALAR || Info == Kind::INTEGER ||
+ Info == Kind::FLOAT;
+ }
constexpr bool isScalar(unsigned Size) const {
return isScalar() && getScalarSizeInBits() == Size;
}
@@ -274,7 +279,7 @@ class LLT {
}
constexpr bool isVector() const {
return isValid() &&
- (Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER||
+ (Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER ||
Info == Kind::VECTOR_FLOAT || Info == Kind::VECTOR_POINTER);
}
constexpr bool isPointer() const {
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index 5671318a8586d..a503199856c5a 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -295,7 +295,9 @@ class LLVM_ABI TargetMachine {
bool getO0WantsFastISel() { return O0WantsFastISel; }
void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; }
void setGlobalISel(bool Enable) { Options.EnableGlobalISel = Enable; }
- void setGlobalISelExtendedLLT(bool Enable) { Options.EnableGlobalISelExtendedLLT = Enable; }
+ void setGlobalISelExtendedLLT(bool Enable) {
+ Options.EnableGlobalISelExtendedLLT = Enable;
+ }
void setGlobalISelAbort(GlobalISelAbortMode Mode) {
Options.GlobalISelAbort = Mode;
}
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index 839412cd151bf..b167d4e13a342 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -236,8 +236,8 @@ class TargetOptions {
/// EnableGlobalISel - This flag enables global instruction selection.
unsigned EnableGlobalISel : 1;
- /// EnableGlobalISelExtendedLLT - This flag enables LLTs with extenden type info
- /// so target may distinguish different formats of equal sized scalars.
+ /// EnableGlobalISelExtendedLLT - This flag enables LLTs with extenden type
+ /// info so target may distinguish different formats of equal sized scalars.
unsigned EnableGlobalISelExtendedLLT : 1;
/// EnableGlobalISelAbort - Control abort behaviour when global instruction
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 670e03e69a9c4..8dac12fc4597a 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -294,7 +294,6 @@ void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
MachinePreds[Edge].push_back(NewPred);
}
-
bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
MachineIRBuilder &MIRBuilder) {
if (!mayTranslateUserTypes(U))
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 699f4d3529b6e..94205698c5038 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1934,7 +1934,8 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
TypeDigits.consume_front("f") || TypeDigits.consume_front("p") ||
TypeDigits.consume_front("bf")) {
if (TypeDigits.empty() || !llvm::all_of(TypeDigits, isdigit))
- return error("expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
+ return error(
+ "expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
}
if (Token.range().starts_with("s") || Token.range().starts_with("i")) {
@@ -1994,15 +1995,17 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
if (HasVScale) {
lex();
if (Token.isNot(MIToken::Identifier) || Token.stringValue() != "x")
- return error("expected <vscale x M x tN>, where t = {'s', 'i', 'f', 'bf', 'p'}");
+ return error(
+ "expected <vscale x M x tN>, where t = {'s', 'i', 'f', 'bf', 'p'}");
lex();
}
auto GetError = [this, &HasVScale, Loc]() {
if (HasVScale)
- return error(
- Loc, "expected <vscale x M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}");
- return error(Loc, "expected <M x tN> for vector type, where t = {'s', 'i', 'f', 'bf', 'p'}");
+ return error(Loc, "expected <vscale x M x tN> for vector type, where t = "
+ "{'s', 'i', 'f', 'bf', 'p'}");
+ return error(Loc, "expected <M x tN> for vector type, where t = {'s', 'i', "
+ "'f', 'bf', 'p'}");
};
if (Token.isNot(MIToken::IntegerLiteral))
@@ -2073,7 +2076,8 @@ bool MIParser::parseTypedImmediateOperand(MachineOperand &Dest) {
return error("a typed immediate operand should start with one of 'i', "
"'s', 'f', 'bf', or 'p'");
if (TypeDigits.empty() || !llvm::all_of(TypeDigits, isdigit))
- return error("expected integers after 'i'/'s'/'f'/'bf'/'p' type identifier");
+ return error(
+ "expected integers after 'i'/'s'/'f'/'bf'/'p' type identifier");
auto Loc = Token.location();
lex();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index aa598dec1c800..29d5cec49d579 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -570,7 +570,8 @@ bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
case Intrinsic::aarch64_neon_fcvtpu:
// Force FPR register bank for half types, as those types otherwise
// don't get legalized correctly resulting in fp16 <-> gpr32 COPY's.
- return MRI.getType(MI.getOperand(2).getReg()) == LLT::scalar(16); // TODO: Expected LLT::float16()
+ return MRI.getType(MI.getOperand(2).getReg()) ==
+ LLT::scalar(16); // TODO: Expected LLT::float16()
default:
break;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index ccc01ddfce777..a4e2f321be91d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -317,8 +317,9 @@ constexpr LLT V10S16 = LLT::fixed_vector(10, 16);
constexpr LLT V12S16 = LLT::fixed_vector(12, 16);
constexpr LLT V16S16 = LLT::fixed_vector(16, 16);
-constexpr LLT V2F16 = LLT::fixed_vector(2, LLT::scalar(16)); // TODO: Expected float16
-constexpr LLT V2BF16 = V2F16; // FIXME
+constexpr LLT V2F16 =
+ LLT::fixed_vector(2, LLT::scalar(16)); // TODO: Expected float16
+constexpr LLT V2BF16 = V2F16; // FIXME
constexpr LLT V2S32 = LLT::fixed_vector(2, 32);
constexpr LLT V3S32 = LLT::fixed_vector(3, 32);
diff --git a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
index 31ec0e34a0661..c532634c19817 100644
--- a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
@@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/AsmParser/Parser.h"
+#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -46,7 +46,7 @@ struct AArch64IRTranslatorTest : public ::testing::Test {
TargetOptions Options;
return std::unique_ptr<TargetMachine>(
T->createTargetMachine(TargetTriple, "", "", Options, std::nullopt,
- std::nullopt, CodeGenOptLevel::Aggressive));
+ std::nullopt, CodeGenOptLevel::Aggressive));
}
std::unique_ptr<Module> parseIR(const char *IR) {
@@ -96,7 +96,8 @@ TEST_F(AArch64IRTranslatorTest, IRTranslateBfloat16) {
legacy::PassManager PM;
TargetPassConfig *TPC(TM->createPassConfig(PM));
- MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass(TM.get());
+ MachineModuleInfoWrapperPass *MMIWP =
+ new MachineModuleInfoWrapperPass(TM.get());
PM.add(TPC);
PM.add(MMIWP);
PM.add(new IRTranslator());
@@ -126,5 +127,6 @@ TEST_F(AArch64IRTranslatorTest, IRTranslateBfloat16) {
TM->setGlobalISelExtendedLLT(false);
PM.run(*M);
MF = MMI->getMachineFunction(*F);
- ASSERT_TRUE(MF->getProperties().hasProperty(llvm::MachineFunctionProperties::Property::FailedISel));
+ ASSERT_TRUE(MF->getProperties().hasProperty(
+ llvm::MachineFunctionProperties::Property::FailedISel));
}
>From d8c9da0763fc54a65b6f433d90af1204ca3abddf Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Mon, 8 Sep 2025 14:46:59 +0300
Subject: [PATCH 10/41] style
---
.../TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 1a624957d5efc..3bee2568e69dc 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -24,10 +24,10 @@ STATISTIC(NumPatternEmitted, "Number of patterns emitted");
using namespace llvm;
using namespace gi;
-static llvm::cl::opt<bool> AllowExtendedLLT(
- "gisel-extended-llt",
- llvm::cl::desc("Generate an extended llt names in match tables"),
- llvm::cl::init(false));
+static cl::opt<bool>
+ AllowExtendedLLT("gisel-extended-llt",
+ cl::desc("Generate an extended llt names in match tables"),
+ cl::init(false));
// FIXME: Use createStringError instead.
static Error failUnsupported(const Twine &Reason) {
>From 7c5f7d226eb0631f1c3b79bc8881fe40a2a6f95b Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sun, 14 Sep 2025 17:27:28 +0300
Subject: [PATCH 11/41] style
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 94205698c5038..56dcb64feb30d 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1968,13 +1968,13 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
if (Token.range().starts_with("f") || Token.range().starts_with("bf")) {
LLT::FPVariant FPVariant;
- if (Token.range().starts_with("f")) {
+ if (Token.range().starts_with("f"))
FPVariant = LLT::FPVariant::IEEE_FLOAT;
- } else if (Token.range().starts_with("bf")) {
+ else if (Token.range().starts_with("bf"))
FPVariant = LLT::FPVariant::BRAIN_FLOAT;
- } else {
+ else
return error("unknown floating point type identifier");
- }
+
auto ScalarSize = APSInt(TypeDigits).getZExtValue();
if (!ScalarSize || !verifyScalarSize(ScalarSize))
return error("invalid size for scalar type");
>From e1f805c031ec41315018307c33459372cf191ce4 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sat, 20 Sep 2025 00:29:20 +0300
Subject: [PATCH 12/41] Review fixes
---
llvm/include/llvm/CodeGen/TargetLowering.h | 8 +-
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 153 +++++++++---------
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 3 +-
llvm/lib/CodeGen/LowLevelTypeUtils.cpp | 6 +-
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 4 +-
llvm/lib/CodeGenTypes/LowLevelType.cpp | 2 +-
6 files changed, 87 insertions(+), 89 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 9bfac318ff595..03db625ce840b 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -417,8 +417,12 @@ class LLVM_ABI TargetLoweringBase {
/// amounts, returns MVT::i32.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
- virtual LLT getLLTForType(Type &Ty, const DataLayout &DL) const;
- virtual LLT getLLTForMVT(MVT Ty) const;
+ /// Returns LLT for given Type, taking into account
+ /// TargetOptions::EnableGlobalISelExtendedLLT.
+ LLT getLLTForType(Type &Ty, const DataLayout &DL) const;
+ /// Returns LLT for given MVT, taking into account
+ /// TargetOptions::EnableGlobalISelExtendedLLT.
+ LLT getLLTForMVT(MVT Ty) const;
/// Return the preferred type to use for a shift opcode, given the shifted
/// amount type is \p ShiftValueTy.
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 0d074f3413c1c..31ac31d36e4a2 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -40,26 +40,26 @@ class raw_ostream;
class LLT {
public:
enum class FPVariant {
- IEEE_FLOAT = 0x0,
- BRAIN_FLOAT = 0x1, // BRAIN_FLOAT
- PPC128_FLOAT = 0x2, // PPC128_FLOAT
- EXTENDED_FP80 = 0x3, // FP80
- TENSOR_FLOAT32 = 0x4, // TENSOR_FLOAT32
- VARIANT_FLOAT_5 = 0x5, // UNASSIGNED
- VARIANT_FLOAT_6 = 0x6, // UNASSIGNED
- VARIANT_FLOAT_7 = 0x7, // UNASSIGNED
+ IEEE_FLOAT,
+ BF16, // BF16
+ TENSOR_FLOAT32, // TENSOR_FLOAT32
+ EXTENDED_FP80, // FP80
+ PPC128_FLOAT, // PPC128_FLOAT
+ VARIANT_FLOAT_5, // UNASSIGNED
+ VARIANT_FLOAT_6, // UNASSIGNED
+ VARIANT_FLOAT_7, // UNASSIGNED
};
- enum class Kind : uint64_t {
- INVALID = 0b0000,
- ANY_SCALAR = 0b0001,
- INTEGER = 0b0010,
- FLOAT = 0b0011,
- POINTER = 0b0100,
- VECTOR_ANY = 0b0101,
- VECTOR_INTEGER = 0b0110,
- VECTOR_FLOAT = 0b0111,
- VECTOR_POINTER = 0b1000,
+ enum class Kind : uint8_t {
+ INVALID,
+ ANY_SCALAR,
+ INTEGER,
+ FLOAT,
+ POINTER,
+ VECTOR_ANY,
+ VECTOR_INTEGER,
+ VECTOR_FLOAT,
+ VECTOR_POINTER,
};
constexpr static Kind toVector(Kind Ty) {
@@ -136,15 +136,9 @@ class LLT {
ScalarTy.isFloat() ? ScalarTy.getFPVariant()
: static_cast<FPVariant>(0)};
}
- // Get a 8-bit brain float value.
- static constexpr LLT bfloat8() {
- return floatingPoint(8, FPVariant::BRAIN_FLOAT);
- }
- // Get a 16-bit brain float value.
- static constexpr LLT bfloat16() {
- return floatingPoint(16, FPVariant::BRAIN_FLOAT);
- }
+ // Get a bfloat16 value.
+ static constexpr LLT bfloat16() { return floatingPoint(16, FPVariant::BF16); }
/// Get a 16-bit IEEE half value.
static constexpr LLT float16() {
@@ -231,7 +225,7 @@ class LLT {
constexpr bool isScalar(unsigned Size) const {
return isScalar() && getScalarSizeInBits() == Size;
}
- constexpr bool isFloat() const { return isValid() && Info == Kind::FLOAT; }
+ constexpr bool isFloat() const { return Info == Kind::FLOAT; }
constexpr bool isFloat(unsigned Size) const {
return isFloat() && getScalarSizeInBits() == Size;
}
@@ -244,14 +238,12 @@ class LLT {
constexpr bool isVariantFloat(unsigned Size, FPVariant Variant) const {
return isVariantFloat(Variant) && getScalarSizeInBits() == Size;
}
- constexpr bool isFloatVector() const {
- return isVector() && Info == Kind::VECTOR_FLOAT;
- }
+ constexpr bool isFloatVector() const { return Info == Kind::VECTOR_FLOAT; }
constexpr bool isIEEEFloat(unsigned Size) const {
return isVariantFloat(Size, FPVariant::IEEE_FLOAT);
}
constexpr bool isBFloat(unsigned Size) const {
- return isVariantFloat(Size, FPVariant::BRAIN_FLOAT);
+ return isVariantFloat(Size, FPVariant::BF16);
}
constexpr bool isX86FP80() const {
return isVariantFloat(80, FPVariant::EXTENDED_FP80);
@@ -262,31 +254,22 @@ class LLT {
constexpr bool isToken() const {
return Info == Kind::ANY_SCALAR && RawData == 0;
}
- constexpr bool isAnyScalar() const {
- return isValid() && Info == Kind::ANY_SCALAR;
- }
- constexpr bool isVectorAny() const {
- return isVector() && Info == Kind::VECTOR_ANY;
- }
- constexpr bool isInteger() const {
- return isValid() && Info == Kind::INTEGER;
- }
+ constexpr bool isAnyScalar() const { return Info == Kind::ANY_SCALAR; }
+ constexpr bool isVectorAny() const { return Info == Kind::VECTOR_ANY; }
+ constexpr bool isInteger() const { return Info == Kind::INTEGER; }
constexpr bool isInteger(unsigned Size) const {
return isInteger() && getScalarSizeInBits() == Size;
}
constexpr bool isIntegerVector() const {
- return isVector() && Info == Kind::VECTOR_INTEGER;
+ return Info == Kind::VECTOR_INTEGER;
}
constexpr bool isVector() const {
- return isValid() &&
- (Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER ||
- Info == Kind::VECTOR_FLOAT || Info == Kind::VECTOR_POINTER);
- }
- constexpr bool isPointer() const {
- return isValid() && Info == Kind::POINTER;
+ return Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER ||
+ Info == Kind::VECTOR_FLOAT || Info == Kind::VECTOR_POINTER;
}
+ constexpr bool isPointer() const { return Info == Kind::POINTER; }
constexpr bool isPointerVector() const {
- return isVector() && Info == Kind::VECTOR_POINTER;
+ return Info == Kind::VECTOR_POINTER;
}
constexpr bool isPointerOrPointerVector() const {
return isPointer() || isPointerVector();
@@ -469,13 +452,13 @@ class LLT {
#endif
constexpr bool operator==(const LLT &RHS) const {
- if (isAnyScalar() || RHS.isAnyScalar()) {
+ if (isAnyScalar() || RHS.isAnyScalar())
return isScalar() == RHS.isScalar() && RawData == RHS.RawData;
- }
- if (isVector() && RHS.isVector()) {
+
+ if (isVector() && RHS.isVector())
return getElementType() == RHS.getElementType() &&
getElementCount() == RHS.getElementCount();
- }
+
return Info == RHS.Info && RawData == RHS.RawData;
}
@@ -488,7 +471,7 @@ class LLT {
/// LLT is packed into 64 bits as follows:
/// Info : 4
/// RawData : 60
- /// with 61 bits of RawData remaining for Kind-specific data, packed in
+ /// with 60 bits of RawData remaining for Kind-specific data, packed in
/// bitfields as described below. As there isn't a simple portable way to pack
/// bits into bitfields, here the different fields in the packed structure is
/// described in static const *Field variables. Each of these variables
@@ -509,38 +492,52 @@ class LLT {
### (6)
%%%% (7)
- (1) ScalarSize (2) PointerSize (3) PointerAddressSpace
- (4) VectorElements (5) VectorScalable (6) FPVariant (7) Kind
+ (1) ScalarSize: [63:32]
+ (2) PointerSize: [63:48]
+ (3) PointerAddressSpace: [47:24]
+ (4) VectorElements: [23:8]
+ (5) VectorScalable: [4:4]
+ (6) FPVariant: [26:24]
+ (7) Kind: [3:0]
*/
- typedef int BitFieldInfo[2];
- ///
- /// This is how the bitfields are packed per Kind:
+
+ /// This is how the LLT are packed per Kind:
/// * Invalid:
- /// gets encoded as RawData == 0, as that is an invalid encoding, since for
- /// valid encodings, SizeInBits/SizeOfElement must be larger than 0.
+ /// Info: [3:0] = 0
+ /// RawData: [63:4] = 0;
+ ///
/// * Non-pointer scalar (isPointer == 0 && isVector == 0):
- /// SizeInBits: 32;
- /// FPInfoField: 3;
- static const constexpr BitFieldInfo ScalarSizeFieldInfo{32, 28};
- static const constexpr BitFieldInfo FPFieldInfo{3, 20};
+ /// Info: [3:0];
+ /// FPVariant: [26:24];
+ /// SizeOfElement: [63:32];
+ ///
/// * Pointer (isPointer == 1 && isVector == 0):
- /// SizeInBits: 16;
- /// AddressSpace: 24;
- static const constexpr BitFieldInfo PointerSizeFieldInfo{16, 44};
- static const constexpr BitFieldInfo PointerAddressSpaceFieldInfo{24, 20};
+ /// Info: [3:0];
+ /// AddressSpace: [47:24];
+ /// SizeInBits: [63:48];
+ ///
/// * Vector-of-non-pointer (isPointer == 0 && isVector == 1):
- /// NumElements: 16;
- /// SizeOfElement: 32;
- /// FPInfoField: 3;
- /// Scalable: 1;
- static const constexpr BitFieldInfo VectorElementsFieldInfo{16, 4};
- static const constexpr BitFieldInfo VectorScalableFieldInfo{1, 0};
+ /// Info: [3:0]
+ /// Scalable: [4:4];
+ /// VectorElements: [23:8];
+ /// FPVariant: [26:24];
+ /// SizeOfElement: [63:32];
+ ///
/// * Vector-of-pointer (isPointer == 1 && isVector == 1):
- /// NumElements: 16;
- /// SizeOfElement: 16;
- /// AddressSpace: 24;
- /// Scalable: 1;
+ /// Scalable: [4:4];
+ /// VectorElements: [23:8];
+ /// AddressSpace: [47:24];
+ /// SizeInBits: [63:48];
+
+ /// BitFieldInfo: {Size, Offset}
+ typedef int BitFieldInfo[2];
+ static const constexpr BitFieldInfo VectorScalableFieldInfo{1, 0};
+ static const constexpr BitFieldInfo VectorElementsFieldInfo{16, 4};
+ static const constexpr BitFieldInfo FPFieldInfo{3, 20};
+ static const constexpr BitFieldInfo PointerAddressSpaceFieldInfo{24, 20};
+ static const constexpr BitFieldInfo ScalarSizeFieldInfo{32, 28};
+ static const constexpr BitFieldInfo PointerSizeFieldInfo{16, 44};
Kind Info : 4;
uint64_t RawData : 60;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index ad1fb6331186e..7f48922ecfbef 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3723,9 +3723,8 @@ bool IRTranslator::translate(const Constant &C, Register Reg) {
}
bool IRTranslator::mayTranslateUserTypes(const User &U) const {
- if (TLI->getTargetMachine().Options.EnableGlobalISelExtendedLLT) {
+ if (TLI->getTargetMachine().Options.EnableGlobalISelExtendedLLT)
return true;
- }
// BF16 cannot currently be represented by default LLT, to avoid miscompiles
// we prevent any instructions using them in targets with disabled
diff --git a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
index 6a15b1748630d..57265b048125d 100644
--- a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
+++ b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
@@ -67,9 +67,8 @@ LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL, bool AllowExtendedLLT) {
llvm_unreachable("Unhandled LLVM IR floating point type");
}
- if (Ty.isIntegerTy()) {
+ if (Ty.isIntegerTy())
return LLT::integer(SizeInBits);
- }
return LLT::scalar(SizeInBits);
}
@@ -81,10 +80,9 @@ LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL, bool AllowExtendedLLT) {
}
MVT llvm::getMVTForLLT(LLT Ty) {
- if (Ty.isVector()) {
+ if (Ty.isVector())
return MVT::getVectorVT(getMVTForLLT(Ty.getElementType()),
Ty.getElementCount());
- }
if (Ty.isFloat()) {
if (Ty == LLT::bfloat16())
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 56dcb64feb30d..2e69ec6691591 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1971,7 +1971,7 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
if (Token.range().starts_with("f"))
FPVariant = LLT::FPVariant::IEEE_FLOAT;
else if (Token.range().starts_with("bf"))
- FPVariant = LLT::FPVariant::BRAIN_FLOAT;
+ FPVariant = LLT::FPVariant::BF16;
else
return error("unknown floating point type identifier");
@@ -2053,7 +2053,7 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
auto ScalarSize = APSInt(VectorTyDigits).getZExtValue();
if (!verifyScalarSize(ScalarSize))
return error("invalid size for bfloat element in vector");
- Ty = LLT::floatingPoint(ScalarSize, LLT::FPVariant::BRAIN_FLOAT);
+ Ty = LLT::floatingPoint(ScalarSize, LLT::FPVariant::BF16);
} else
return GetError();
lex();
diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index 6025f3fedafa1..c5995c179fa72 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -22,7 +22,7 @@ static std::optional<LLT::FPVariant> deriveFPInfo(MVT VT) {
switch (VT.getScalarType().SimpleTy) {
case MVT::bf16:
- return LLT::FPVariant::BRAIN_FLOAT;
+ return LLT::FPVariant::BF16;
case MVT::f80:
return LLT::FPVariant::EXTENDED_FP80;
case MVT::ppcf128:
>From d37eeb8c826eb2c27e93c8b1aba9b88c8e1dea1f Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Mon, 22 Sep 2025 23:56:05 +0300
Subject: [PATCH 13/41] typo
---
llvm/include/llvm/Target/TargetOptions.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index 0b81ded79c0b1..fff27c9601810 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -230,7 +230,7 @@ class TargetOptions {
/// EnableGlobalISel - This flag enables global instruction selection.
unsigned EnableGlobalISel : 1;
- /// EnableGlobalISelExtendedLLT - This flag enables LLTs with extenden type
+ /// EnableGlobalISelExtendedLLT - This flag enables LLTs with extended type
/// info so target may distinguish different formats of equal sized scalars.
unsigned EnableGlobalISelExtendedLLT : 1;
>From aba146b8deaf34186468ff24912cb7b2d5d65a40 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Tue, 23 Sep 2025 13:08:58 +0300
Subject: [PATCH 14/41] Small fix in test
---
llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
index c532634c19817..079f8dea377e0 100644
--- a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
@@ -111,13 +111,13 @@ TEST_F(AArch64IRTranslatorTest, IRTranslateBfloat16) {
llvm::MachineFunctionProperties::Property::FailedISel));
for (auto &MI : MF->front()) {
if (MI.getOpcode() == TargetOpcode::G_LOAD) {
- ASSERT_EQ(MRI.getType(MI.getOperand(0).getReg()), LLT::bfloat16());
+ ASSERT_TRUE(MRI.getType(MI.getOperand(0).getReg()).isBFloat(16));
}
if (MI.getOpcode() == TargetOpcode::G_FADD ||
MI.getOpcode() == TargetOpcode::G_FMUL) {
for (auto &Op : MI.operands()) {
- ASSERT_EQ(MRI.getType(Op.getReg()), LLT::bfloat16());
+ ASSERT_TRUE(MRI.getType(Op.getReg()).isBFloat(16));
}
}
}
>From a72d2a3f5066e609e51d50a90f62a80c5174149b Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Thu, 16 Oct 2025 14:58:08 +0300
Subject: [PATCH 15/41] Fixed misprints
---
.../TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index efd2a99f7104b..e689a2d3be283 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -26,7 +26,7 @@ using namespace gi;
static cl::opt<bool>
AllowExtendedLLT("gisel-extended-llt",
- cl::desc("Generate an extended llt names in match tables"),
+ cl::desc("Generate extended llt names in match tables"),
cl::init(false));
// FIXME: Use createStringError instead.
@@ -418,7 +418,7 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
if (Ty.isInteger())
OS << "LLT::integer(" << Ty.getScalarSizeInBits() << ")";
else if (Ty.isBFloat(16))
- OS << "LLT::bfloat()";
+ OS << "LLT::bfloat16()";
else if (Ty.isPPCF128())
OS << "LLT::ppcf128()";
else if (Ty.isX86FP80())
@@ -441,7 +441,7 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
if (ElemTy.isInteger())
OS << "LLT::integer(" << ElemTy.getScalarSizeInBits() << ")";
else if (ElemTy.isBFloat(16))
- OS << "LLT::bfloat()";
+ OS << "LLT::bfloat16()";
else if (ElemTy.isPPCF128())
OS << "LLT::ppcf128()";
else if (ElemTy.isX86FP80())
>From ce75915901e25a69bf6278f36ae525d112313e23 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Fri, 17 Oct 2025 16:12:29 +0300
Subject: [PATCH 16/41] Restructure LLT packed data. LLTCodeGen compare now
uses `getUniqueRAWLLTData`. Added simple test for GlobalSelEmitter
---
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 73 ++++++++++---------
.../GlobalISelEmitter/GlobalISelEmitter.td | 36 ++++++++-
.../TableGen/GlobalISelEmitter/HwModes.td | 10 +--
.../GlobalISel/GlobalISelMatchTable.cpp | 31 +-------
4 files changed, 76 insertions(+), 74 deletions(-)
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 31ac31d36e4a2..04e19d03c7c37 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -469,9 +469,9 @@ class LLT {
private:
/// LLT is packed into 64 bits as follows:
- /// Info : 4
/// RawData : 60
- /// with 60 bits of RawData remaining for Kind-specific data, packed in
+ /// Info : 4
+ /// RawData remaining for Kind-specific data, packed in
/// bitfields as described below. As there isn't a simple portable way to pack
/// bits into bitfields, here the different fields in the packed structure is
/// described in static const *Field variables. Each of these variables
@@ -484,51 +484,52 @@ class LLT {
63 56 47 39 31 23 15 7 0
| | | | | | | | |
|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|xxxxxxxx|
- ........ ........ ........ ........ (1)
- ******** ******** (2)
- ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ (3)
- ^^^^^^^^ ^^^^^^^^ (4)
- @ (5)
- ### (6)
- %%%% (7)
-
- (1) ScalarSize: [63:32]
- (2) PointerSize: [63:48]
- (3) PointerAddressSpace: [47:24]
- (4) VectorElements: [23:8]
- (5) VectorScalable: [4:4]
- (6) FPVariant: [26:24]
- (7) Kind: [3:0]
+ %%%% (1)
+ .... ........ ........ ........ .... (2)
+ **** ******** **** (3)
+ ~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~ (4)
+ ### (5)
+ ^^^^ ^^^^^^^^ ^^^^ (6)
+ @ (7)
+
+ (1) Kind: [63:60]
+ (2) ScalarSize: [59:28]
+ (3) PointerSize: [59:44]
+ (4) PointerAddressSpace: [43:20]
+ (5) FPVariant: [22:20]
+ (6) VectorElements: [19:4]
+ (7) VectorScalable: [0:0]
*/
/// This is how the LLT are packed per Kind:
/// * Invalid:
- /// Info: [3:0] = 0
- /// RawData: [63:4] = 0;
+ /// Info: [63:60] = 0
+ /// RawData: [59:0] = 0;
///
/// * Non-pointer scalar (isPointer == 0 && isVector == 0):
- /// Info: [3:0];
- /// FPVariant: [26:24];
- /// SizeOfElement: [63:32];
+ /// Info: [63:60];
+ /// SizeOfElement: [59:28];
+ /// FPVariant: [22:20];
///
/// * Pointer (isPointer == 1 && isVector == 0):
- /// Info: [3:0];
- /// AddressSpace: [47:24];
- /// SizeInBits: [63:48];
+ /// Info: [63:60];
+ /// SizeInBits: [59:44];
+ /// AddressSpace: [43:20];
///
/// * Vector-of-non-pointer (isPointer == 0 && isVector == 1):
- /// Info: [3:0]
- /// Scalable: [4:4];
- /// VectorElements: [23:8];
- /// FPVariant: [26:24];
- /// SizeOfElement: [63:32];
+ /// Info: [63:60]
+ /// SizeOfElement: [59:28];
+ /// FPVariant: [22:20];
+ /// VectorElements: [19:4];
+ /// Scalable: [0:0];
///
/// * Vector-of-pointer (isPointer == 1 && isVector == 1):
- /// Scalable: [4:4];
- /// VectorElements: [23:8];
- /// AddressSpace: [47:24];
- /// SizeInBits: [63:48];
+ /// Info: [63:60];
+ /// SizeInBits: [59:44];
+ /// AddressSpace: [43:20];
+ /// VectorElements: [19:4];
+ /// Scalable: [0:0];
/// BitFieldInfo: {Size, Offset}
typedef int BitFieldInfo[2];
@@ -539,8 +540,8 @@ class LLT {
static const constexpr BitFieldInfo ScalarSizeFieldInfo{32, 28};
static const constexpr BitFieldInfo PointerSizeFieldInfo{16, 44};
- Kind Info : 4;
uint64_t RawData : 60;
+ Kind Info : 4;
static constexpr uint64_t getMask(const BitFieldInfo FieldInfo) {
const int FieldSizeInBits = FieldInfo[0];
@@ -582,7 +583,7 @@ class LLT {
public:
constexpr uint64_t getUniqueRAWLLTData() const {
- return ((uint64_t)RawData) << 4 | ((uint64_t)Info);
+ return ((uint64_t)RawData) | ((uint64_t)Info) << 60;
}
};
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index fdabc53a3ff3b..d889523950a91 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -1,6 +1,7 @@
// RUN: llvm-tblgen -gen-global-isel -I %p/../../../include -I %p/../Common -optimize-match-table=false %s -o %t.non-optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../../include -I %p/../Common -optimize-match-table=true %s -o %t.optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../../include -I %p/../Common %s -o %t.default.cpp
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../../include -I %p/../Common -gisel-extended-llt %s -o %t.extended-llt.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%t.non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%t.optimized.cpp
@@ -19,6 +20,7 @@
// RUN: FileCheck %s --check-prefixes=CHECK,R02C,R02N,NOOPT -input-file=%t.non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R02C,R02O -input-file=%t.optimized.cpp
+// RUN: FileCheck %s --check-prefixes=EXTENDED -input-file=%t.extended-llt.cpp
// RUN: diff %t.default.cpp %t.optimized.cpp
@@ -94,15 +96,28 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// CHECK-LABEL: // LLT Objects.
// CHECK-NEXT: enum {
-// CHECK-NEXT: GILLT_p0s32
// CHECK-NEXT: GILLT_s32,
-// CHECK-NEXT: }
+// CHECK-NEXT: GILLT_p0s32,
+// CHECK-NEXT: };
// CHECK-NEXT: const static size_t NumTypeObjects = 2;
// CHECK-NEXT: const static LLT TypeObjects[] = {
-// CHECK-NEXT: LLT::pointer(0, 32),
// CHECK-NEXT: LLT::scalar(32),
+// CHECK-NEXT: LLT::pointer(0, 32),
// CHECK-NEXT: };
+// EXTENDED-LABEL: // LLT Objects.
+// EXTENDED-NEXT: enum {
+// EXTENDED-NEXT: GILLT_i32,
+// EXTENDED-NEXT: GILLT_f32,
+// EXTENDED-NEXT: GILLT_p0s32,
+// EXTENDED-NEXT: };
+// EXTENDED-NEXT: const static size_t NumTypeObjects = 3;
+// EXTENDED-NEXT: const static LLT TypeObjects[] = {
+// EXTENDED-NEXT: LLT::integer(32),
+// EXTENDED-NEXT: LLT::floatingPoint(32, LLT::FPVariant::IEEE_FLOAT),
+// EXTENDED-NEXT: LLT::pointer(0, 32),
+// EXTENDED-NEXT: };
+
// CHECK-LABEL: enum SubtargetFeatureBits : uint8_t {
// CHECK-NEXT: Feature_HasABit = 0,
// CHECK-NEXT: Feature_HasBBit = 1,
@@ -251,6 +266,10 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// CHECK-LABEL: MyTargetInstructionSelector::getMatchTable() const {
// CHECK-NEXT: MatchTable0[] = {
+// EXTENDED: const uint8_t *
+// EXTENDED-LABEL: MyTargetInstructionSelector::getMatchTable() const {
+// EXTENDED-NEXT: MatchTable0[] = {
+
//===- Test a pattern with multiple ComplexPatterns in multiple instrs ----===//
//
// R19O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ GIMT_Encode4([[DEFAULT:[0-9]+]]),
@@ -328,6 +347,17 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// R19O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
// R19O-NEXT: GIM_Reject,
// R19O-NEXT: };
+//
+// EXTENDED-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ GIMT_Encode4([[DEFAULT:[0-9]+]]),
+// EXTENDED-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_ADD:[0-9]+]]),
+// EXTENDED: /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_SELECT:[0-9]+]]),
+// EXTENDED: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
+// EXTENDED: // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]]
+// EXTENDED-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]),
+// EXTENDED-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_i32,
+// EXTENDED-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_i32,
+// EXTENDED-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_i32,
+// EXTENDED-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_i32,
def INSN3 : I<(outs GPR32:$dst),
(ins GPR32Op:$src1, GPR32:$src2a, GPR32:$src2b, GPR32:$scr), []>;
diff --git a/llvm/test/TableGen/GlobalISelEmitter/HwModes.td b/llvm/test/TableGen/GlobalISelEmitter/HwModes.td
index 56d62ca070889..00be337183b07 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/HwModes.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/HwModes.td
@@ -66,17 +66,17 @@ class I<dag OOps, dag IOps, list<dag> Pat>
// CHECK-LABEL: // LLT Objects.
// CHECK-NEXT: enum {
-// CHECK-NEXT: GILLT_p0s32,
-// CHECK-NEXT: GILLT_p0s64,
// CHECK-NEXT: GILLT_s32,
// CHECK-NEXT: GILLT_s64,
-// CHECK-NEXT: }
+// CHECK-NEXT: GILLT_p0s32,
+// CHECK-NEXT: GILLT_p0s64,
+// CHECK-NEXT: };
// CHECK-NEXT: const static size_t NumTypeObjects = 4;
// CHECK-NEXT: const static LLT TypeObjects[] = {
-// CHECK-NEXT: LLT::pointer(0, 32),
-// CHECK-NEXT: LLT::pointer(0, 64),
// CHECK-NEXT: LLT::scalar(32),
// CHECK-NEXT: LLT::scalar(64),
+// CHECK-NEXT: LLT::pointer(0, 32),
+// CHECK-NEXT: LLT::pointer(0, 64),
// CHECK-NEXT: };
// CHECK-LABEL: enum SubtargetFeatureBits : uint8_t {
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index e689a2d3be283..c5cdea5c1c753 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -468,36 +468,7 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
/// particular logic behind the order but either A < B or B < A must be
/// true if A != B.
bool LLTCodeGen::operator<(const LLTCodeGen &Other) const {
- if (Ty.isValid() != Other.Ty.isValid())
- return Ty.isValid() < Other.Ty.isValid();
- if (!Ty.isValid())
- return false;
-
- if (Ty.isVector() != Other.Ty.isVector())
- return Ty.isVector() < Other.Ty.isVector();
- if (Ty.isScalar() != Other.Ty.isScalar())
- return Ty.isScalar() < Other.Ty.isScalar();
- if (Ty.isPointer() != Other.Ty.isPointer())
- return Ty.isPointer() < Other.Ty.isPointer();
-
- if (Ty.isPointer() && Ty.getAddressSpace() != Other.Ty.getAddressSpace())
- return Ty.getAddressSpace() < Other.Ty.getAddressSpace();
-
- if (Ty.isVector() && Ty.getElementCount() != Other.Ty.getElementCount())
- return std::tuple(Ty.isScalable(),
- Ty.getElementCount().getKnownMinValue()) <
- std::tuple(Other.Ty.isScalable(),
- Other.Ty.getElementCount().getKnownMinValue());
-
- assert((!Ty.isVector() || Ty.isScalable() == Other.Ty.isScalable()) &&
- "Unexpected mismatch of scalable property");
- return Ty.isVector()
- ? std::tuple(Ty.isScalable(),
- Ty.getSizeInBits().getKnownMinValue()) <
- std::tuple(Other.Ty.isScalable(),
- Other.Ty.getSizeInBits().getKnownMinValue())
- : Ty.getSizeInBits().getFixedValue() <
- Other.Ty.getSizeInBits().getFixedValue();
+ return Ty.getUniqueRAWLLTData() < Other.Ty.getUniqueRAWLLTData();
}
//===- LLTCodeGen Helpers -------------------------------------------------===//
>From 74e1cf875244f6de889ce138ea667e0dbb4bb158 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Fri, 17 Oct 2025 16:39:32 +0300
Subject: [PATCH 17/41] initialization fix
---
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 04e19d03c7c37..aac77737c411f 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -215,7 +215,7 @@ class LLT {
}
LLVM_ABI explicit LLT(MVT VT, bool AllowExtendedLLT = false);
- explicit constexpr LLT() : Info(static_cast<Kind>(0)), RawData(0) {}
+ explicit constexpr LLT() : RawData(0), Info(static_cast<Kind>(0)) {}
constexpr bool isValid() const { return isToken() || RawData != 0; }
constexpr bool isScalar() const {
>From 664b6445c7b5a146297cf2c61675d708616b0334 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Thu, 30 Oct 2025 15:36:58 +0300
Subject: [PATCH 18/41] Link CodeGenTypes to TableGenCommon
---
llvm/utils/TableGen/Common/CMakeLists.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/utils/TableGen/Common/CMakeLists.txt b/llvm/utils/TableGen/Common/CMakeLists.txt
index 66279a3ed3755..b49f36b937c42 100644
--- a/llvm/utils/TableGen/Common/CMakeLists.txt
+++ b/llvm/utils/TableGen/Common/CMakeLists.txt
@@ -43,6 +43,9 @@ add_llvm_library(LLVMTableGenCommon STATIC OBJECT EXCLUDE_FROM_ALL DISABLE_LLVM_
DEPENDS
vt_gen
intrinsics_gen
+
+ LINK_COMPONENTS
+ CodeGenTypes
)
# Users may include its headers as "Common/*.h"
>From cb0dc5fc83f4d7c6bd2eb91fe114c59f165d414d Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Mon, 10 Nov 2025 20:59:15 +0300
Subject: [PATCH 19/41] Fix misprint
---
llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 696bd64c22d13..525f222d4ae25 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -396,7 +396,7 @@ void LLTCodeGen::emitCxxEnumValue(raw_ostream &OS) const {
OS << "x86fp80";
else if (ElemTy.isFloat())
OS << "f" << ElemTy.getSizeInBits();
- else if (Ty.isInteger())
+ else if (ElemTy.isInteger())
OS << "i" << ElemTy.getSizeInBits();
else
OS << "s" << ElemTy.getSizeInBits();
>From e076732fe2304e8e4d1d6dbd8c1fc7e8aba9d36f Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Tue, 11 Nov 2025 15:04:57 +0300
Subject: [PATCH 20/41] format
---
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 097362cf86956..d7c5508aec27a 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3820,9 +3820,9 @@ bool IRTranslator::mayTranslateUserTypes(const User &U) const {
// SPIRV target is exception.
return TM.getTargetTriple().isSPIRV() ||
(!U.getType()->getScalarType()->isBFloatTy() &&
- !any_of(U.operands(), [](Value *V) {
- return V->getType()->getScalarType()->isBFloatTy();
- }));
+ !any_of(U.operands(), [](Value *V) {
+ return V->getType()->getScalarType()->isBFloatTy();
+ }));
}
bool IRTranslator::finalizeBasicBlock(const BasicBlock &BB,
>From 24c0af1925527b0ec8ca6859bf7dafc0283fc6dc Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sat, 15 Nov 2025 16:08:25 +0300
Subject: [PATCH 21/41] Replace FPVariant with APFloat::Semantics
---
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 189 ++++++++++--------
llvm/lib/CodeGen/LowLevelTypeUtils.cpp | 34 ++--
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 19 +-
llvm/lib/CodeGenTypes/LowLevelType.cpp | 47 +++--
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 12 +-
.../GlobalISelEmitter/GlobalISelEmitter.td | 2 +-
.../GlobalISel/IRTranslatorBF16Test.cpp | 4 +-
.../GlobalISel/GlobalISelMatchTable.cpp | 14 +-
8 files changed, 166 insertions(+), 155 deletions(-)
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 80e4aae388c71..1456700ce0bb1 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -26,10 +26,13 @@
#ifndef LLVM_CODEGEN_LOWLEVELTYPE_H
#define LLVM_CODEGEN_LOWLEVELTYPE_H
+#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/DenseMapInfo.h"
+#include "llvm/ADT/bit.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include <cassert>
namespace llvm {
@@ -39,16 +42,7 @@ class raw_ostream;
class LLT {
public:
- enum class FPVariant {
- IEEE_FLOAT,
- BF16, // BF16
- TENSOR_FLOAT32, // TENSOR_FLOAT32
- EXTENDED_FP80, // FP80
- PPC128_FLOAT, // PPC128_FLOAT
- VARIANT_FLOAT_5, // UNASSIGNED
- VARIANT_FLOAT_6, // UNASSIGNED
- VARIANT_FLOAT_7, // UNASSIGNED
- };
+ using FpSemantics = APFloat::Semantics;
enum class Kind : uint8_t {
INVALID,
@@ -91,38 +85,39 @@ class LLT {
/// Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT scalar(unsigned SizeInBits) {
return LLT{Kind::ANY_SCALAR, ElementCount::getFixed(0), SizeInBits,
- /*AddressSpace=*/0, static_cast<FPVariant>(0)};
+ /*AddressSpace=*/0, static_cast<FpSemantics>(0)};
}
static constexpr LLT integer(unsigned SizeInBits) {
return LLT{Kind::INTEGER, ElementCount::getFixed(0), SizeInBits,
- /*AddressSpace=*/0, static_cast<FPVariant>(0)};
+ /*AddressSpace=*/0, static_cast<FpSemantics>(0)};
}
- static constexpr LLT floatingPoint(unsigned SizeInBits, FPVariant FP) {
- return LLT{Kind::FLOAT, ElementCount::getFixed(0), SizeInBits,
- /*AddressSpace=*/0, FP};
+ static LLT floatingPoint(const FpSemantics &Sem) {
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0),
+ APFloat::getSizeInBits(APFloatBase::EnumToSemantics(Sem)),
+ /*AddressSpace=*/0, Sem};
}
/// Get a low-level token; just a scalar with zero bits (or no size).
static constexpr LLT token() {
return LLT{Kind::ANY_SCALAR, ElementCount::getFixed(0),
/*SizeInBits=*/0,
- /*AddressSpace=*/0, static_cast<FPVariant>(0)};
+ /*AddressSpace=*/0, static_cast<FpSemantics>(0)};
}
/// Get a low-level pointer in the given address space.
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits) {
assert(SizeInBits > 0 && "invalid pointer size");
return LLT{Kind::POINTER, ElementCount::getFixed(0), SizeInBits,
- AddressSpace, static_cast<FPVariant>(0)};
+ AddressSpace, static_cast<FpSemantics>(0)};
}
/// Get a low-level vector of some number of elements and element width.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits) {
assert(!EC.isScalar() && "invalid number of vector elements");
return LLT{Kind::VECTOR_ANY, EC, ScalarSizeInBits,
- /*AddressSpace=*/0, static_cast<FPVariant>(0)};
+ /*AddressSpace=*/0, static_cast<FpSemantics>(0)};
}
/// Get a low-level vector of some number of elements and element type.
@@ -133,41 +128,62 @@ class LLT {
Kind Info = toVector(ScalarTy.Info);
return LLT{Info, EC, ScalarTy.getSizeInBits().getFixedValue(),
ScalarTy.isPointer() ? ScalarTy.getAddressSpace() : 0,
- ScalarTy.isFloat() ? ScalarTy.getFPVariant()
- : static_cast<FPVariant>(0)};
+ ScalarTy.isFloat() ? ScalarTy.getFpSemantics()
+ : static_cast<FpSemantics>(0)};
+ }
+
+ static constexpr LLT floatIEEE(unsigned SizeInBits) {
+ switch (SizeInBits) {
+ default:
+ llvm_unreachable("Wrong SizeInBits for IEEE Floating point!");
+ case 16:
+ return float16();
+ case 32:
+ return float32();
+ case 64:
+ return float64();
+ case 128:
+ return float128();
+ }
}
// Get a bfloat16 value.
- static constexpr LLT bfloat16() { return floatingPoint(16, FPVariant::BF16); }
-
+ static constexpr LLT bfloat16() {
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 16, 0,
+ FpSemantics::S_BFloat};
+ }
/// Get a 16-bit IEEE half value.
static constexpr LLT float16() {
- return floatingPoint(16, FPVariant::IEEE_FLOAT);
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 16, 0,
+ FpSemantics::S_IEEEhalf};
}
-
/// Get a 32-bit IEEE float value.
static constexpr LLT float32() {
- return floatingPoint(32, FPVariant::IEEE_FLOAT);
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 32, 0,
+ FpSemantics::S_IEEEsingle};
}
-
/// Get a 64-bit IEEE double value.
static constexpr LLT float64() {
- return floatingPoint(64, FPVariant::IEEE_FLOAT);
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 64, 0,
+ FpSemantics::S_IEEEdouble};
}
/// Get a 80-bit X86 floating point value.
static constexpr LLT x86fp80() {
- return floatingPoint(80, FPVariant::EXTENDED_FP80);
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 80, 0,
+ FpSemantics::S_x87DoubleExtended};
}
/// Get a 128-bit IEEE quad value.
static constexpr LLT float128() {
- return floatingPoint(128, FPVariant::IEEE_FLOAT);
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 128, 0,
+ FpSemantics::S_IEEEquad};
}
/// Get a 128-bit PowerPC double double value.
static constexpr LLT ppcf128() {
- return floatingPoint(128, FPVariant::PPC128_FLOAT);
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 128, 0,
+ FpSemantics::S_PPCDoubleDouble};
}
/// Get a low-level fixed-width vector of some number of elements and element
@@ -209,15 +225,34 @@ class LLT {
}
explicit constexpr LLT(Kind Info, ElementCount EC, uint64_t SizeInBits,
- unsigned AddressSpace, FPVariant FP)
+ unsigned AddressSpace, FpSemantics Sem)
: LLT() {
- init(Info, EC, SizeInBits, AddressSpace, FP);
+ init(Info, EC, SizeInBits, AddressSpace, Sem);
}
LLVM_ABI explicit LLT(MVT VT, bool AllowExtendedLLT = false);
explicit constexpr LLT() : RawData(0), Info(static_cast<Kind>(0)) {}
+ constexpr bool isToken() const {
+ return Info == Kind::ANY_SCALAR && RawData == 0;
+ }
constexpr bool isValid() const { return isToken() || RawData != 0; }
+ constexpr bool isAnyScalar() const { return Info == Kind::ANY_SCALAR; }
+ constexpr bool isInteger() const { return Info == Kind::INTEGER; }
+ constexpr bool isFloat() const { return Info == Kind::FLOAT; }
+ constexpr bool isPointer() const { return Info == Kind::POINTER; }
+ constexpr bool isVectorAny() const { return Info == Kind::VECTOR_ANY; }
+ constexpr bool isIntegerVector() const {
+ return Info == Kind::VECTOR_INTEGER;
+ }
+ constexpr bool isFloatVector() const { return Info == Kind::VECTOR_FLOAT; }
+ constexpr bool isPointerVector() const {
+ return Info == Kind::VECTOR_POINTER;
+ }
+ constexpr bool isPointerOrPointerVector() const {
+ return isPointer() || isPointerVector();
+ }
+
constexpr bool isScalar() const {
return Info == Kind::ANY_SCALAR || Info == Kind::INTEGER ||
Info == Kind::FLOAT;
@@ -225,54 +260,35 @@ class LLT {
constexpr bool isScalar(unsigned Size) const {
return isScalar() && getScalarSizeInBits() == Size;
}
- constexpr bool isFloat() const { return Info == Kind::FLOAT; }
- constexpr bool isFloat(unsigned Size) const {
- return isFloat() && getScalarSizeInBits() == Size;
+ constexpr bool isVector() const {
+ return Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER ||
+ Info == Kind::VECTOR_FLOAT || Info == Kind::VECTOR_POINTER;
}
- constexpr bool isVariantFloat() const {
- return isFloat() && getFPVariant() != FPVariant::IEEE_FLOAT;
+
+ constexpr bool isInteger(unsigned Size) const {
+ return isInteger() && getScalarSizeInBits() == Size;
}
- constexpr bool isVariantFloat(FPVariant Variant) const {
- return isFloat() && getFPVariant() == Variant;
+
+ constexpr bool isFloat(unsigned Size) const {
+ return isFloat() && getScalarSizeInBits() == Size;
}
- constexpr bool isVariantFloat(unsigned Size, FPVariant Variant) const {
- return isVariantFloat(Variant) && getScalarSizeInBits() == Size;
+ constexpr bool isFloatWithSem(FpSemantics Sem) const {
+ return isFloat() && getFpSemantics() == Sem;
}
- constexpr bool isFloatVector() const { return Info == Kind::VECTOR_FLOAT; }
- constexpr bool isIEEEFloat(unsigned Size) const {
- return isVariantFloat(Size, FPVariant::IEEE_FLOAT);
+ constexpr bool isFloatIEEE() const {
+ return isFloatWithSem(APFloatBase::S_IEEEhalf) ||
+ isFloatWithSem(APFloatBase::S_IEEEsingle) ||
+ isFloatWithSem(APFloatBase::S_IEEEdouble) ||
+ isFloatWithSem(APFloatBase::S_IEEEquad);
}
- constexpr bool isBFloat(unsigned Size) const {
- return isVariantFloat(Size, FPVariant::BF16);
+ constexpr bool isBFloat16() const {
+ return isFloatWithSem(FpSemantics::S_BFloat);
}
constexpr bool isX86FP80() const {
- return isVariantFloat(80, FPVariant::EXTENDED_FP80);
+ return isFloatWithSem(FpSemantics::S_x87DoubleExtended);
}
constexpr bool isPPCF128() const {
- return isVariantFloat(128, FPVariant::PPC128_FLOAT);
- }
- constexpr bool isToken() const {
- return Info == Kind::ANY_SCALAR && RawData == 0;
- }
- constexpr bool isAnyScalar() const { return Info == Kind::ANY_SCALAR; }
- constexpr bool isVectorAny() const { return Info == Kind::VECTOR_ANY; }
- constexpr bool isInteger() const { return Info == Kind::INTEGER; }
- constexpr bool isInteger(unsigned Size) const {
- return isInteger() && getScalarSizeInBits() == Size;
- }
- constexpr bool isIntegerVector() const {
- return Info == Kind::VECTOR_INTEGER;
- }
- constexpr bool isVector() const {
- return Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER ||
- Info == Kind::VECTOR_FLOAT || Info == Kind::VECTOR_POINTER;
- }
- constexpr bool isPointer() const { return Info == Kind::POINTER; }
- constexpr bool isPointerVector() const {
- return Info == Kind::VECTOR_POINTER;
- }
- constexpr bool isPointerOrPointerVector() const {
- return isPointer() || isPointerVector();
+ return isFloatWithSem(FpSemantics::S_PPCDoubleDouble);
}
/// Returns the number of elements in a vector LLT. Must only be called on
@@ -333,11 +349,10 @@ class LLT {
return isVector() ? getElementType() : *this;
}
- constexpr FPVariant getFPVariant() const {
+ constexpr FpSemantics getFpSemantics() const {
assert((isFloat() || isFloatVector()) &&
"cannot get FP info for non float type");
-
- return FPVariant(getFieldValue(FPFieldInfo));
+ return FpSemantics(getFieldValue(FpSemanticFieldInfo));
}
constexpr Kind getKind() const { return Info; }
@@ -427,7 +442,7 @@ class LLT {
return pointer(getAddressSpace(), getScalarSizeInBits());
if (isFloatVector())
- return floatingPoint(getScalarSizeInBits(), getFPVariant());
+ return floatingPoint(getFpSemantics());
if (isIntegerVector())
return integer(getScalarSizeInBits());
@@ -453,7 +468,8 @@ class LLT {
constexpr bool operator==(const LLT &RHS) const {
if (isAnyScalar() || RHS.isAnyScalar())
- return isScalar() == RHS.isScalar() && RawData == RHS.RawData;
+ return isScalar() == RHS.isScalar() &&
+ getScalarSizeInBits() == RHS.getScalarSizeInBits();
if (isVector() && RHS.isVector())
return getElementType() == RHS.getElementType() &&
@@ -488,7 +504,7 @@ class LLT {
.... ........ ........ ........ .... (2)
**** ******** **** (3)
~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~ (4)
- ### (5)
+ #### #### (5)
^^^^ ^^^^^^^^ ^^^^ (6)
@ (7)
@@ -496,7 +512,7 @@ class LLT {
(2) ScalarSize: [59:28]
(3) PointerSize: [59:44]
(4) PointerAddressSpace: [43:20]
- (5) FPVariant: [22:20]
+ (5) FpSemantics: [27:20]
(6) VectorElements: [19:4]
(7) VectorScalable: [0:0]
@@ -510,7 +526,7 @@ class LLT {
/// * Non-pointer scalar (isPointer == 0 && isVector == 0):
/// Info: [63:60];
/// SizeOfElement: [59:28];
- /// FPVariant: [22:20];
+ /// FpSemantics: [27:20];
///
/// * Pointer (isPointer == 1 && isVector == 0):
/// Info: [63:60];
@@ -520,7 +536,7 @@ class LLT {
/// * Vector-of-non-pointer (isPointer == 0 && isVector == 1):
/// Info: [63:60]
/// SizeOfElement: [59:28];
- /// FPVariant: [22:20];
+ /// FpSemantics: [27:20];
/// VectorElements: [19:4];
/// Scalable: [0:0];
///
@@ -533,9 +549,10 @@ class LLT {
/// BitFieldInfo: {Size, Offset}
typedef int BitFieldInfo[2];
+ static_assert(bit_width_constexpr((uint32_t)APFloat::S_MaxSemantics) <= 8);
static constexpr BitFieldInfo VectorScalableFieldInfo{1, 0};
static constexpr BitFieldInfo VectorElementsFieldInfo{16, 4};
- static constexpr BitFieldInfo FPFieldInfo{3, 20};
+ static constexpr BitFieldInfo FpSemanticFieldInfo{8, 20};
static constexpr BitFieldInfo PointerAddressSpaceFieldInfo{24, 20};
static constexpr BitFieldInfo ScalarSizeFieldInfo{32, 28};
static constexpr BitFieldInfo PointerSizeFieldInfo{16, 44};
@@ -562,7 +579,7 @@ class LLT {
}
constexpr void init(Kind Info, ElementCount EC, uint64_t SizeInBits,
- unsigned AddressSpace, FPVariant FP) {
+ unsigned AddressSpace, FpSemantics Sem) {
assert(SizeInBits <= std::numeric_limits<unsigned>::max() &&
"Not enough bits in LLT to represent size");
this->Info = Info;
@@ -571,7 +588,7 @@ class LLT {
maskAndShift(AddressSpace, PointerAddressSpaceFieldInfo);
} else {
RawData = maskAndShift(SizeInBits, ScalarSizeFieldInfo) |
- maskAndShift((uint64_t)FP, FPFieldInfo);
+ maskAndShift((uint64_t)Sem, FpSemanticFieldInfo);
}
if (Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER ||
@@ -587,7 +604,7 @@ class LLT {
}
};
-inline raw_ostream& operator<<(raw_ostream &OS, const LLT &Ty) {
+inline raw_ostream &operator<<(raw_ostream &OS, const LLT &Ty) {
Ty.print(OS);
return OS;
}
@@ -607,9 +624,7 @@ template <> struct DenseMapInfo<LLT> {
uint64_t Val = Ty.getUniqueRAWLLTData();
return DenseMapInfo<uint64_t>::getHashValue(Val);
}
- static bool isEqual(const LLT &LHS, const LLT &RHS) {
- return LHS == RHS;
- }
+ static bool isEqual(const LLT &LHS, const LLT &RHS) { return LHS == RHS; }
};
} // namespace llvm
diff --git a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
index 57265b048125d..b3f397610c71c 100644
--- a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
+++ b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
@@ -117,24 +117,20 @@ const llvm::fltSemantics &llvm::getFltSemanticForLLT(LLT Ty) {
assert((Ty.isAnyScalar() || Ty.isFloat()) &&
"Expected a any scalar or float type.");
- if (Ty.isBFloat(16))
- return APFloat::BFloat();
- if (Ty.isX86FP80())
- return APFloat::x87DoubleExtended();
- if (Ty.isPPCF128())
- return APFloat::PPCDoubleDouble();
-
- assert(!Ty.isVariantFloat() && "Unhandled variant float type");
-
- switch (Ty.getSizeInBits()) {
- case 16:
- return APFloat::IEEEhalf();
- case 32:
- return APFloat::IEEEsingle();
- case 64:
- return APFloat::IEEEdouble();
- case 128:
- return APFloat::IEEEquad();
+ if (Ty.isAnyScalar()) {
+ switch (Ty.getSizeInBits()) {
+ default:
+ llvm_unreachable("Invalid FP type size.");
+ case 16:
+ return APFloat::IEEEhalf();
+ case 32:
+ return APFloat::IEEEsingle();
+ case 64:
+ return APFloat::IEEEdouble();
+ case 128:
+ return APFloat::IEEEquad();
+ }
}
- llvm_unreachable("Invalid FP type size.");
+
+ return APFloat::EnumToSemantics(Ty.getFpSemantics());
}
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 8497ee7b17fef..8f431640da154 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1969,18 +1969,15 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
}
if (Token.range().starts_with("f") || Token.range().starts_with("bf")) {
- LLT::FPVariant FPVariant;
- if (Token.range().starts_with("f"))
- FPVariant = LLT::FPVariant::IEEE_FLOAT;
- else if (Token.range().starts_with("bf"))
- FPVariant = LLT::FPVariant::BF16;
- else
- return error("unknown floating point type identifier");
-
auto ScalarSize = APSInt(TypeDigits).getZExtValue();
if (!ScalarSize || !verifyScalarSize(ScalarSize))
return error("invalid size for scalar type");
- Ty = LLT::floatingPoint(ScalarSize, FPVariant);
+
+ if (Token.range().starts_with("bf") && ScalarSize != 16)
+ return error("invalid size for bfloat");
+
+ Ty = Token.range().starts_with("bf") ? LLT::bfloat16()
+ : LLT::floatIEEE(ScalarSize);
lex();
return false;
}
@@ -2050,12 +2047,12 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
auto ScalarSize = APSInt(VectorTyDigits).getZExtValue();
if (!verifyScalarSize(ScalarSize))
return error("invalid size for float element in vector");
- Ty = LLT::floatingPoint(ScalarSize, LLT::FPVariant::IEEE_FLOAT);
+ Ty = LLT::floatIEEE(ScalarSize);
} else if (Token.range().starts_with("bf")) {
auto ScalarSize = APSInt(VectorTyDigits).getZExtValue();
if (!verifyScalarSize(ScalarSize))
return error("invalid size for bfloat element in vector");
- Ty = LLT::floatingPoint(ScalarSize, LLT::FPVariant::BF16);
+ Ty = LLT::bfloat16();
} else
return GetError();
lex();
diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index 96b7a33783fba..229c9d542fe9e 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -16,19 +16,25 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
-static std::optional<LLT::FPVariant> deriveFPInfo(MVT VT) {
- if (!VT.isFloatingPoint())
- return std::nullopt;
-
+// Repeat logic of MVT::getFltSemantics to exclude CodeGen dependency
+static LLT::FpSemantics getFpSemanticsForMVT(MVT VT) {
switch (VT.getScalarType().SimpleTy) {
+ default:
+ llvm_unreachable("Unknown FP format");
+ case MVT::f16:
+ return LLT::FpSemantics::S_IEEEhalf;
case MVT::bf16:
- return LLT::FPVariant::BF16;
+ return LLT::FpSemantics::S_BFloat;
+ case MVT::f32:
+ return LLT::FpSemantics::S_IEEEsingle;
+ case MVT::f64:
+ return LLT::FpSemantics::S_IEEEdouble;
case MVT::f80:
- return LLT::FPVariant::EXTENDED_FP80;
+ return LLT::FpSemantics::S_x87DoubleExtended;
+ case MVT::f128:
+ return LLT::FpSemantics::S_IEEEquad;
case MVT::ppcf128:
- return LLT::FPVariant::PPC128_FLOAT;
- default:
- return LLT::FPVariant::IEEE_FLOAT;
+ return LLT::FpSemantics::S_PPCDoubleDouble;
}
}
@@ -38,10 +44,11 @@ LLT::LLT(MVT VT, bool AllowExtendedLLT) {
bool AsVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector();
Kind Info = AsVector ? Kind::VECTOR_ANY : Kind::ANY_SCALAR;
init(Info, VT.getVectorElementCount(),
- VT.getVectorElementType().getSizeInBits(), 0, FPVariant::IEEE_FLOAT);
+ VT.getVectorElementType().getSizeInBits(), 0,
+ static_cast<FpSemantics>(0));
} else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
init(Kind::ANY_SCALAR, ElementCount::getFixed(0), VT.getSizeInBits(), 0,
- FPVariant::IEEE_FLOAT);
+ static_cast<FpSemantics>(0));
} else {
this->Info = Kind::INVALID;
this->RawData = 0;
@@ -49,25 +56,24 @@ LLT::LLT(MVT VT, bool AllowExtendedLLT) {
return;
}
- auto FP = deriveFPInfo(VT);
+ bool IsFloatingPoint = VT.isFloatingPoint();
+ FpSemantics FpSem =
+ IsFloatingPoint ? getFpSemanticsForMVT(VT) : static_cast<FpSemantics>(0);
bool AsVector = VT.isVector() &&
(VT.getVectorMinNumElements() > 1 || VT.isScalableVector());
-
LLT::Kind Info;
- if (FP.has_value())
+ if (IsFloatingPoint)
Info = AsVector ? LLT::Kind::VECTOR_FLOAT : LLT::Kind::FLOAT;
else
Info = AsVector ? LLT::Kind::VECTOR_INTEGER : LLT::Kind::INTEGER;
if (VT.isVector()) {
init(Info, VT.getVectorElementCount(),
- VT.getVectorElementType().getSizeInBits(), 0,
- FP.value_or(LLT::FPVariant::IEEE_FLOAT));
+ VT.getVectorElementType().getSizeInBits(), 0, FpSem);
} else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
// Aggregates are no different from real scalars as far as GlobalISel is
// concerned.
- init(Info, ElementCount::getFixed(0), VT.getSizeInBits(), 0,
- FP.value_or(LLT::FPVariant::IEEE_FLOAT));
+ init(Info, ElementCount::getFixed(0), VT.getSizeInBits(), 0, FpSem);
} else {
this->Info = Kind::INVALID;
this->RawData = 0;
@@ -81,12 +87,11 @@ void LLT::print(raw_ostream &OS) const {
OS << getElementCount() << " x " << getElementType() << ">";
} else if (isPointer()) {
OS << "p" << getAddressSpace();
- } else if (isBFloat(16)) {
+ } else if (isBFloat16()) {
OS << "bf16";
} else if (isPPCF128()) {
OS << "ppcf128";
- } else if (isFloat()) {
- assert(!isVariantFloat() && "unknown float variant");
+ } else if (isFloatIEEE()) {
OS << "f" << getScalarSizeInBits();
} else if (isInteger()) {
OS << "i" << getScalarSizeInBits();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index d4d1c7f18668e..4f4ef74688a54 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -317,9 +317,9 @@ constexpr LLT V10S16 = LLT::fixed_vector(10, 16);
constexpr LLT V12S16 = LLT::fixed_vector(12, 16);
constexpr LLT V16S16 = LLT::fixed_vector(16, 16);
-constexpr LLT V2F16 =
- LLT::fixed_vector(2, LLT::scalar(16)); // TODO: Expected float16
-constexpr LLT V2BF16 = V2F16; // FIXME
+// TODO: Expected LLT::fixed_vector(2, LLT::float16())
+constexpr LLT V2F16 = LLT::fixed_vector(2, LLT::scalar(16));
+constexpr LLT V2BF16 = V2F16; // FIXME
constexpr LLT V2S32 = LLT::fixed_vector(2, 32);
constexpr LLT V3S32 = LLT::fixed_vector(3, 32);
@@ -3344,7 +3344,7 @@ bool AMDGPULegalizerInfo::legalizeFMad(
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// TODO: Always legal with future ftz flag.
- // TODO: Type is expected to be float32/float16
+ // TODO: Type is expected to be LLT::float32()/LLT::float16()
// FIXME: Do we need just output?
if (Ty == LLT::scalar(32) &&
MFI->getMode().FP32Denormals == DenormalMode::getPreserveSign())
@@ -3895,8 +3895,8 @@ bool AMDGPULegalizerInfo::legalizeFPow(MachineInstr &MI,
Register Src1 = MI.getOperand(2).getReg();
unsigned Flags = MI.getFlags();
LLT Ty = B.getMRI()->getType(Dst);
- const LLT F16 = LLT::scalar(16); // TODO: Expected float16
- const LLT F32 = LLT::scalar(32); // TODO: Expected float32
+ const LLT F16 = LLT::scalar(16); // TODO: Expected LLT::float16()
+ const LLT F32 = LLT::scalar(32); // TODO: Expected LLT::float32()
if (Ty == F32) {
auto Log = B.buildFLog2(F32, Src0, Flags);
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index d889523950a91..e85ec2e990e09 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -114,7 +114,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// EXTENDED-NEXT: const static size_t NumTypeObjects = 3;
// EXTENDED-NEXT: const static LLT TypeObjects[] = {
// EXTENDED-NEXT: LLT::integer(32),
-// EXTENDED-NEXT: LLT::floatingPoint(32, LLT::FPVariant::IEEE_FLOAT),
+// EXTENDED-NEXT: LLT::floatIEEE(32),
// EXTENDED-NEXT: LLT::pointer(0, 32),
// EXTENDED-NEXT: };
diff --git a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
index 079f8dea377e0..ffac39e90bb6a 100644
--- a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
@@ -111,13 +111,13 @@ TEST_F(AArch64IRTranslatorTest, IRTranslateBfloat16) {
llvm::MachineFunctionProperties::Property::FailedISel));
for (auto &MI : MF->front()) {
if (MI.getOpcode() == TargetOpcode::G_LOAD) {
- ASSERT_TRUE(MRI.getType(MI.getOperand(0).getReg()).isBFloat(16));
+ ASSERT_TRUE(MRI.getType(MI.getOperand(0).getReg()).isBFloat16());
}
if (MI.getOpcode() == TargetOpcode::G_FADD ||
MI.getOpcode() == TargetOpcode::G_FMUL) {
for (auto &Op : MI.operands()) {
- ASSERT_TRUE(MRI.getType(Op.getReg()).isBFloat(16));
+ ASSERT_TRUE(MRI.getType(Op.getReg()).isBFloat16());
}
}
}
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 525f222d4ae25..5ef4ac65cde84 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -369,7 +369,7 @@ std::string LLTCodeGen::getCxxEnumValue() const {
void LLTCodeGen::emitCxxEnumValue(raw_ostream &OS) const {
if (Ty.isScalar()) {
- if (Ty.isBFloat(16))
+ if (Ty.isBFloat16())
OS << "GILLT_bf16";
else if (Ty.isPPCF128())
OS << "GILLT_ppcf128";
@@ -388,7 +388,7 @@ void LLTCodeGen::emitCxxEnumValue(raw_ostream &OS) const {
<< Ty.getElementCount().getKnownMinValue();
LLT ElemTy = Ty.getElementType();
- if (ElemTy.isBFloat(16))
+ if (ElemTy.isBFloat16())
OS << "bf16";
else if (ElemTy.isPPCF128())
OS << "ppcf128";
@@ -417,15 +417,14 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
if (Ty.isScalar()) {
if (Ty.isInteger())
OS << "LLT::integer(" << Ty.getScalarSizeInBits() << ")";
- else if (Ty.isBFloat(16))
+ else if (Ty.isBFloat16())
OS << "LLT::bfloat16()";
else if (Ty.isPPCF128())
OS << "LLT::ppcf128()";
else if (Ty.isX86FP80())
OS << "LLT::x86fp80()";
else if (Ty.isFloat())
- OS << "LLT::floatingPoint(" << Ty.getScalarSizeInBits()
- << ", LLT::FPVariant::IEEE_FLOAT)";
+ OS << "LLT::floatIEEE(" << Ty.getScalarSizeInBits() << ")";
else
OS << "LLT::scalar(" << Ty.getScalarSizeInBits() << ")";
return;
@@ -440,15 +439,14 @@ void LLTCodeGen::emitCxxConstructorCall(raw_ostream &OS) const {
LLT ElemTy = Ty.getElementType();
if (ElemTy.isInteger())
OS << "LLT::integer(" << ElemTy.getScalarSizeInBits() << ")";
- else if (ElemTy.isBFloat(16))
+ else if (ElemTy.isBFloat16())
OS << "LLT::bfloat16()";
else if (ElemTy.isPPCF128())
OS << "LLT::ppcf128()";
else if (ElemTy.isX86FP80())
OS << "LLT::x86fp80()";
else if (ElemTy.isFloat())
- OS << "LLT::floatingPoint(" << ElemTy.getScalarSizeInBits()
- << ", LLT::FPVariant::IEEE_FLOAT)";
+ OS << "LLT::floatIEEE(" << ElemTy.getScalarSizeInBits() << ")";
else
OS << "LLT::scalar(" << Ty.getScalarSizeInBits() << ")";
OS << ")";
>From 282bfd7d28882a0717f251bcae98564c55a78aed Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Fri, 28 Nov 2025 00:21:08 +0300
Subject: [PATCH 22/41] Added assert and updated comment
---
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 1456700ce0bb1..64dc0249b88c3 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -365,10 +365,10 @@ class LLT {
/// If this type is a vector, return a vector with the same number of elements
/// but the new element size. Otherwise, return the new element type. Invalid
- /// for pointer types. For pointer types, use changeElementType.
+ /// for pointer and floating point types. For these, use changeElementType.
constexpr LLT changeElementSize(unsigned NewEltSize) const {
assert(!isPointerOrPointerVector() && !(isFloat() || isFloatVector()) &&
- "invalid to directly change element size for pointers");
+ "invalid to directly change element size for pointers and floats");
return isVector()
? LLT::vector(getElementCount(), getElementType().isInteger()
? LLT::integer(NewEltSize)
@@ -392,8 +392,8 @@ class LLT {
/// not attempt to handle cases that aren't evenly divisible.
constexpr LLT divide(int Factor) const {
assert(Factor != 1);
- assert((!isScalar() || getScalarSizeInBits() != 0) &&
- "cannot divide scalar of size zero");
+ assert((!isScalar() || getScalarSizeInBits() != 0) && !isFloat() &&
+ "cannot divide scalar of size zero and floats");
if (isVector()) {
assert(getElementCount().isKnownMultipleOf(Factor));
return scalarOrVector(getElementCount().divideCoefficientBy(Factor),
>From af98f6361af10f2231d079946f6b6d3e87bfd6b9 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sat, 6 Dec 2025 15:00:11 +0300
Subject: [PATCH 23/41] Added global state for LLT, allowing initialize
extended LLTs
---
llvm/include/llvm/CodeGen/LowLevelTypeUtils.h | 5 +-
llvm/include/llvm/CodeGen/TargetLowering.h | 7 ---
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 8 ++-
llvm/lib/CodeGen/Analysis.cpp | 2 +-
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 13 +++--
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 50 ++++++++++---------
llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp | 2 +-
llvm/lib/CodeGen/LowLevelTypeUtils.cpp | 10 ++--
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 +-
llvm/lib/CodeGen/TargetLoweringBase.cpp | 8 ---
llvm/lib/CodeGenTypes/LowLevelType.cpp | 6 ++-
.../AArch64/GISel/AArch64CallLowering.cpp | 4 +-
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 4 +-
.../GlobalISel/GlobalISelMatchTable.cpp | 9 +---
.../GlobalISelMatchTableExecutorEmitter.cpp | 10 ++++
.../GlobalISelMatchTableExecutorEmitter.h | 2 +-
16 files changed, 71 insertions(+), 73 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h b/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
index 4092509948ae6..f0c1758a4c9cc 100644
--- a/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
+++ b/llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
@@ -27,8 +27,7 @@ class Type;
struct fltSemantics;
/// Construct a low-level type based on an LLVM type.
-LLVM_ABI LLT getLLTForType(Type &Ty, const DataLayout &DL,
- bool AllowExtendedLLT = false);
+LLVM_ABI LLT getLLTForType(Type &Ty, const DataLayout &DL);
/// Get a rough equivalent of an MVT for a given LLT. MVT can't distinguish
/// pointers, so these will convert to a plain integer.
@@ -37,7 +36,7 @@ LLVM_ABI EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx);
/// Get a rough equivalent of an LLT for a given MVT. LLT does not yet support
/// scalarable vector types, and will assert if used.
-LLVM_ABI LLT getLLTForMVT(MVT Ty, bool AllowExtendedLLT = false);
+LLVM_ABI LLT getLLTForMVT(MVT Ty);
/// Get the appropriate floating point arithmetic semantic based on the bit size
/// of the given scalar LLT.
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index a5f7bdb037165..b2697c81fd825 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -418,13 +418,6 @@ class LLVM_ABI TargetLoweringBase {
/// amounts, returns MVT::i32.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
- /// Returns LLT for given Type, taking into account
- /// TargetOptions::EnableGlobalISelExtendedLLT.
- LLT getLLTForType(Type &Ty, const DataLayout &DL) const;
- /// Returns LLT for given MVT, taking into account
- /// TargetOptions::EnableGlobalISelExtendedLLT.
- LLT getLLTForMVT(MVT Ty) const;
-
/// Return the preferred type to use for a shift opcode, given the shifted
/// amount type is \p ShiftValueTy.
LLVM_READONLY
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 64dc0249b88c3..fbbb4bd0d1de1 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -230,7 +230,7 @@ class LLT {
init(Info, EC, SizeInBits, AddressSpace, Sem);
}
- LLVM_ABI explicit LLT(MVT VT, bool AllowExtendedLLT = false);
+ LLVM_ABI explicit LLT(MVT VT);
explicit constexpr LLT() : RawData(0), Info(static_cast<Kind>(0)) {}
constexpr bool isToken() const {
@@ -602,6 +602,12 @@ class LLT {
constexpr uint64_t getUniqueRAWLLTData() const {
return ((uint64_t)RawData) | ((uint64_t)Info) << 60;
}
+
+ static bool getUseExtended() { return ExtendedLLT; }
+ static void setUseExtended(bool Enable) { ExtendedLLT = Enable; }
+
+private:
+ static bool ExtendedLLT;
};
inline raw_ostream &operator<<(raw_ostream &OS, const LLT &Ty) {
diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp
index 6d6697167cefa..f16c35ce3f259 100644
--- a/llvm/lib/CodeGen/Analysis.cpp
+++ b/llvm/lib/CodeGen/Analysis.cpp
@@ -176,7 +176,7 @@ void llvm::computeValueLLTs(const TargetLowering &TLI, const DataLayout &DL,
if (Ty.isVoidTy())
return;
// Base case: we can get an LLT for this LLVM IR type.
- ValueTys.push_back(TLI.getLLTForType(Ty, DL));
+ ValueTys.push_back(getLLTForType(Ty, DL));
if (Offsets)
Offsets->push_back(StartingOffset);
}
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index b29695c66020d..c1501b2f428f7 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -159,7 +159,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
if (const Function *F = dyn_cast<Function>(CalleeV)) {
if (F->hasFnAttribute(Attribute::NonLazyBind)) {
- LLT Ty = TLI->getLLTForType(*F->getType(), DL);
+ LLT Ty = getLLTForType(*F->getType(), DL);
Register Reg = MIRBuilder.buildGlobalValue(Ty, F).getReg(0);
Info.Callee = MachineOperand::CreateReg(Reg, false);
} else {
@@ -786,11 +786,11 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
const MVT ValVT = VA.getValVT();
const MVT LocVT = VA.getLocVT();
- const LLT LocTy = TLI->getLLTForMVT(LocVT);
- const LLT ValTy = TLI->getLLTForMVT(ValVT);
+ const LLT LocTy = getLLTForMVT(LocVT);
+ const LLT ValTy = getLLTForMVT(ValVT);
const LLT NewLLT = Handler.isIncomingArgumentHandler() ? LocTy : ValTy;
const EVT OrigVT = EVT::getEVT(Args[i].Ty);
- const LLT OrigTy = TLI->getLLTForType(*Args[i].Ty, DL);
+ const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
const LLT PointerTy = LLT::pointer(
AllocaAddressSpace, DL.getPointerSizeInBits(AllocaAddressSpace));
@@ -1009,7 +1009,7 @@ void CallLowering::insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy,
Align BaseAlign = DL.getPrefTypeAlign(RetTy);
Type *RetPtrTy =
PointerType::get(RetTy->getContext(), DL.getAllocaAddrSpace());
- LLT OffsetLLTy = TLI->getLLTForType(*DL.getIndexType(RetPtrTy), DL);
+ LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetPtrTy), DL);
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
@@ -1040,8 +1040,7 @@ void CallLowering::insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy,
unsigned NumValues = SplitVTs.size();
Align BaseAlign = DL.getPrefTypeAlign(RetTy);
unsigned AS = DL.getAllocaAddrSpace();
- LLT OffsetLLTy =
- TLI->getLLTForType(*DL.getIndexType(RetTy->getContext(), AS), DL);
+ LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetTy->getContext(), AS), DL);
MachinePointerInfo PtrInfo(AS);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index b76ce276fd371..74bc88df79495 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -847,7 +847,7 @@ void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
MIB.setDebugLoc(CurBuilder->getDebugLoc());
Type *PtrIRTy = PointerType::getUnqual(MF->getFunction().getContext());
- const LLT PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
+ const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
auto Table = MIB.buildJumpTable(PtrTy, JT.JTI);
MIB.buildBrJT(Table.getReg(0), JT.JTI, JT.Reg);
@@ -862,7 +862,7 @@ bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
const Value &SValue = *JTH.SValue;
// Subtract the lowest switch case value from the value being switched on.
- const LLT SwitchTy = TLI->getLLTForType(*SValue.getType(), *DL);
+ const LLT SwitchTy = getLLTForType(*SValue.getType(), *DL);
Register SwitchOpReg = getOrCreateVReg(SValue);
auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First);
auto Sub = MIB.buildSub({SwitchTy}, SwitchOpReg, FirstCst);
@@ -1095,7 +1095,7 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
auto RangeSub = MIB.buildSub(SwitchOpTy, SwitchOpReg, MinValReg);
Type *PtrIRTy = PointerType::getUnqual(MF->getFunction().getContext());
- const LLT PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
+ const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
LLT MaskTy = SwitchOpTy;
if (MaskTy.getSizeInBits() > PtrTy.getSizeInBits() ||
@@ -1148,7 +1148,7 @@ void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB,
MachineIRBuilder &MIB = *CurBuilder;
MIB.setMBB(*SwitchBB);
- LLT SwitchTy = TLI->getLLTForMVT(BB.RegVT);
+ LLT SwitchTy = getLLTForMVT(BB.RegVT);
Register Cmp;
unsigned PopCount = llvm::popcount(B.Mask);
if (PopCount == 1) {
@@ -1375,7 +1375,7 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
const Value *Ptr = LI.getPointerOperand();
Type *OffsetIRTy = DL->getIndexType(Ptr->getType());
- LLT OffsetTy = TLI->getLLTForType(*OffsetIRTy, *DL);
+ LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
if (CLI->supportSwiftError() && isSwiftError(Ptr)) {
assert(Regs.size() == 1 && "swifterror should be single pointer");
@@ -1422,7 +1422,7 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
Register Base = getOrCreateVReg(*SI.getPointerOperand());
Type *OffsetIRTy = DL->getIndexType(SI.getPointerOperandType());
- LLT OffsetTy = TLI->getLLTForType(*OffsetIRTy, *DL);
+ LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
if (CLI->supportSwiftError() && isSwiftError(SI.getPointerOperand())) {
assert(Vals.size() == 1 && "swifterror should be single pointer");
@@ -1544,8 +1544,8 @@ bool IRTranslator::translateCopy(const User &U, const Value &V,
bool IRTranslator::translateBitCast(const User &U,
MachineIRBuilder &MIRBuilder) {
// If we're bitcasting to the source type, we can reuse the source vreg.
- if (TLI->getLLTForType(*U.getOperand(0)->getType(), *DL) ==
- TLI->getLLTForType(*U.getType(), *DL)) {
+ if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
+ getLLTForType(*U.getType(), *DL)) {
// If the source is a ConstantInt then it was probably created by
// ConstantHoisting and we should leave it alone.
if (isa<ConstantInt>(U.getOperand(0)))
@@ -1577,9 +1577,9 @@ bool IRTranslator::translateGetElementPtr(const User &U,
Value &Op0 = *U.getOperand(0);
Register BaseReg = getOrCreateVReg(Op0);
Type *PtrIRTy = Op0.getType();
- LLT PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
+ LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
Type *OffsetIRTy = DL->getIndexType(PtrIRTy);
- LLT OffsetTy = TLI->getLLTForType(*OffsetIRTy, *DL);
+ LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
uint32_t PtrAddFlags = 0;
// Each PtrAdd generated to implement the GEP inherits its nuw, nusw, inbounds
@@ -1616,9 +1616,9 @@ bool IRTranslator::translateGetElementPtr(const User &U,
BaseReg)
.getReg(0);
PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth);
- PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
+ PtrTy = getLLTForType(*PtrIRTy, *DL);
OffsetIRTy = DL->getIndexType(PtrIRTy);
- OffsetTy = TLI->getLLTForType(*OffsetIRTy, *DL);
+ OffsetTy = getLLTForType(*OffsetIRTy, *DL);
}
int64_t Offset = 0;
@@ -1668,7 +1668,7 @@ bool IRTranslator::translateGetElementPtr(const User &U,
Register GepOffsetReg;
if (ElementSize != 1) {
auto ElementSizeMIB = MIRBuilder.buildConstant(
- TLI->getLLTForType(*OffsetIRTy, *DL), ElementSize);
+ getLLTForType(*OffsetIRTy, *DL), ElementSize);
// The multiplication is NUW if the GEP is NUW and NSW if the GEP is
// NUSW.
@@ -2329,7 +2329,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
MIRBuilder.buildFMA(Dst, Op0, Op1, Op2,
MachineInstr::copyFlagsFromInstruction(CI));
} else {
- LLT Ty = TLI->getLLTForType(*CI.getType(), *DL);
+ LLT Ty = getLLTForType(*CI.getType(), *DL);
auto FMul = MIRBuilder.buildFMul(
Ty, Op0, Op1, MachineInstr::copyFlagsFromInstruction(CI));
MIRBuilder.buildFAdd(Dst, FMul, Op2,
@@ -2403,7 +2403,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
getStackGuard(getOrCreateVReg(CI), MIRBuilder);
return true;
case Intrinsic::stackprotector: {
- LLT PtrTy = TLI->getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
+ LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
Register GuardVal;
if (TLI->useLoadStackGuardNode(*CI.getModule())) {
GuardVal = MRI->createGenericVirtualRegister(PtrTy);
@@ -2653,7 +2653,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::vector_deinterleave2: {
// Both intrinsics have at least one operand.
Value *Op0 = CI.getOperand(0);
- LLT ResTy = TLI->getLLTForType(*Op0->getType(), MIRBuilder.getDataLayout());
+ LLT ResTy = getLLTForType(*Op0->getType(), MIRBuilder.getDataLayout());
if (!ResTy.isFixedVector())
return false;
@@ -2710,7 +2710,7 @@ bool IRTranslator::translateCallBase(const CallBase &CB,
for (const auto &Arg : CB.args()) {
if (CLI->supportSwiftError() && isSwiftError(Arg)) {
assert(SwiftInVReg == 0 && "Expected only one swift error argument");
- LLT Ty = TLI->getLLTForType(*Arg->getType(), *DL);
+ LLT Ty = getLLTForType(*Arg->getType(), *DL);
SwiftInVReg = MRI->createGenericVirtualRegister(Ty);
MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt(
&CB, &MIRBuilder.getMBB(), Arg));
@@ -2877,7 +2877,7 @@ bool IRTranslator::translateIntrinsic(
TgtMemIntrinsicInfo->memVT.getTypeForEVT(F->getContext())));
LLT MemTy =
TgtMemIntrinsicInfo->memVT.isSimple()
- ? TLI->getLLTForMVT(TgtMemIntrinsicInfo->memVT.getSimpleVT())
+ ? getLLTForMVT(TgtMemIntrinsicInfo->memVT.getSimpleVT())
: LLT::scalar(TgtMemIntrinsicInfo->memVT.getStoreSizeInBits());
// TODO: We currently just fallback to address space 0 if getTgtMemIntrinsic
@@ -3091,13 +3091,13 @@ bool IRTranslator::translateLandingPad(const User &U,
if (auto *RegMask = TRI.getCustomEHPadPreservedMask(*MF))
MF->getRegInfo().addPhysRegsUsedFromRegMask(RegMask);
- LLT Ty = TLI->getLLTForType(*LP.getType(), *DL);
+ LLT Ty = getLLTForType(*LP.getType(), *DL);
Register Undef = MRI->createGenericVirtualRegister(Ty);
MIRBuilder.buildUndef(Undef);
SmallVector<LLT, 2> Tys;
for (Type *Ty : cast<StructType>(LP.getType())->elements())
- Tys.push_back(TLI->getLLTForType(*Ty, *DL));
+ Tys.push_back(getLLTForType(*Ty, *DL));
assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
// Mark exception register as live in.
@@ -3142,7 +3142,7 @@ bool IRTranslator::translateAlloca(const User &U,
// Now we're in the harder dynamic case.
Register NumElts = getOrCreateVReg(*AI.getArraySize());
Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
- LLT IntPtrTy = TLI->getLLTForType(*IntPtrIRTy, *DL);
+ LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
if (MRI->getType(NumElts) != IntPtrTy) {
Register ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
@@ -3949,8 +3949,8 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
CurBuilder->setInsertPt(*ParentBB, ParentBB->end());
// First create the loads to the guard/stack slot for the comparison.
Type *PtrIRTy = PointerType::getUnqual(MF->getFunction().getContext());
- const LLT PtrTy = TLI->getLLTForType(*PtrIRTy, *DL);
- LLT PtrMemTy = TLI->getLLTForMVT(TLI->getPointerMemTy(*DL));
+ const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
+ LLT PtrMemTy = getLLTForMVT(TLI->getPointerMemTy(*DL));
MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
int FI = MFI.getStackProtectorIndex();
@@ -4153,6 +4153,10 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
return false;
}
+ // Enable globally extended LLT types.
+ if (TM.Options.EnableGlobalISelExtendedLLT)
+ LLT::setUseExtended(true);
+
// Release the per-function state when we return, whether we succeeded or not.
auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
diff --git a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
index cade075b702f4..cdc1f64dc439f 100644
--- a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
@@ -952,7 +952,7 @@ void LoadStoreOpt::initializeStoreMergeTargetInfo(unsigned AddrSpace) {
const auto &LI = *MF->getSubtarget().getLegalizerInfo();
const auto &DL = MF->getFunction().getDataLayout();
Type *IRPtrTy = PointerType::get(MF->getFunction().getContext(), AddrSpace);
- LLT PtrTy = TLI->getLLTForType(*IRPtrTy, DL);
+ LLT PtrTy = getLLTForType(*IRPtrTy, DL);
// We assume that we're not going to be generating any stores wider than
// MaxStoreSizeToForm bits for now.
for (unsigned Size = 2; Size <= MaxStoreSizeToForm; Size *= 2) {
diff --git a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
index b3f397610c71c..1ebf2e62f3242 100644
--- a/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
+++ b/llvm/lib/CodeGen/LowLevelTypeUtils.cpp
@@ -17,10 +17,10 @@
#include "llvm/IR/DerivedTypes.h"
using namespace llvm;
-LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL, bool AllowExtendedLLT) {
+LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) {
if (auto *VTy = dyn_cast<VectorType>(&Ty)) {
auto EC = VTy->getElementCount();
- LLT ScalarTy = getLLTForType(*VTy->getElementType(), DL, AllowExtendedLLT);
+ LLT ScalarTy = getLLTForType(*VTy->getElementType(), DL);
if (EC.isScalar())
return ScalarTy;
return LLT::vector(EC, ScalarTy);
@@ -38,7 +38,7 @@ LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL, bool AllowExtendedLLT) {
assert(SizeInBits != 0 && "invalid zero-sized type");
// Return simple scalar
- if (!AllowExtendedLLT)
+ if (!LLT::getUseExtended())
return LLT::scalar(SizeInBits);
// Choose more precise LLT variant
@@ -109,9 +109,7 @@ EVT llvm::getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx) {
return EVT::getIntegerVT(Ctx, Ty.getSizeInBits());
}
-LLT llvm::getLLTForMVT(MVT VT, bool AllowExtendedLLT) {
- return LLT(VT, AllowExtendedLLT);
-}
+LLT llvm::getLLTForMVT(MVT VT) { return LLT(VT); }
const llvm::fltSemantics &llvm::getFltSemanticForLLT(LLT Ty) {
assert((Ty.isAnyScalar() || Ty.isFloat()) &&
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 2abed21acdab3..dd8f18d3b8a6a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2482,7 +2482,7 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
const MDString *RegStr = cast<MDString>(MD->getMD()->getOperand(0));
EVT VT = Op->getValueType(0);
- LLT Ty = VT.isSimple() ? TLI->getLLTForMVT(VT.getSimpleVT()) : LLT();
+ LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
const MachineFunction &MF = CurDAG->getMachineFunction();
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
@@ -2513,7 +2513,7 @@ void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
const MDString *RegStr = cast<MDString>(MD->getMD()->getOperand(0));
EVT VT = Op->getOperand(2).getValueType();
- LLT Ty = VT.isSimple() ? TLI->getLLTForMVT(VT.getSimpleVT()) : LLT();
+ LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
const MachineFunction &MF = CurDAG->getMachineFunction();
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 968e8a88e9dfa..1d674b283db15 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1051,14 +1051,6 @@ EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
return ShiftVT;
}
-LLT TargetLoweringBase::getLLTForType(Type &Ty, const DataLayout &DL) const {
- return llvm::getLLTForType(Ty, DL, TM.Options.EnableGlobalISelExtendedLLT);
-}
-
-LLT TargetLoweringBase::getLLTForMVT(MVT Ty) const {
- return llvm::getLLTForMVT(Ty, TM.Options.EnableGlobalISelExtendedLLT);
-}
-
bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
assert(isTypeLegal(VT));
switch (Op) {
diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index 229c9d542fe9e..9418d54058c4b 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -16,6 +16,8 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+bool LLT::ExtendedLLT = false;
+
// Repeat logic of MVT::getFltSemantics to exclude CodeGen dependency
static LLT::FpSemantics getFpSemanticsForMVT(MVT VT) {
switch (VT.getScalarType().SimpleTy) {
@@ -38,8 +40,8 @@ static LLT::FpSemantics getFpSemanticsForMVT(MVT VT) {
}
}
-LLT::LLT(MVT VT, bool AllowExtendedLLT) {
- if (!AllowExtendedLLT) {
+LLT::LLT(MVT VT) {
+ if (!ExtendedLLT) {
if (VT.isVector()) {
bool AsVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector();
Kind Info = AsVector ? Kind::VECTOR_ANY : Kind::ANY_SCALAR;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 0d5379b61e954..7907a3c283624 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -457,7 +457,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
ExtendOp = TargetOpcode::G_ZEXT;
LLT NewLLT(NewVT);
- LLT OldLLT = TLI.getLLTForType(*CurArgInfo.Ty, DL);
+ LLT OldLLT = getLLTForType(*CurArgInfo.Ty, DL);
CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
// Instead of an extend, we might have a vector type which needs
// padding with more elements, e.g. <2 x half> -> <4 x half>.
@@ -1397,7 +1397,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// is set.
if (Info.Callee.isSymbol() && F.getParent()->getRtLibUseGOT()) {
auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_GLOBAL_VALUE);
- DstOp(TLI.getLLTForType(*F.getType(), DL)).addDefToMIB(MRI, MIB);
+ DstOp(getLLTForType(*F.getType(), DL)).addDefToMIB(MRI, MIB);
MIB.addExternalSymbol(Info.Callee.getSymbolName(), AArch64II::MO_GOT);
Info.Callee = MachineOperand::CreateReg(MIB.getReg(0), false);
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index c39d7f7a55f34..78d6a21808ee9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -332,7 +332,7 @@ bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
extOpcodeToISDExtOpcode(ExtendOp));
if (ExtVT != VT) {
RetInfo.Ty = ExtVT.getTypeForEVT(Ctx);
- LLT ExtTy = TLI.getLLTForType(*RetInfo.Ty, DL);
+ LLT ExtTy = getLLTForType(*RetInfo.Ty, DL);
Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0);
}
}
@@ -428,7 +428,7 @@ void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg,
Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy);
lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]);
- LLT ArgTy = TLI.getLLTForType(*SplitArg.Ty, DL);
+ LLT ArgTy = getLLTForType(*SplitArg.Ty, DL);
if (SplitArg.Flags[0].isPointer()) {
// Compensate for losing pointeriness in splitValueTypes.
LLT PtrTy = LLT::pointer(SplitArg.Flags[0].getPointerAddrSpace(),
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 308db1f2ca205..9f7069e04f85a 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -24,11 +24,6 @@ STATISTIC(NumPatternEmitted, "Number of patterns emitted");
using namespace llvm;
using namespace gi;
-static cl::opt<bool>
- AllowExtendedLLT("gisel-extended-llt",
- cl::desc("Generate extended llt names in match tables"),
- cl::init(false));
-
// FIXME: Use createStringError instead.
static Error failUnsupported(const Twine &Reason) {
return make_error<StringError>(Reason, inconvertibleErrorCode());
@@ -473,10 +468,10 @@ bool LLTCodeGen::operator<(const LLTCodeGen &Other) const {
std::optional<LLTCodeGen> llvm::gi::MVTToLLT(MVT VT) {
if (VT.isVector() && !VT.getVectorElementCount().isScalar())
- return LLTCodeGen(LLT(VT, AllowExtendedLLT));
+ return LLTCodeGen(LLT(VT));
if (VT.isInteger() || VT.isFloatingPoint())
- return LLTCodeGen(LLT(VT, AllowExtendedLLT));
+ return LLTCodeGen(LLT(VT));
return std::nullopt;
}
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp
index 333d956a4ff3b..27dc02ccb1646 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp
@@ -8,10 +8,20 @@
#include "GlobalISelMatchTableExecutorEmitter.h"
#include "GlobalISelMatchTable.h"
+#include "llvm/Support/CommandLine.h"
using namespace llvm;
using namespace llvm::gi;
+static cl::opt<bool>
+ AllowExtendedLLT("gisel-extended-llt",
+ cl::desc("Generate extended llt names in match tables"),
+ cl::init(false));
+
+GlobalISelMatchTableExecutorEmitter::GlobalISelMatchTableExecutorEmitter() {
+ LLT::setUseExtended(AllowExtendedLLT);
+}
+
void GlobalISelMatchTableExecutorEmitter::emitSubtargetFeatureBitsetImpl(
raw_ostream &OS, ArrayRef<RuleMatcher> Rules) {
SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(SubtargetFeatures,
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h
index 1f66d73f77576..c56e0549f1ec6 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h
@@ -188,7 +188,7 @@ class GlobalISelMatchTableExecutorEmitter {
Comment);
}
- GlobalISelMatchTableExecutorEmitter() = default;
+ GlobalISelMatchTableExecutorEmitter();
public:
virtual ~GlobalISelMatchTableExecutorEmitter() = default;
>From 899e79e58c29d3227790f37d299f3b4987862b21 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sat, 6 Dec 2025 15:05:28 +0300
Subject: [PATCH 24/41] Remove TargetOption::EnableGlobalISelExtendedLLT.
Targets must use LLT::setUseExtended instead.
---
llvm/include/llvm/Target/TargetMachine.h | 3 ---
llvm/include/llvm/Target/TargetOptions.h | 7 +------
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 12 ++++--------
3 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index 9099683967398..d0fd483a8ddaa 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -295,9 +295,6 @@ class LLVM_ABI TargetMachine {
bool getO0WantsFastISel() { return O0WantsFastISel; }
void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; }
void setGlobalISel(bool Enable) { Options.EnableGlobalISel = Enable; }
- void setGlobalISelExtendedLLT(bool Enable) {
- Options.EnableGlobalISelExtendedLLT = Enable;
- }
void setGlobalISelAbort(GlobalISelAbortMode Mode) {
Options.GlobalISelAbort = Mode;
}
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index 123bb94a53dc4..0312515d11798 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -123,8 +123,7 @@ class TargetOptions {
NoSignedZerosFPMath(false), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
- EnableFastISel(false), EnableGlobalISel(false),
- EnableGlobalISelExtendedLLT(false), UseInitArray(false),
+ EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
DisableIntegratedAS(false), FunctionSections(false),
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
@@ -223,10 +222,6 @@ class TargetOptions {
/// EnableGlobalISel - This flag enables global instruction selection.
unsigned EnableGlobalISel : 1;
- /// EnableGlobalISelExtendedLLT - This flag enables LLTs with extended type
- /// info so target may distinguish different formats of equal sized scalars.
- unsigned EnableGlobalISelExtendedLLT : 1;
-
/// EnableGlobalISelAbort - Control abort behaviour when global instruction
/// selection fails to lower/select an instruction.
GlobalISelAbortMode GlobalISelAbort = GlobalISelAbortMode::Enable;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 74bc88df79495..c7151dc2a3190 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3814,12 +3814,12 @@ bool IRTranslator::translate(const Constant &C, Register Reg) {
bool IRTranslator::mayTranslateUserTypes(const User &U) const {
const TargetMachine &TM = TLI->getTargetMachine();
- if (TLI->getTargetMachine().Options.EnableGlobalISelExtendedLLT)
+ if (LLT::getUseExtended())
return true;
- // BF16 cannot currently be represented by default LLT, to avoid miscompiles
- // we prevent any instructions using them in targets with disabled
- // TargetOptions::EnableGlobalISelExtendedLLT.
+ // BF16 cannot currently be represented by default LLT. To avoid miscompiles
+ // we prevent any instructions using them by default in all targets that do
+ // not explicitly enable it via LLT::setUseExtended(true).
// SPIRV target is exception.
return TM.getTargetTriple().isSPIRV() ||
(!U.getType()->getScalarType()->isBFloatTy() &&
@@ -4153,10 +4153,6 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
return false;
}
- // Enable globally extended LLT types.
- if (TM.Options.EnableGlobalISelExtendedLLT)
- LLT::setUseExtended(true);
-
// Release the per-function state when we return, whether we succeeded or not.
auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
>From 0fa794a1f5a090b7c32a651812d7088567730c03 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sat, 6 Dec 2025 16:17:11 +0300
Subject: [PATCH 25/41] Fix after merge
---
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +-
llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index fc00ce3aee1a8..2dcff723be3a4 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3057,7 +3057,7 @@ bool IRTranslator::translateInvoke(const User &U,
/// intrinsics such as amdgcn.kill.
bool IRTranslator::translateCallBr(const User &U,
MachineIRBuilder &MIRBuilder) {
- if (containsBF16Type(U))
+ if (!mayTranslateUserTypes(U))
return false; // see translateCall
const CallBrInst &I = cast<CallBrInst>(U);
diff --git a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
index ffac39e90bb6a..2f39416010235 100644
--- a/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
@@ -90,8 +90,8 @@ TEST_F(AArch64IRTranslatorTest, IRTranslateBfloat16) {
M->setDataLayout(TM->createDataLayout());
TM->setGlobalISel(true);
- TM->setGlobalISelExtendedLLT(true);
TM->setGlobalISelAbort(GlobalISelAbortMode::DisableWithDiag);
+ LLT::setUseExtended(true);
legacy::PassManager PM;
TargetPassConfig *TPC(TM->createPassConfig(PM));
@@ -124,7 +124,8 @@ TEST_F(AArch64IRTranslatorTest, IRTranslateBfloat16) {
MMI->deleteMachineFunctionFor(*F);
// Run again without extended LLT
- TM->setGlobalISelExtendedLLT(false);
+ LLT::setUseExtended(false);
+
PM.run(*M);
MF = MMI->getMachineFunction(*F);
ASSERT_TRUE(MF->getProperties().hasProperty(
>From 97c78325010dd46f9dde1d8c9c9758dc174c38df Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Sun, 21 Dec 2025 21:42:57 +0300
Subject: [PATCH 26/41] review fixes
---
llvm/include/llvm/CodeGen/Analysis.h | 2 +-
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 146 +++++++++++-------
llvm/lib/CodeGen/Analysis.cpp | 8 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 4 +-
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 12 +-
llvm/lib/CodeGenTypes/LowLevelType.cpp | 30 ++--
6 files changed, 120 insertions(+), 82 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/Analysis.h b/llvm/include/llvm/CodeGen/Analysis.h
index b60029d1d7398..2f1364d199710 100644
--- a/llvm/include/llvm/CodeGen/Analysis.h
+++ b/llvm/include/llvm/CodeGen/Analysis.h
@@ -87,7 +87,7 @@ void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty,
/// If Offsets is non-null, it points to a vector to be filled in
/// with the in-memory offsets of each of the individual values.
///
-void computeValueLLTs(const TargetLowering &TLI, const DataLayout &DL, Type &Ty,
+void computeValueLLTs(const DataLayout &DL, Type &Ty,
SmallVectorImpl<LLT> &ValueTys,
SmallVectorImpl<uint64_t> *Offsets = nullptr,
uint64_t StartingOffset = 0);
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index fbbb4bd0d1de1..33cb4d0b5e771 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -9,17 +9,19 @@
/// Implement a low-level type suitable for MachineInstr level instruction
/// selection.
///
-/// For a type attached to a MachineInstr, we only care about 2 details: total
-/// size and the number of vector lanes (if any). Accordingly, there are 4
-/// possible valid type-kinds:
+/// For a type attached to a MachineInstr, we care about total
+/// size, the number of vector lanes (if any)
+/// and the kind of the type (anyscalar, integer, float and etc).
+/// Floating point are filled with APFloat::Semantics to make them
+/// distinguishable.
///
-/// * `sN` for scalars and aggregates
-/// * `<N x sM>` for vectors, which must have at least 2 elements.
-/// * `pN` for pointers
+/// Earlier other information required for correct selection was expected to be
+/// carried only by the opcode, or non-type flags. For example the distinction
+/// between G_ADD and G_FADD for int/float or fast-math flags.
///
-/// Other information required for correct selection is expected to be carried
-/// by the opcode, or non-type flags. For example the distinction between G_ADD
-/// and G_FADD for int/float or fast-math flags.
+/// Now we also able to rely on the kind of the type.
+/// This may be useful to distinguish different types of the same size used at
+/// the same opcode, for example, G_FADD with half vs G_FADD with bfloat16.
///
//===----------------------------------------------------------------------===//
@@ -84,40 +86,35 @@ class LLT {
/// Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT scalar(unsigned SizeInBits) {
- return LLT{Kind::ANY_SCALAR, ElementCount::getFixed(0), SizeInBits,
- /*AddressSpace=*/0, static_cast<FpSemantics>(0)};
+ return LLT{Kind::ANY_SCALAR, ElementCount::getFixed(0), SizeInBits};
}
static constexpr LLT integer(unsigned SizeInBits) {
- return LLT{Kind::INTEGER, ElementCount::getFixed(0), SizeInBits,
- /*AddressSpace=*/0, static_cast<FpSemantics>(0)};
+ return LLT{Kind::INTEGER, ElementCount::getFixed(0), SizeInBits};
}
static LLT floatingPoint(const FpSemantics &Sem) {
return LLT{Kind::FLOAT, ElementCount::getFixed(0),
- APFloat::getSizeInBits(APFloatBase::EnumToSemantics(Sem)),
- /*AddressSpace=*/0, Sem};
+ APFloat::getSizeInBits(APFloatBase::EnumToSemantics(Sem)), Sem};
}
/// Get a low-level token; just a scalar with zero bits (or no size).
static constexpr LLT token() {
return LLT{Kind::ANY_SCALAR, ElementCount::getFixed(0),
- /*SizeInBits=*/0,
- /*AddressSpace=*/0, static_cast<FpSemantics>(0)};
+ /*SizeInBits=*/0};
}
/// Get a low-level pointer in the given address space.
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits) {
assert(SizeInBits > 0 && "invalid pointer size");
return LLT{Kind::POINTER, ElementCount::getFixed(0), SizeInBits,
- AddressSpace, static_cast<FpSemantics>(0)};
+ AddressSpace};
}
/// Get a low-level vector of some number of elements and element width.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits) {
assert(!EC.isScalar() && "invalid number of vector elements");
- return LLT{Kind::VECTOR_ANY, EC, ScalarSizeInBits,
- /*AddressSpace=*/0, static_cast<FpSemantics>(0)};
+ return LLT{Kind::VECTOR_ANY, EC, ScalarSizeInBits};
}
/// Get a low-level vector of some number of elements and element type.
@@ -126,10 +123,14 @@ class LLT {
assert(!ScalarTy.isVector() && "invalid vector element type");
Kind Info = toVector(ScalarTy.Info);
- return LLT{Info, EC, ScalarTy.getSizeInBits().getFixedValue(),
- ScalarTy.isPointer() ? ScalarTy.getAddressSpace() : 0,
- ScalarTy.isFloat() ? ScalarTy.getFpSemantics()
- : static_cast<FpSemantics>(0)};
+ if (ScalarTy.isPointer())
+ return LLT{Info, EC, ScalarTy.getSizeInBits().getFixedValue(),
+ ScalarTy.getAddressSpace()};
+ if (ScalarTy.isFloat())
+ return LLT{Info, EC, ScalarTy.getSizeInBits().getFixedValue(),
+ ScalarTy.getFpSemantics()};
+
+ return LLT{Info, EC, ScalarTy.getSizeInBits().getFixedValue()};
}
static constexpr LLT floatIEEE(unsigned SizeInBits) {
@@ -149,40 +150,40 @@ class LLT {
// Get a bfloat16 value.
static constexpr LLT bfloat16() {
- return LLT{Kind::FLOAT, ElementCount::getFixed(0), 16, 0,
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 16,
FpSemantics::S_BFloat};
}
/// Get a 16-bit IEEE half value.
static constexpr LLT float16() {
- return LLT{Kind::FLOAT, ElementCount::getFixed(0), 16, 0,
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 16,
FpSemantics::S_IEEEhalf};
}
/// Get a 32-bit IEEE float value.
static constexpr LLT float32() {
- return LLT{Kind::FLOAT, ElementCount::getFixed(0), 32, 0,
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 32,
FpSemantics::S_IEEEsingle};
}
/// Get a 64-bit IEEE double value.
static constexpr LLT float64() {
- return LLT{Kind::FLOAT, ElementCount::getFixed(0), 64, 0,
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 64,
FpSemantics::S_IEEEdouble};
}
/// Get a 80-bit X86 floating point value.
static constexpr LLT x86fp80() {
- return LLT{Kind::FLOAT, ElementCount::getFixed(0), 80, 0,
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 80,
FpSemantics::S_x87DoubleExtended};
}
/// Get a 128-bit IEEE quad value.
static constexpr LLT float128() {
- return LLT{Kind::FLOAT, ElementCount::getFixed(0), 128, 0,
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 128,
FpSemantics::S_IEEEquad};
}
/// Get a 128-bit PowerPC double double value.
static constexpr LLT ppcf128() {
- return LLT{Kind::FLOAT, ElementCount::getFixed(0), 128, 0,
+ return LLT{Kind::FLOAT, ElementCount::getFixed(0), 128,
FpSemantics::S_PPCDoubleDouble};
}
@@ -224,10 +225,21 @@ class LLT {
return scalarOrVector(EC, LLT::scalar(static_cast<unsigned>(ScalarSize)));
}
+ explicit constexpr LLT(Kind Info, ElementCount EC, uint64_t SizeInBits)
+ : LLT() {
+ init(Info, EC, SizeInBits);
+ }
+
+ explicit constexpr LLT(Kind Info, ElementCount EC, uint64_t SizeInBits,
+ unsigned AddressSpace)
+ : LLT() {
+ init(Info, EC, SizeInBits, AddressSpace);
+ }
+
explicit constexpr LLT(Kind Info, ElementCount EC, uint64_t SizeInBits,
- unsigned AddressSpace, FpSemantics Sem)
+ FpSemantics Sem)
: LLT() {
- init(Info, EC, SizeInBits, AddressSpace, Sem);
+ init(Info, EC, SizeInBits, Sem);
}
LLVM_ABI explicit LLT(MVT VT);
@@ -241,7 +253,7 @@ class LLT {
constexpr bool isInteger() const { return Info == Kind::INTEGER; }
constexpr bool isFloat() const { return Info == Kind::FLOAT; }
constexpr bool isPointer() const { return Info == Kind::POINTER; }
- constexpr bool isVectorAny() const { return Info == Kind::VECTOR_ANY; }
+ constexpr bool isAnyVector() const { return Info == Kind::VECTOR_ANY; }
constexpr bool isIntegerVector() const {
return Info == Kind::VECTOR_INTEGER;
}
@@ -272,23 +284,21 @@ class LLT {
constexpr bool isFloat(unsigned Size) const {
return isFloat() && getScalarSizeInBits() == Size;
}
- constexpr bool isFloatWithSem(FpSemantics Sem) const {
+ constexpr bool isFloat(FpSemantics Sem) const {
return isFloat() && getFpSemantics() == Sem;
}
constexpr bool isFloatIEEE() const {
- return isFloatWithSem(APFloatBase::S_IEEEhalf) ||
- isFloatWithSem(APFloatBase::S_IEEEsingle) ||
- isFloatWithSem(APFloatBase::S_IEEEdouble) ||
- isFloatWithSem(APFloatBase::S_IEEEquad);
- }
- constexpr bool isBFloat16() const {
- return isFloatWithSem(FpSemantics::S_BFloat);
+ return isFloat(APFloatBase::S_IEEEhalf) ||
+ isFloat(APFloatBase::S_IEEEsingle) ||
+ isFloat(APFloatBase::S_IEEEdouble) ||
+ isFloat(APFloatBase::S_IEEEquad);
}
+ constexpr bool isBFloat16() const { return isFloat(FpSemantics::S_BFloat); }
constexpr bool isX86FP80() const {
- return isFloatWithSem(FpSemantics::S_x87DoubleExtended);
+ return isFloat(FpSemantics::S_x87DoubleExtended);
}
constexpr bool isPPCF128() const {
- return isFloatWithSem(FpSemantics::S_PPCDoubleDouble);
+ return isFloat(FpSemantics::S_PPCDoubleDouble);
}
/// Returns the number of elements in a vector LLT. Must only be called on
@@ -578,21 +588,51 @@ class LLT {
return getMask(FieldInfo) & (RawData >> FieldInfo[1]);
}
- constexpr void init(Kind Info, ElementCount EC, uint64_t SizeInBits,
- unsigned AddressSpace, FpSemantics Sem) {
+ // Init for scalar and integer single or vector types
+ constexpr void init(Kind Info, ElementCount EC, uint64_t SizeInBits) {
assert(SizeInBits <= std::numeric_limits<unsigned>::max() &&
"Not enough bits in LLT to represent size");
+ assert((Info == Kind::ANY_SCALAR || Info == Kind::INTEGER ||
+ Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER) &&
+ "Called initializer for wrong LLT Kind");
this->Info = Info;
- if (Info == Kind::POINTER || Info == Kind::VECTOR_POINTER) {
- RawData = maskAndShift(SizeInBits, PointerSizeFieldInfo) |
- maskAndShift(AddressSpace, PointerAddressSpaceFieldInfo);
- } else {
+ RawData = maskAndShift(SizeInBits, ScalarSizeFieldInfo);
+
+ if (Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER) {
RawData = maskAndShift(SizeInBits, ScalarSizeFieldInfo) |
- maskAndShift((uint64_t)Sem, FpSemanticFieldInfo);
+ maskAndShift(EC.getKnownMinValue(), VectorElementsFieldInfo) |
+ maskAndShift(EC.isScalable() ? 1 : 0, VectorScalableFieldInfo);
}
+ }
+
+ // Init pointer or pointer vector
+ constexpr void init(Kind Info, ElementCount EC, uint64_t SizeInBits,
+ unsigned AddressSpace) {
+ assert(SizeInBits <= std::numeric_limits<unsigned>::max() &&
+ "Not enough bits in LLT to represent size");
+ assert((Info == Kind::POINTER || Info == Kind::VECTOR_POINTER) &&
+ "Called initializer for wrong LLT Kind");
+ this->Info = Info;
+ RawData = maskAndShift(SizeInBits, PointerSizeFieldInfo) |
+ maskAndShift(AddressSpace, PointerAddressSpaceFieldInfo);
+
+ if (Info == Kind::VECTOR_POINTER) {
+ RawData |= maskAndShift(EC.getKnownMinValue(), VectorElementsFieldInfo) |
+ maskAndShift(EC.isScalable() ? 1 : 0, VectorScalableFieldInfo);
+ }
+ }
+
+ constexpr void init(Kind Info, ElementCount EC, uint64_t SizeInBits,
+ FpSemantics Sem) {
+ assert(SizeInBits <= std::numeric_limits<unsigned>::max() &&
+ "Not enough bits in LLT to represent size");
+ assert((Info == Kind::FLOAT || Info == Kind::VECTOR_FLOAT) &&
+ "Called initializer for wrong LLT Kind");
+ this->Info = Info;
+ RawData = maskAndShift(SizeInBits, ScalarSizeFieldInfo) |
+ maskAndShift((uint64_t)Sem, FpSemanticFieldInfo);
- if (Info == Kind::VECTOR_ANY || Info == Kind::VECTOR_INTEGER ||
- Info == Kind::VECTOR_FLOAT || Info == Kind::VECTOR_POINTER) {
+ if (Info == Kind::VECTOR_FLOAT) {
RawData |= maskAndShift(EC.getKnownMinValue(), VectorElementsFieldInfo) |
maskAndShift(EC.isScalable() ? 1 : 0, VectorScalableFieldInfo);
}
diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp
index f16c35ce3f259..f5fbfb7e5e21d 100644
--- a/llvm/lib/CodeGen/Analysis.cpp
+++ b/llvm/lib/CodeGen/Analysis.cpp
@@ -146,8 +146,8 @@ void llvm::ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL,
}
}
-void llvm::computeValueLLTs(const TargetLowering &TLI, const DataLayout &DL,
- Type &Ty, SmallVectorImpl<LLT> &ValueTys,
+void llvm::computeValueLLTs(const DataLayout &DL, Type &Ty,
+ SmallVectorImpl<LLT> &ValueTys,
SmallVectorImpl<uint64_t> *Offsets,
uint64_t StartingOffset) {
// Given a struct type, recursively traverse the elements.
@@ -158,7 +158,7 @@ void llvm::computeValueLLTs(const TargetLowering &TLI, const DataLayout &DL,
const StructLayout *SL = Offsets ? DL.getStructLayout(STy) : nullptr;
for (unsigned I = 0, E = STy->getNumElements(); I != E; ++I) {
uint64_t EltOffset = SL ? SL->getElementOffset(I) : 0;
- computeValueLLTs(TLI, DL, *STy->getElementType(I), ValueTys, Offsets,
+ computeValueLLTs(DL, *STy->getElementType(I), ValueTys, Offsets,
StartingOffset + EltOffset);
}
return;
@@ -168,7 +168,7 @@ void llvm::computeValueLLTs(const TargetLowering &TLI, const DataLayout &DL,
Type *EltTy = ATy->getElementType();
uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue();
for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
- computeValueLLTs(TLI, DL, *EltTy, ValueTys, Offsets,
+ computeValueLLTs(DL, *EltTy, ValueTys, Offsets,
StartingOffset + i * EltSize);
return;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 2dcff723be3a4..23178610c16d1 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -193,7 +193,7 @@ IRTranslator::allocateVRegs(const Value &Val) {
auto *Regs = VMap.getVRegs(Val);
auto *Offsets = VMap.getOffsets(Val);
SmallVector<LLT, 4> SplitTys;
- computeValueLLTs(*TLI, *DL, *Val.getType(), SplitTys,
+ computeValueLLTs(*DL, *Val.getType(), SplitTys,
Offsets->empty() ? Offsets : nullptr);
for (unsigned i = 0; i < SplitTys.size(); ++i)
Regs->push_back(0);
@@ -217,7 +217,7 @@ ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
"Don't know how to create an empty vreg");
SmallVector<LLT, 4> SplitTys;
- computeValueLLTs(*TLI, *DL, *Val.getType(), SplitTys,
+ computeValueLLTs(*DL, *Val.getType(), SplitTys,
Offsets->empty() ? Offsets : nullptr);
if (!isa<Constant>(Val)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 9c35ec552b62c..26de822b4c344 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1952,8 +1952,8 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
"expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
}
- if (Token.range().starts_with("s") || Token.range().starts_with("i")) {
- bool ScalarOrInt = Token.range().starts_with("s");
+ bool Scalar = Token.range().starts_with("s");
+ if (Scalar || Token.range().starts_with("i")) {
auto ScalarSize = APSInt(TypeDigits).getZExtValue();
if (!ScalarSize) {
Ty = LLT::token();
@@ -1964,7 +1964,7 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
if (!verifyScalarSize(ScalarSize))
return error("invalid size for scalar type");
- Ty = ScalarOrInt ? LLT::scalar(ScalarSize) : LLT::integer(ScalarSize);
+ Ty = Scalar ? LLT::scalar(ScalarSize) : LLT::integer(ScalarSize);
lex();
return false;
}
@@ -2042,12 +2042,12 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
return error(
"expected integers after 's'/'i'/'f'/'bf'/'p' type identifier");
- if (Token.range().starts_with("s") || Token.range().starts_with("i")) {
- bool ScalarOrInt = Token.range().starts_with("s");
+ Scalar = Token.range().starts_with("s");
+ if (Scalar || Token.range().starts_with("i")) {
auto ScalarSize = APSInt(VectorTyDigits).getZExtValue();
if (!verifyScalarSize(ScalarSize))
return error("invalid size for scalar element in vector");
- Ty = ScalarOrInt ? LLT::scalar(ScalarSize) : LLT::integer(ScalarSize);
+ Ty = Scalar ? LLT::scalar(ScalarSize) : LLT::integer(ScalarSize);
} else if (Token.range().starts_with("p")) {
const DataLayout &DL = MF.getDataLayout();
uint64_t AS = APSInt(VectorTyDigits).getZExtValue();
diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index 9418d54058c4b..484329e918903 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -18,7 +18,6 @@ using namespace llvm;
bool LLT::ExtendedLLT = false;
-// Repeat logic of MVT::getFltSemantics to exclude CodeGen dependency
static LLT::FpSemantics getFpSemanticsForMVT(MVT VT) {
switch (VT.getScalarType().SimpleTy) {
default:
@@ -46,11 +45,9 @@ LLT::LLT(MVT VT) {
bool AsVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector();
Kind Info = AsVector ? Kind::VECTOR_ANY : Kind::ANY_SCALAR;
init(Info, VT.getVectorElementCount(),
- VT.getVectorElementType().getSizeInBits(), 0,
- static_cast<FpSemantics>(0));
+ VT.getVectorElementType().getSizeInBits());
} else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
- init(Kind::ANY_SCALAR, ElementCount::getFixed(0), VT.getSizeInBits(), 0,
- static_cast<FpSemantics>(0));
+ init(Kind::ANY_SCALAR, ElementCount::getFixed(0), VT.getSizeInBits());
} else {
this->Info = Kind::INVALID;
this->RawData = 0;
@@ -59,23 +56,24 @@ LLT::LLT(MVT VT) {
}
bool IsFloatingPoint = VT.isFloatingPoint();
- FpSemantics FpSem =
- IsFloatingPoint ? getFpSemanticsForMVT(VT) : static_cast<FpSemantics>(0);
bool AsVector = VT.isVector() &&
(VT.getVectorMinNumElements() > 1 || VT.isScalableVector());
- LLT::Kind Info;
- if (IsFloatingPoint)
- Info = AsVector ? LLT::Kind::VECTOR_FLOAT : LLT::Kind::FLOAT;
- else
- Info = AsVector ? LLT::Kind::VECTOR_INTEGER : LLT::Kind::INTEGER;
- if (VT.isVector()) {
- init(Info, VT.getVectorElementCount(),
- VT.getVectorElementType().getSizeInBits(), 0, FpSem);
+ if (AsVector) {
+ if (IsFloatingPoint)
+ init(LLT::Kind::VECTOR_FLOAT, VT.getVectorElementCount(),
+ VT.getVectorElementType().getSizeInBits(), getFpSemanticsForMVT(VT));
+ else
+ init(LLT::Kind::VECTOR_INTEGER, VT.getVectorElementCount(),
+ VT.getVectorElementType().getSizeInBits());
} else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
// Aggregates are no different from real scalars as far as GlobalISel is
// concerned.
- init(Info, ElementCount::getFixed(0), VT.getSizeInBits(), 0, FpSem);
+ if (IsFloatingPoint)
+ init(LLT::Kind::FLOAT, ElementCount::getFixed(0), VT.getSizeInBits(),
+ getFpSemanticsForMVT(VT));
+ else
+ init(LLT::Kind::INTEGER, ElementCount::getFixed(0), VT.getSizeInBits());
} else {
this->Info = Kind::INVALID;
this->RawData = 0;
>From f8cf186806507a734f7c170818f5c45172842453 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Fri, 2 Jan 2026 11:19:31 +0000
Subject: [PATCH 27/41] Add wrapper around type constructors to fallback to
scalars when extended types aren't enabled
---
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 86f091297bc4a..b909e7e63fc0b 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -98,6 +98,27 @@ class LLT {
APFloat::getSizeInBits(APFloatBase::EnumToSemantics(Sem)), Sem};
}
+ static LLT buildInteger(unsigned SizeInBits) {
+ if (!getUseExtended())
+ return LLT::scalar(SizeInBits);
+
+ return integer(SizeInBits);
+ }
+
+ static LLT buildFloatingPoint(const FpSemantics &Sem) {
+ if (!getUseExtended())
+ return LLT::scalar(APFloat::getSizeInBits(APFloatBase::EnumToSemantics(Sem)));
+
+ return floatingPoint(Sem);
+ }
+
+ static LLT buildFloatingIEEE(unsigned SizeInBits) {
+ if (!getUseExtended())
+ return LLT::scalar(SizeInBits);
+
+ return floatIEEE(SizeInBits);
+ }
+
/// Get a low-level token; just a scalar with zero bits (or no size).
static constexpr LLT token() {
return LLT{Kind::ANY_SCALAR, ElementCount::getFixed(0),
>From 12b9b094b8eb33b6bc0a3fd26a0068dcfcc6a82f Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Mon, 12 Jan 2026 15:48:12 +0300
Subject: [PATCH 28/41] Modify mutations to change the size of types, not the
type itself
---
.../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 26 +++++++++++--------
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 22 +++++++++-------
.../CodeGen/GlobalISel/LegalizeMutations.cpp | 12 +++++++--
3 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 9324bab3fe656..bb5145fcab963 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -402,6 +402,11 @@ LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx,
LLVM_ABI LegalizeMutation changeElementSizeTo(unsigned TypeIdx,
unsigned FromTypeIdx);
+/// Change the scalar size or element size to have the same scalar size as the
+/// type \p NewTy. Unlike changeElementTo, this discards pointer types and only
+/// changes the size.
+LLVM_ABI LegalizeMutation changeElementSizeTo(unsigned TypeIdx, LLT NewTy);
+
/// Widen the scalar type or vector element type for the given type index to the
/// next power of 2.
LLVM_ABI LegalizeMutation widenScalarOrEltToNextPow2(unsigned TypeIdx,
@@ -1032,7 +1037,7 @@ class LegalizeRuleSet {
using namespace LegalizeMutations;
return actionIf(LegalizeAction::WidenScalar,
scalarOrEltNarrowerThan(TypeIdx, Ty.getScalarSizeInBits()),
- changeElementTo(typeIdx(TypeIdx), Ty));
+ changeElementSizeTo(typeIdx(TypeIdx), Ty));
}
/// Ensure the scalar or element is at least as wide as Ty.
@@ -1043,7 +1048,7 @@ class LegalizeRuleSet {
return actionIf(LegalizeAction::WidenScalar,
all(Predicate, scalarOrEltNarrowerThan(
TypeIdx, Ty.getScalarSizeInBits())),
- changeElementTo(typeIdx(TypeIdx), Ty));
+ changeElementSizeTo(typeIdx(TypeIdx), Ty));
}
/// Ensure the vector size is at least as wide as VectorSize by promoting the
@@ -1062,7 +1067,7 @@ class LegalizeRuleSet {
const LLT VecTy = Query.Types[TypeIdx];
unsigned NumElts = VecTy.getNumElements();
unsigned MinSize = VectorSize / NumElts;
- LLT NewTy = LLT::fixed_vector(NumElts, LLT::scalar(MinSize));
+ LLT NewTy = LLT::fixed_vector(NumElts, VecTy.getElementType().changeElementSize(MinSize));
return std::make_pair(TypeIdx, NewTy);
});
}
@@ -1073,7 +1078,7 @@ class LegalizeRuleSet {
using namespace LegalizeMutations;
return actionIf(LegalizeAction::WidenScalar,
scalarNarrowerThan(TypeIdx, Ty.getSizeInBits()),
- changeTo(typeIdx(TypeIdx), Ty));
+ changeElementSizeTo(typeIdx(TypeIdx), Ty));
}
LegalizeRuleSet &minScalar(bool Pred, unsigned TypeIdx, const LLT Ty) {
if (!Pred)
@@ -1094,7 +1099,7 @@ class LegalizeRuleSet {
QueryTy.getSizeInBits() < Ty.getSizeInBits() &&
Predicate(Query);
},
- changeTo(typeIdx(TypeIdx), Ty));
+ changeElementSizeTo(typeIdx(TypeIdx), Ty));
}
/// Ensure the scalar is at most as wide as Ty.
@@ -1103,7 +1108,7 @@ class LegalizeRuleSet {
using namespace LegalizeMutations;
return actionIf(LegalizeAction::NarrowScalar,
scalarOrEltWiderThan(TypeIdx, Ty.getScalarSizeInBits()),
- changeElementTo(typeIdx(TypeIdx), Ty));
+ changeElementSizeTo(typeIdx(TypeIdx), Ty));
}
/// Ensure the scalar is at most as wide as Ty.
@@ -1112,7 +1117,7 @@ class LegalizeRuleSet {
using namespace LegalizeMutations;
return actionIf(LegalizeAction::NarrowScalar,
scalarWiderThan(TypeIdx, Ty.getSizeInBits()),
- changeTo(typeIdx(TypeIdx), Ty));
+ changeElementSizeTo(typeIdx(TypeIdx), Ty));
}
/// Conditionally limit the maximum size of the scalar.
@@ -1130,7 +1135,7 @@ class LegalizeRuleSet {
QueryTy.getSizeInBits() > Ty.getSizeInBits() &&
Predicate(Query);
},
- changeElementTo(typeIdx(TypeIdx), Ty));
+ changeElementSizeTo(typeIdx(TypeIdx), Ty));
}
/// Limit the range of scalar sizes to MinTy and MaxTy.
@@ -1195,9 +1200,8 @@ class LegalizeRuleSet {
Predicate(Query);
},
[=](const LegalityQuery &Query) {
- LLT T = Query.Types[LargeTypeIdx];
- if (T.isPointerVector())
- T = T.changeElementType(LLT::scalar(T.getScalarSizeInBits()));
+ LLT T = Query.Types[TypeIdx].changeElementSize(
+ Query.Types[LargeTypeIdx].getScalarSizeInBits());
return std::make_pair(TypeIdx, T);
});
}
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index b909e7e63fc0b..4d8164b9bb358 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -402,16 +402,20 @@ class LLT {
/// If this type is a vector, return a vector with the same number of elements
/// but the new element size. Otherwise, return the new element type. Invalid
- /// for pointer and floating point types. For these, use changeElementType.
+ /// for pointer types. For these, use changeElementType.
constexpr LLT changeElementSize(unsigned NewEltSize) const {
- assert(!isPointerOrPointerVector() && !(isFloat() || isFloatVector()) &&
- "invalid to directly change element size for pointers and floats");
- return isVector()
- ? LLT::vector(getElementCount(), getElementType().isInteger()
- ? LLT::integer(NewEltSize)
- : LLT::scalar(NewEltSize))
- : isInteger() ? LLT::integer(NewEltSize)
- : LLT::scalar(NewEltSize);
+ assert(!isPointerOrPointerVector() &&
+ "invalid to directly change element size for pointers");
+ if (isVector())
+ return LLT::vector(getElementCount(), getElementType().changeElementSize(NewEltSize));
+
+ if (isInteger())
+ return LLT::integer(NewEltSize);
+
+ if (isFloatIEEE())
+ return LLT::floatIEEE(NewEltSize);
+
+ return LLT::scalar(NewEltSize);
}
/// Return a vector with the same element type and the new element count. Must
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
index ded4df4edc14c..92a94401403f5 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
@@ -67,8 +67,16 @@ LegalizeMutation LegalizeMutations::changeElementSizeTo(unsigned TypeIdx,
return [=](const LegalityQuery &Query) {
const LLT OldTy = Query.Types[TypeIdx];
const LLT NewTy = Query.Types[FromTypeIdx];
- const LLT NewEltTy = LLT::scalar(NewTy.getScalarSizeInBits());
- return std::make_pair(TypeIdx, OldTy.changeElementType(NewEltTy));
+ return std::make_pair(TypeIdx, OldTy.changeElementSize(NewTy.getScalarSizeInBits()));
+ };
+}
+
+LegalizeMutation LegalizeMutations::changeElementSizeTo(unsigned TypeIdx,
+ LLT NewTy) {
+ return [=](const LegalityQuery &Query) {
+ const LLT OldTy = Query.Types[TypeIdx];
+ return std::make_pair(TypeIdx,
+ OldTy.changeElementSize(NewTy.getScalarSizeInBits()));
};
}
>From cfed5d4f186eb57a1c3f5191172ecae9375737e5 Mon Sep 17 00:00:00 2001
From: Denis Gerasimov <dengzmm at gmail.com>
Date: Mon, 12 Jan 2026 16:11:34 +0300
Subject: [PATCH 29/41] format
---
llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h | 3 ++-
llvm/include/llvm/CodeGenTypes/LowLevelType.h | 6 ++++--
llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp | 3 ++-
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index bb5145fcab963..ad8ef30d8659c 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -1067,7 +1067,8 @@ class LegalizeRuleSet {
const LLT VecTy = Query.Types[TypeIdx];
unsigned NumElts = VecTy.getNumElements();
unsigned MinSize = VectorSize / NumElts;
- LLT NewTy = LLT::fixed_vector(NumElts, VecTy.getElementType().changeElementSize(MinSize));
+ LLT NewTy = LLT::fixed_vector(
+ NumElts, VecTy.getElementType().changeElementSize(MinSize));
return std::make_pair(TypeIdx, NewTy);
});
}
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 4d8164b9bb358..d79f3a4a8e246 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -107,7 +107,8 @@ class LLT {
static LLT buildFloatingPoint(const FpSemantics &Sem) {
if (!getUseExtended())
- return LLT::scalar(APFloat::getSizeInBits(APFloatBase::EnumToSemantics(Sem)));
+ return LLT::scalar(
+ APFloat::getSizeInBits(APFloatBase::EnumToSemantics(Sem)));
return floatingPoint(Sem);
}
@@ -407,7 +408,8 @@ class LLT {
assert(!isPointerOrPointerVector() &&
"invalid to directly change element size for pointers");
if (isVector())
- return LLT::vector(getElementCount(), getElementType().changeElementSize(NewEltSize));
+ return LLT::vector(getElementCount(),
+ getElementType().changeElementSize(NewEltSize));
if (isInteger())
return LLT::integer(NewEltSize);
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
index 92a94401403f5..f7ead3b41ea49 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
@@ -67,7 +67,8 @@ LegalizeMutation LegalizeMutations::changeElementSizeTo(unsigned TypeIdx,
return [=](const LegalityQuery &Query) {
const LLT OldTy = Query.Types[TypeIdx];
const LLT NewTy = Query.Types[FromTypeIdx];
- return std::make_pair(TypeIdx, OldTy.changeElementSize(NewTy.getScalarSizeInBits()));
+ return std::make_pair(TypeIdx,
+ OldTy.changeElementSize(NewTy.getScalarSizeInBits()));
};
}
>From 09ebfd48db57744694699de5766ac1a94b74788d Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 14:40:32 +0000
Subject: [PATCH 30/41] Enabled extended types in AArch64 & no longer skip bf16
patterns with extended types enabled.
---
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 ++
llvm/lib/Target/AArch64/CMakeLists.txt | 2 +-
llvm/utils/TableGen/GlobalISelEmitter.cpp | 3 ++-
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 1ec5a20cc0ce0..444bf573e05c8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -390,6 +390,8 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
setGlobalISelAbort(GlobalISelAbortMode::Disable);
}
+ LLT::setUseExtended(true);
+
// AArch64 supports the MachineOutliner.
setMachineOutliner(true);
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt
index 3334b3689e03f..a87a7d076ae4f 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -9,7 +9,7 @@ tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
-tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel -gisel-extended-llt)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="AArch64O0PreLegalizerCombiner")
tablegen(LLVM AArch64GenPreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 84024ec086808..530672667ec42 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2462,7 +2462,8 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
// Skip any patterns containing BF16 types, as GISel cannot currently tell
// the difference between fp16 and bf16. FIXME: This can be removed once
// BF16 is supported properly.
- if (hasBFloatType(Pat.getSrcPattern()))
+ bool UseExtended = LLT::getUseExtended();
+ if (hasBFloatType(Pat.getSrcPattern()) && !UseExtended)
continue;
auto MatcherOrErr = runOnPattern(Pat);
>From 6732b4af6eb35271b3c4c3e2bfa83b32cc1241f7 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 14:41:12 +0000
Subject: [PATCH 31/41] Try to match multiple types in the match table. Start
with the given type, then try integers and finally fall back to scalars.
---
.../GlobalISel/GIMatchTableExecutorImpl.h | 48 ++++++++++++++-----
1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index a50a0a04fe2bc..e93013e0616a9 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -285,24 +285,46 @@ bool GIMatchTableExecutor::executeMatchTable(
break;
}
const LLT Ty = MRI.getType(MO.getReg());
- const auto TyI = ExecInfo.TypeIDMap.find(Ty);
- if (TyI == ExecInfo.TypeIDMap.end()) {
- CurrentIdx = Default;
- break;
- }
- const int64_t TypeID = TyI->second;
- if (TypeID < LowerBound || UpperBound <= TypeID) {
- CurrentIdx = Default;
+
+ SmallVector<LLT> TypesToTry;
+ TypesToTry.push_back(Ty);
+
+ // Always try the integer patterns as we now consider that to be generic
+ // (to an extent)
+ if (LLT::getUseExtended() && !Ty.getScalarType().isInteger())
+ TypesToTry.push_back(
+ Ty.changeElementType(LLT::integer(Ty.getScalarSizeInBits())));
+
+ if (LLT::getUseExtended() && Ty.isAnyScalar() &&
+ Ty.getScalarSizeInBits() > 8)
+ TypesToTry.push_back(
+ Ty.changeElementType(LLT::floatIEEE(Ty.getScalarSizeInBits())));
+
+ const auto JumpTableBase = CurrentIdx;
+ bool Matched = false;
+ for (LLT Type : TypesToTry) {
+ const auto TyI = ExecInfo.TypeIDMap.find(Type);
+ if (TyI == ExecInfo.TypeIDMap.end())
+ continue;
+ const int64_t TypeID = TyI->second;
+ if (TypeID < LowerBound || UpperBound <= TypeID)
+ continue;
+ const auto NumEntry = (TypeID - LowerBound);
+ // Each entry is 4 bytes
+ CurrentIdx =
+ readBytesAs<uint32_t>(MatchTable + JumpTableBase + (NumEntry * 4));
+ if (!CurrentIdx) {
+ CurrentIdx = Default;
+ continue;
+ }
+ Matched = true;
break;
}
- const auto NumEntry = (TypeID - LowerBound);
- // Each entry is 4 bytes
- CurrentIdx =
- readBytesAs<uint32_t>(MatchTable + CurrentIdx + (NumEntry * 4));
- if (!CurrentIdx) {
+ if (!Matched) {
CurrentIdx = Default;
break;
}
+
OnFailResumeAt.push_back(Default);
break;
}
>From 99bf92b6aebd7abace5c1e82397892c3bf9309fc Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 31 Dec 2025 09:35:38 +0000
Subject: [PATCH 32/41] Add mutation to allow for converting bf16 to fp32
---
.../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index ad8ef30d8659c..b3a8e86cbb546 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -854,6 +854,39 @@ class LegalizeRuleSet {
return actionFor(LegalizeAction::NarrowScalar, Types, Mutation);
}
+ /// Promote bf16 operands/results to \p PromoteEltTy so the operation executes
+ /// in that wider type before truncating back to bf16.
+ LegalizeRuleSet &convertBF16(unsigned TypeIdx = 0,
+ LLT PromoteEltTy = LLT::float32()) {
+ assert(!PromoteEltTy.isVector() && PromoteEltTy.isScalar() &&
+ PromoteEltTy.isFloat() &&
+ "convertBF16 expects a floating-point scalar promotion type");
+ typeIdx(TypeIdx);
+ const LLT BF16Ty = LLT::bfloat16();
+ return widenScalarIf(
+ [=](const LegalityQuery &Query) {
+ if (TypeIdx >= Query.Types.size())
+ return false;
+ const LLT Ty = Query.Types[TypeIdx];
+ if (!Ty.isValid())
+ return false;
+ if (Ty == BF16Ty)
+ return true;
+ if (Ty.isVector() && Ty.getElementType() == BF16Ty)
+ return true;
+ return false;
+ },
+ LegalizeMutations::changeElementTo(TypeIdx, PromoteEltTy));
+ }
+
+ /// Conditionally promote bf16 operands/results to \p PromoteEltTy.
+ LegalizeRuleSet &convertBF16(bool Enable, unsigned TypeIdx = 0,
+ LLT PromoteEltTy = LLT::float32()) {
+ if (!Enable)
+ return *this;
+ return convertBF16(TypeIdx, PromoteEltTy);
+ }
+
/// Add more elements to reach the type selected by the mutation if the
/// predicate is true.
LegalizeRuleSet &moreElementsIf(LegalityPredicate Predicate,
>From 97720a0bbd486cf550cac9eb47925db8eeebfdd9 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 15:36:59 +0000
Subject: [PATCH 33/41] Modify construction of types to reduce the instances of
of scalar types.
---
llvm/include/llvm/CodeGen/TargetLowering.h | 2 +-
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 2 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 29 ++--
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 144 +++++++++++-------
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 2 +-
.../Target/AArch64/AArch64ISelLowering.cpp | 8 +-
.../AArch64/GISel/AArch64CallLowering.cpp | 10 +-
.../GISel/AArch64InstructionSelector.cpp | 5 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 86 ++++++-----
.../GISel/AArch64PostLegalizerCombiner.cpp | 5 +-
.../GISel/AArch64PostLegalizerLowering.cpp | 10 +-
.../GISel/AArch64PreLegalizerCombiner.cpp | 26 ++--
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 4 +-
13 files changed, 189 insertions(+), 144 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 1df4ba582d1b9..92df37765c4a1 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -443,7 +443,7 @@ class LLVM_ABI TargetLoweringBase {
/// G_INSERT_VECTOR_ELT, G_EXTRACT_VECTOR_ELT,
/// G_INSERT_SUBVECTOR, and G_EXTRACT_SUBVECTOR
LLT getVectorIdxLLT(const DataLayout &DL) const {
- return LLT::scalar(getVectorIdxWidth(DL));
+ return LLT::integer(getVectorIdxWidth(DL));
}
/// Returns the type to be used for the EVL/AVL operand of VP nodes:
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index c1501b2f428f7..a62973965564f 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -1290,7 +1290,7 @@ void CallLowering::ValueHandler::copyArgumentMemory(
MemSize, DstAlign);
const LLT PtrTy = MRI.getType(DstPtr);
- const LLT SizeTy = LLT::scalar(PtrTy.getSizeInBits());
+ const LLT SizeTy = LLT::integer(PtrTy.getSizeInBits());
auto SizeConst = MIRBuilder.buildConstant(SizeTy, MemSize);
MIRBuilder.buildMemCpy(DstPtr, SrcPtr, SizeConst, *DstMMO, *SrcMMO);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index e990a9706da0b..df26478380f04 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -888,7 +888,7 @@ bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
auto Cst = getOrCreateVReg(
*ConstantInt::get(SValue.getType(), JTH.Last - JTH.First));
Cst = MIB.buildZExtOrTrunc(PtrScalarTy, Cst).getReg(0);
- auto Cmp = MIB.buildICmp(CmpInst::ICMP_UGT, LLT::scalar(1), Sub, Cst);
+ auto Cmp = MIB.buildICmp(CmpInst::ICMP_UGT, LLT::integer(1), Sub, Cst);
auto BrCond = MIB.buildBrCond(Cmp.getReg(0), *JT.Default);
@@ -919,7 +919,7 @@ void IRTranslator::emitSwitchCase(SwitchCG::CaseBlock &CB,
return;
}
- const LLT i1Ty = LLT::scalar(1);
+ const LLT i1Ty = LLT::integer(1);
// Build the compare.
if (!CB.CmpMHS) {
const auto *CI = dyn_cast<ConstantInt>(CB.CmpRHS);
@@ -1131,7 +1131,7 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
if (!B.FallthroughUnreachable) {
// Conditional branch to the default block.
auto RangeCst = MIB.buildConstant(SwitchOpTy, B.Range);
- auto RangeCmp = MIB.buildICmp(CmpInst::Predicate::ICMP_UGT, LLT::scalar(1),
+ auto RangeCmp = MIB.buildICmp(CmpInst::Predicate::ICMP_UGT, LLT::integer(1),
RangeSub, RangeCst);
MIB.buildBrCond(RangeCmp, *B.Default);
}
@@ -1157,15 +1157,16 @@ void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB,
// would need to be to shift a 1 bit in that position.
auto MaskTrailingZeros =
MIB.buildConstant(SwitchTy, llvm::countr_zero(B.Mask));
- Cmp =
- MIB.buildICmp(ICmpInst::ICMP_EQ, LLT::scalar(1), Reg, MaskTrailingZeros)
- .getReg(0);
+ Cmp = MIB.buildICmp(ICmpInst::ICMP_EQ, LLT::integer(1), Reg,
+ MaskTrailingZeros)
+ .getReg(0);
} else if (PopCount == BB.Range) {
// There is only one zero bit in the range, test for it directly.
auto MaskTrailingOnes =
MIB.buildConstant(SwitchTy, llvm::countr_one(B.Mask));
- Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Reg, MaskTrailingOnes)
- .getReg(0);
+ Cmp =
+ MIB.buildICmp(CmpInst::ICMP_NE, LLT::integer(1), Reg, MaskTrailingOnes)
+ .getReg(0);
} else {
// Make desired shift.
auto CstOne = MIB.buildConstant(SwitchTy, 1);
@@ -1175,7 +1176,7 @@ void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB,
auto CstMask = MIB.buildConstant(SwitchTy, B.Mask);
auto AndOp = MIB.buildAnd(SwitchTy, SwitchVal, CstMask);
auto CstZero = MIB.buildConstant(SwitchTy, 0);
- Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), AndOp, CstZero)
+ Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::integer(1), AndOp, CstZero)
.getReg(0);
}
@@ -1722,7 +1723,7 @@ bool IRTranslator::translateMemFunc(const CallInst &CI,
SrcRegs.push_back(SrcReg);
}
- LLT SizeTy = LLT::scalar(MinPtrSize);
+ LLT SizeTy = LLT::integer(MinPtrSize);
// The size operand should be the minimum of the pointer sizes.
Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1];
@@ -3265,7 +3266,8 @@ bool IRTranslator::translateInsertElement(const User &U,
if (!Idx)
Idx = getOrCreateVReg(*U.getOperand(2));
if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
- const LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
+ const LLT VecIdxTy =
+ MRI->getType(Idx).changeElementSize(PreferredVecIdxWidth);
Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0);
}
MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
@@ -3346,7 +3348,8 @@ bool IRTranslator::translateExtractElement(const User &U,
if (!Idx)
Idx = getOrCreateVReg(*U.getOperand(1));
if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
- const LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
+ const LLT VecIdxTy =
+ MRI->getType(Idx).changeElementSize(PreferredVecIdxWidth);
Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0);
}
MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
@@ -4071,7 +4074,7 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
// Perform the comparison.
auto Cmp =
- CurBuilder->buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Guard, GuardVal);
+ CurBuilder->buildICmp(CmpInst::ICMP_NE, LLT::integer(1), Guard, GuardVal);
// If the guard/stackslot do not equal, branch to failure MBB.
CurBuilder->buildBrCond(Cmp, *SPD.getFailureMBB());
// Otherwise branch to success MBB.
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index e40b34b0b306f..5ec47ca632903 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1178,7 +1178,7 @@ LegalizerHelper::createFCMPLibcall(MachineIRBuilder &MIRBuilder,
const CmpInst::Predicate ICmpPred,
const DstOp &Res) -> Register {
// FCMP libcall always returns an i32, and needs an ICMP with #0.
- constexpr LLT TempLLT = LLT::scalar(32);
+ constexpr LLT TempLLT = LLT::integer(32);
Register Temp = MRI.createGenericVirtualRegister(TempLLT);
// Generate libcall, holding result in Temp
const auto Status = createLibcall(
@@ -3284,10 +3284,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
LLT VecTy = MRI.getType(VecReg);
Observer.changingInstr(MI);
- widenScalarSrc(
- MI,
- VecTy.changeVectorElementType(LLT::scalar(WideTy.getSizeInBits())), 1,
- TargetOpcode::G_ANYEXT);
+ widenScalarSrc(MI, LLT::vector(VecTy.getElementCount(), WideTy), 1,
+ TargetOpcode::G_ANYEXT);
widenScalarDst(MI, WideTy, 0);
Observer.changedInstr(MI);
@@ -3941,7 +3939,7 @@ LegalizerHelper::bitcastConcatVector(MachineInstr &MI, unsigned TypeIdx,
// Check if bitcast is Legal
auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
- LLT SrcScalTy = LLT::scalar(SrcTy.getSizeInBits());
+ LLT SrcScalTy = CastTy.getScalarType();
// Check if the build vector is Legal
if (!LI.isLegal({TargetOpcode::G_BUILD_VECTOR, {CastTy, SrcScalTy}})) {
@@ -4139,6 +4137,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerLoad(GAnyLoad &LoadMI) {
LLT MemTy = MMO.getMemoryType();
MachineFunction &MF = MIRBuilder.getMF();
+ LLT EltTy = MemTy.getScalarType();
+
unsigned MemSizeInBits = MemTy.getSizeInBits();
unsigned MemStoreSizeInBits = 8 * MemTy.getSizeInBytes();
@@ -4148,7 +4148,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerLoad(GAnyLoad &LoadMI) {
// Promote to a byte-sized load if not loading an integral number of
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
- LLT WideMemTy = LLT::scalar(MemStoreSizeInBits);
+ LLT WideMemTy = EltTy.changeElementSize(MemStoreSizeInBits);
MachineMemOperand *NewMMO =
MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideMemTy);
@@ -4250,12 +4250,22 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerLoad(GAnyLoad &LoadMI) {
LLT PtrTy = MRI.getType(PtrReg);
unsigned AnyExtSize = PowerOf2Ceil(DstTy.getSizeInBits());
- LLT AnyExtTy = LLT::scalar(AnyExtSize);
+
+ LLT AnyExtTy;
+ LLT OffsetCstRes;
+ if (EltTy.isPointer()) {
+ AnyExtTy = LLT::scalar(AnyExtSize);
+ OffsetCstRes = LLT::scalar(PtrTy.getSizeInBits());
+ } else {
+ AnyExtTy = EltTy.changeElementSize(AnyExtSize);
+ OffsetCstRes = EltTy.changeElementSize(PtrTy.getSizeInBits());
+ }
+
auto LargeLoad = MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, AnyExtTy,
PtrReg, *LargeMMO);
- auto OffsetCst = MIRBuilder.buildConstant(LLT::scalar(PtrTy.getSizeInBits()),
- LargeSplitSize / 8);
+ auto OffsetCst = MIRBuilder.buildConstant(
+ OffsetCstRes, LargeSplitSize / 8);
Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
auto SmallPtr = MIRBuilder.buildObjectPtrOffset(PtrAddReg, PtrReg, OffsetCst);
auto SmallLoad = MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), AnyExtTy,
@@ -4392,7 +4402,7 @@ LegalizerHelper::scalarizeVectorBooleanStore(GStore &StoreMI) {
// We need to build an integer scalar of the vector bit pattern.
// It's not legal for us to add padding when storing a vector.
unsigned NumBits = MemTy.getSizeInBits();
- LLT IntTy = LLT::scalar(NumBits);
+ LLT IntTy = LLT::integer(NumBits);
auto CurrVal = MIRBuilder.buildConstant(IntTy, 0);
LLT IdxTy = TLI.getVectorIdxLLT(MF.getDataLayout());
@@ -5448,7 +5458,7 @@ LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
return UnableToLegalize;
LLT PtrTy = MRI.getType(AddrReg);
- const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
+ const LLT OffsetTy = LLT::integer(PtrTy.getSizeInBits());
unsigned TotalSize = ValTy.getSizeInBits();
@@ -6139,7 +6149,7 @@ LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
// input. If that isn't small enough, the resulting pieces will be further
// legalized.
const unsigned NewBitSize = DstEltSize / 2;
- const LLT HalfTy = LLT::scalar(NewBitSize);
+ const LLT HalfTy = DstTy.getScalarType().changeElementSize(NewBitSize);
const LLT CondTy = LLT::scalar(1);
if (auto VRegAndVal = getIConstantVRegValWithLookThrough(Amt, MRI)) {
@@ -8216,11 +8226,13 @@ LegalizerHelper::lowerU64ToF64BitFloatOps(MachineInstr &MI) {
static LegalizerHelper::LegalizeResult
loweri64tof16ITOFP(MachineInstr &MI, Register Dst, LLT DstTy, Register Src,
LLT SrcTy, MachineIRBuilder &MIRBuilder) {
+ auto DstFpTy =
+ SrcTy.changeElementType(LLT::floatIEEE(SrcTy.getScalarSizeInBits()));
auto M1 = MI.getOpcode() == TargetOpcode::G_UITOFP
- ? MIRBuilder.buildUITOFP(SrcTy, Src)
- : MIRBuilder.buildSITOFP(SrcTy, Src);
- LLT S32Ty = SrcTy.changeElementSize(32);
- auto M2 = MIRBuilder.buildFPTrunc(S32Ty, M1);
+ ? MIRBuilder.buildUITOFP(DstFpTy, Src)
+ : MIRBuilder.buildSITOFP(DstFpTy, Src);
+ LLT F32Ty = DstFpTy.changeElementSize(32);
+ auto M2 = MIRBuilder.buildFPTrunc(F32Ty, M1);
MIRBuilder.buildFPTrunc(Dst, M2);
MI.eraseFromParent();
return LegalizerHelper::Legalized;
@@ -8259,11 +8271,11 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) {
LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) {
auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
- const LLT S64 = LLT::scalar(64);
- const LLT S32 = LLT::scalar(32);
- const LLT S1 = LLT::scalar(1);
+ const LLT I64 = LLT::integer(64);
+ const LLT I32 = LLT::integer(32);
+ const LLT I1 = LLT::integer(1);
- if (SrcTy == S1) {
+ if (SrcTy == I1) {
auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
MIRBuilder.buildSelect(Dst, Src, True, False);
@@ -8274,26 +8286,26 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) {
if (DstTy.getScalarSizeInBits() == 16 && SrcTy.getScalarSizeInBits() == 64)
return loweri64tof16ITOFP(MI, Dst, DstTy, Src, SrcTy, MIRBuilder);
- if (SrcTy != S64)
+ if (SrcTy != I64)
return UnableToLegalize;
- if (DstTy == S32) {
+ if (DstTy.getScalarSizeInBits() == 32) {
// signed cl2f(long l) {
// long s = l >> 63;
// float r = cul2f((l + s) ^ s);
// return s ? -r : r;
// }
Register L = Src;
- auto SignBit = MIRBuilder.buildConstant(S64, 63);
- auto S = MIRBuilder.buildAShr(S64, L, SignBit);
+ auto SignBit = MIRBuilder.buildConstant(I64, 63);
+ auto S = MIRBuilder.buildAShr(I64, L, SignBit);
- auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
- auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
- auto R = MIRBuilder.buildUITOFP(S32, Xor);
+ auto LPlusS = MIRBuilder.buildAdd(I64, L, S);
+ auto Xor = MIRBuilder.buildXor(I64, LPlusS, S);
+ auto R = MIRBuilder.buildUITOFP(I32, Xor);
- auto RNeg = MIRBuilder.buildFNeg(S32, R);
- auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
- MIRBuilder.buildConstant(S64, 0));
+ auto RNeg = MIRBuilder.buildFNeg(I32, R);
+ auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, I1, S,
+ MIRBuilder.buildConstant(I64, 0));
MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
MI.eraseFromParent();
return Legalized;
@@ -8441,14 +8453,13 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
if (AreExactFloatBounds) {
// Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat.
auto MaxC = MIRBuilder.buildFConstant(SrcTy, MinFloat);
- auto MaxP = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT,
- SrcTy.changeElementSize(1), Src, MaxC);
+ auto MaxP =
+ MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::integer(1), Src, MaxC);
auto Max = MIRBuilder.buildSelect(SrcTy, MaxP, Src, MaxC);
// Clamp by MaxFloat from above. NaN cannot occur.
auto MinC = MIRBuilder.buildFConstant(SrcTy, MaxFloat);
- auto MinP =
- MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, SrcTy.changeElementSize(1), Max,
- MinC, MachineInstr::FmNoNans);
+ auto MinP = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, LLT::integer(1), Max,
+ MinC, MachineInstr::FmNoNans);
auto Min =
MIRBuilder.buildSelect(SrcTy, MinP, Max, MinC, MachineInstr::FmNoNans);
// Convert clamped value to integer. In the unsigned case we're done,
@@ -8461,8 +8472,8 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
// Otherwise, select 0 if Src is NaN.
auto FpToInt = MIRBuilder.buildFPTOSI(DstTy, Min);
- auto IsZero = MIRBuilder.buildFCmp(CmpInst::FCMP_UNO,
- DstTy.changeElementSize(1), Src, Src);
+ auto IsZero =
+ MIRBuilder.buildFCmp(CmpInst::FCMP_UNO, LLT::integer(1), Src, Src);
MIRBuilder.buildSelect(Dst, IsZero, MIRBuilder.buildConstant(DstTy, 0),
FpToInt);
MI.eraseFromParent();
@@ -8477,15 +8488,13 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
// If Src ULT MinFloat, select MinInt. In particular, this also selects
// MinInt if Src is NaN.
- auto ULT =
- MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, SrcTy.changeElementSize(1), Src,
- MIRBuilder.buildFConstant(SrcTy, MinFloat));
+ auto ULT = MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, LLT::integer(1), Src,
+ MIRBuilder.buildFConstant(SrcTy, MinFloat));
auto Max = MIRBuilder.buildSelect(
DstTy, ULT, MIRBuilder.buildConstant(DstTy, MinInt), FpToInt);
// If Src OGT MaxFloat, select MaxInt.
- auto OGT =
- MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, SrcTy.changeElementSize(1), Src,
- MIRBuilder.buildFConstant(SrcTy, MaxFloat));
+ auto OGT = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::integer(1), Src,
+ MIRBuilder.buildFConstant(SrcTy, MaxFloat));
// In the unsigned case we are done, because we mapped NaN to MinInt, which
// is already zero.
@@ -8499,8 +8508,8 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
// Otherwise, select 0 if Src is NaN.
auto Min = MIRBuilder.buildSelect(
DstTy, OGT, MIRBuilder.buildConstant(DstTy, MaxInt), Max);
- auto IsZero = MIRBuilder.buildFCmp(CmpInst::FCMP_UNO,
- DstTy.changeElementSize(1), Src, Src);
+ auto IsZero =
+ MIRBuilder.buildFCmp(CmpInst::FCMP_UNO, LLT::integer(1), Src, Src);
MIRBuilder.buildSelect(Dst, IsZero, MIRBuilder.buildConstant(DstTy, 0), Min);
MI.eraseFromParent();
return Legalized;
@@ -8663,7 +8672,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) {
auto [Dst, Src0, Src1] = MI.getFirst3Regs();
const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
- LLT CmpType = MRI.getType(Dst).changeElementType(LLT::scalar(1));
+ LLT CmpType = MRI.getType(Dst).changeElementType(LLT::integer(1));
auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
@@ -8726,26 +8735,43 @@ LegalizerHelper::lowerFCopySign(MachineInstr &MI) {
const int Src0Size = Src0Ty.getScalarSizeInBits();
const int Src1Size = Src1Ty.getScalarSizeInBits();
- auto SignBitMask = MIRBuilder.buildConstant(
- Src0Ty, APInt::getSignMask(Src0Size));
+ LLT DstIntTy =
+ DstTy.changeElementType(LLT::integer(DstTy.getScalarSizeInBits()));
+ LLT Src0IntTy = Src0Ty.changeElementType(LLT::integer(Src0Size));
+ LLT Src1IntTy = Src1Ty.changeElementType(LLT::integer(Src1Size));
+
+ Register Src0Int = Src0;
+ Register Src1Int = Src1;
+
+ if (!(Src0Ty.getScalarType().isAnyScalar() ||
+ Src0Ty.getScalarType().isInteger()))
+ Src0Int = MIRBuilder.buildBitcast(Src0IntTy, Src0).getReg(0);
+
+ if (!(Src1Ty.getScalarType().isAnyScalar() ||
+ Src1Ty.getScalarType().isInteger()))
+ Src1Int = MIRBuilder.buildBitcast(Src1IntTy, Src1).getReg(0);
+
+ auto SignBitMask =
+ MIRBuilder.buildConstant(Src0IntTy, APInt::getSignMask(Src0Size));
auto NotSignBitMask = MIRBuilder.buildConstant(
- Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
+ Src0IntTy, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
- Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0);
+ Register And0 =
+ MIRBuilder.buildAnd(Src0IntTy, Src0Int, NotSignBitMask).getReg(0);
Register And1;
if (Src0Ty == Src1Ty) {
- And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0);
+ And1 = MIRBuilder.buildAnd(Src1IntTy, Src1Int, SignBitMask).getReg(0);
} else if (Src0Size > Src1Size) {
- auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
- auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
- auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
+ auto ShiftAmt = MIRBuilder.buildConstant(Src0IntTy, Src0Size - Src1Size);
+ auto Zext = MIRBuilder.buildZExt(Src0IntTy, Src1Int);
+ auto Shift = MIRBuilder.buildShl(Src0IntTy, Zext, ShiftAmt);
And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0);
} else {
- auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
- auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
- auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
- And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0);
+ auto ShiftAmt = MIRBuilder.buildConstant(Src1IntTy, Src1Size - Src0Size);
+ auto Shift = MIRBuilder.buildLShr(Src1IntTy, Src1Int, ShiftAmt);
+ auto Trunc = MIRBuilder.buildTrunc(Src0IntTy, Shift);
+ And1 = MIRBuilder.buildAnd(Src0IntTy, Trunc, SignBitMask).getReg(0);
}
// Be careful about setting nsz/nnan/ninf on every instruction, since the
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 0468c214e4bae..63c9ada9b059d 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -787,7 +787,7 @@ MachineInstrBuilder MachineIRBuilder::buildShuffleSplat(const DstOp &Res,
assert(Src.getLLTTy(*getMRI()) == DstTy.getElementType() &&
"Expected Src to match Dst elt ty");
auto UndefVec = buildUndef(DstTy);
- auto Zero = buildConstant(LLT::scalar(64), 0);
+ auto Zero = buildConstant(LLT::integer(64), 0);
auto InsElt = buildInsertVectorElement(DstTy, UndefVec, Src, Zero);
SmallVector<int, 16> ZeroMask(DstTy.getNumElements());
return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ffd9641e9f9df..20dc0b020fb91 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18735,13 +18735,13 @@ LLT AArch64TargetLowering::getOptimalMemOpLLT(
if (CanUseNEON && Op.isMemset() && !IsSmallMemset &&
AlignmentIsAcceptable(MVT::v2i64, Align(16)))
- return LLT::fixed_vector(2, 64);
+ return LLT::fixed_vector(2, LLT::integer(64));
if (CanUseFP && !IsSmallMemset && AlignmentIsAcceptable(MVT::f128, Align(16)))
- return LLT::scalar(128);
+ return LLT::floatIEEE(128);
if (Op.size() >= 8 && AlignmentIsAcceptable(MVT::i64, Align(8)))
- return LLT::scalar(64);
+ return LLT::integer(64);
if (Op.size() >= 4 && AlignmentIsAcceptable(MVT::i32, Align(4)))
- return LLT::scalar(32);
+ return LLT::integer(32);
return LLT();
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 7907a3c283624..e975932763e0e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -257,7 +257,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
ISD::ArgFlagsTy Flags) override {
MachineFunction &MF = MIRBuilder.getMF();
LLT p0 = LLT::pointer(0, 64);
- LLT s64 = LLT::scalar(64);
+ LLT s64 = LLT::integer(64);
if (IsTailCall) {
assert(!Flags.isByVal() && "byval unhandled with tail calls");
@@ -444,7 +444,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
auto &Flags = CurArgInfo.Flags[0];
if (MRI.getType(CurVReg).getSizeInBits() == TypeSize::getFixed(1) &&
!Flags.isSExt() && !Flags.isZExt()) {
- CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
+ CurVReg = MIRBuilder.buildZExt(LLT::integer(8), CurVReg).getReg(0);
} else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
1) {
// Some types will need extending as specified by the CC.
@@ -611,7 +611,7 @@ void AArch64CallLowering::saveVarArgRegisters(
bool IsWin64CC = Subtarget.isCallingConvWin64(CCInfo.getCallingConv(),
MF.getFunction().isVarArg());
const LLT p0 = LLT::pointer(0, 64);
- const LLT s64 = LLT::scalar(64);
+ const LLT s64 = LLT::integer(64);
unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
unsigned NumVariadicGPRArgRegs = GPRArgRegs.size() - FirstVariadicGPR + 1;
@@ -735,7 +735,7 @@ bool AArch64CallLowering::lowerFormalArguments(
if (!Flags.isZExt() && !Flags.isSExt()) {
// Lower i1 argument as i8, and insert AssertZExt + Trunc later.
Register OrigReg = OrigArg.Regs[0];
- Register WideReg = MRI.createGenericVirtualRegister(LLT::scalar(8));
+ Register WideReg = MRI.createGenericVirtualRegister(LLT::integer(8));
OrigArg.Regs[0] = WideReg;
BoolArgs.push_back({OrigReg, WideReg});
}
@@ -1341,7 +1341,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// We cannot use a ZExt ArgInfo flag here, because it will
// zero-extend the argument to i32 instead of just i8.
OutArg.Regs[0] =
- MIRBuilder.buildZExt(LLT::scalar(8), OutArg.Regs[0]).getReg(0);
+ MIRBuilder.buildZExt(LLT::integer(8), OutArg.Regs[0]).getReg(0);
LLVMContext &Ctx = MF.getFunction().getContext();
OutArg.Ty = Type::getInt8Ty(Ctx);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index f9db39e5f8622..9809675a6995a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2226,8 +2226,9 @@ bool AArch64InstructionSelector::convertPtrAddToAdd(
if (PtrTy.getAddressSpace() != 0)
return false;
- const LLT CastPtrTy =
- PtrTy.isVector() ? LLT::fixed_vector(2, 64) : LLT::scalar(64);
+ const LLT CastPtrTy = PtrTy.isVector()
+ ? LLT::fixed_vector(2, LLT::integer(64))
+ : LLT::integer(64);
auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg);
// Set regbanks on the registers.
if (PtrTy.isVector())
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 1ae0b99416a29..1e663342527d8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1801,20 +1801,22 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(2).getReg();
LLT DstTy = MRI.getType(DstReg);
+ LLT DstTyScalar = DstTy.getScalarType();
LLT MidTy, ExtTy;
if (DstTy.isScalar() && DstTy.getScalarSizeInBits() <= 32) {
- MidTy = LLT::fixed_vector(4, 32);
- ExtTy = LLT::scalar(32);
+ ExtTy = DstTyScalar.changeElementSize(32);
+ MidTy = LLT::fixed_vector(4, ExtTy);
} else {
- MidTy = LLT::fixed_vector(2, 64);
- ExtTy = LLT::scalar(64);
+ ExtTy = DstTy.changeElementSize(64);
+ MidTy = LLT::fixed_vector(2, ExtTy);
}
Register MidReg =
MIB.buildInstr(Opc, {MidTy}, {SrcReg})->getOperand(0).getReg();
- Register ZeroReg =
- MIB.buildConstant(LLT::scalar(64), 0)->getOperand(0).getReg();
+ Register ZeroReg = MIB.buildConstant(DstTyScalar.changeElementSize(64), 0)
+ ->getOperand(0)
+ .getReg();
Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy},
{MidReg, ZeroReg})
.getReg(0);
@@ -2019,6 +2021,7 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(
// If the shift amount is a G_CONSTANT, promote it to a 64 bit type so the
// imported patterns can select it later. Either way, it will be legal.
Register AmtReg = MI.getOperand(2).getReg();
+ LLT AmtRegEltTy = MRI.getType(AmtReg).getScalarType();
auto VRegAndVal = getIConstantVRegValWithLookThrough(AmtReg, MRI);
if (!VRegAndVal)
return true;
@@ -2026,7 +2029,8 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(
int64_t Amount = VRegAndVal->Value.getSExtValue();
if (Amount > 31)
return true; // This will have to remain a register variant.
- auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount);
+ auto ExtCst =
+ MIRBuilder.buildConstant(AmtRegEltTy.changeElementSize(64), Amount);
Observer.changingInstr(MI);
MI.getOperand(2).setReg(ExtCst.getReg(0));
Observer.changedInstr(MI);
@@ -2230,7 +2234,7 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
"Expected src and dst to have the same type!");
if (ST->hasCSSC() && Ty.isScalar() && Size == 128) {
- LLT s64 = LLT::scalar(64);
+ LLT s64 = Ty.changeElementSize(64);
auto Split = MIRBuilder.buildUnmerge(s64, Val);
auto CTPOP1 = MIRBuilder.buildCTPOP(s64, Split->getOperand(0));
@@ -2253,11 +2257,13 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
// Pre-conditioning: widen Val up to the nearest vector type.
// s32,s64,v4s16,v2s32 -> v8i8
// v8s16,v4s32,v2s64 -> v16i8
- LLT VTy = Size == 128 ? LLT::fixed_vector(16, 8) : LLT::fixed_vector(8, 8);
+ LLT ScalarTy = Ty.getScalarType();
+ LLT VTy = Size == 128 ? LLT::fixed_vector(16, ScalarTy.changeElementSize(8))
+ : LLT::fixed_vector(8, ScalarTy.changeElementSize(8));
if (Ty.isScalar()) {
assert((Size == 32 || Size == 64 || Size == 128) && "Expected only 32, 64, or 128 bit scalars!");
if (Size == 32) {
- Val = MIRBuilder.buildZExt(LLT::scalar(64), Val).getReg(0);
+ Val = MIRBuilder.buildZExt(ScalarTy.changeElementSize(64), Val).getReg(0);
}
}
Val = MIRBuilder.buildBitcast(VTy, Val).getReg(0);
@@ -2266,15 +2272,16 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
auto CTPOP = MIRBuilder.buildCTPOP(VTy, Val);
// Sum across lanes.
-
if (ST->hasDotProd() && Ty.isVector() && Ty.getNumElements() >= 2 &&
Ty.getScalarSizeInBits() != 16) {
- LLT Dt = Ty == LLT::fixed_vector(2, 64) ? LLT::fixed_vector(4, 32) : Ty;
+ LLT Dt = Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))
+ ? LLT::fixed_vector(4, ScalarTy.changeElementSize(32))
+ : Ty;
auto Zeros = MIRBuilder.buildConstant(Dt, 0);
auto Ones = MIRBuilder.buildConstant(VTy, 1);
MachineInstrBuilder Sum;
- if (Ty == LLT::fixed_vector(2, 64)) {
+ if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))) {
auto UDOT =
MIRBuilder.buildInstr(AArch64::G_UDOT, {Dt}, {Zeros, Ones, CTPOP});
Sum = MIRBuilder.buildInstr(AArch64::G_UADDLP, {Ty}, {UDOT});
@@ -2296,26 +2303,26 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
SmallVector<LLT> HAddTys;
if (Ty.isScalar()) {
Opc = Intrinsic::aarch64_neon_uaddlv;
- HAddTys.push_back(LLT::scalar(32));
- } else if (Ty == LLT::fixed_vector(8, 16)) {
+ HAddTys.push_back(ScalarTy.changeElementSize(32));
+ } else if (Ty == LLT::fixed_vector(8, ScalarTy.changeElementSize(16))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, 16));
- } else if (Ty == LLT::fixed_vector(4, 32)) {
+ HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
+ } else if (Ty == LLT::fixed_vector(4, ScalarTy.changeElementSize(32))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, 16));
- HAddTys.push_back(LLT::fixed_vector(4, 32));
- } else if (Ty == LLT::fixed_vector(2, 64)) {
+ HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
+ HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(32)));
+ } else if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, 16));
- HAddTys.push_back(LLT::fixed_vector(4, 32));
- HAddTys.push_back(LLT::fixed_vector(2, 64));
- } else if (Ty == LLT::fixed_vector(4, 16)) {
+ HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
+ HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(32)));
+ HAddTys.push_back(LLT::fixed_vector(2, ScalarTy.changeElementSize(64)));
+ } else if (Ty == LLT::fixed_vector(4, ScalarTy.changeElementSize(16))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(4, 16));
- } else if (Ty == LLT::fixed_vector(2, 32)) {
+ HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(16)));
+ } else if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(32))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(4, 16));
- HAddTys.push_back(LLT::fixed_vector(2, 32));
+ HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(16)));
+ HAddTys.push_back(LLT::fixed_vector(2, ScalarTy.changeElementSize(32)));
} else
llvm_unreachable("unexpected vector shape");
MachineInstrBuilder UADD;
@@ -2336,12 +2343,12 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
- LLT s64 = LLT::scalar(64);
+ LLT i64 = LLT::integer(64);
auto Addr = MI.getOperand(1).getReg();
- auto DesiredI = MIRBuilder.buildUnmerge({s64, s64}, MI.getOperand(2));
- auto NewI = MIRBuilder.buildUnmerge({s64, s64}, MI.getOperand(3));
- auto DstLo = MRI.createGenericVirtualRegister(s64);
- auto DstHi = MRI.createGenericVirtualRegister(s64);
+ auto DesiredI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(2));
+ auto NewI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(3));
+ auto DstLo = MRI.createGenericVirtualRegister(i64);
+ auto DstHi = MRI.createGenericVirtualRegister(i64);
MachineInstrBuilder CAS;
if (ST->hasLSE()) {
@@ -2544,14 +2551,11 @@ bool AArch64LegalizerInfo::legalizeFptrunc(MachineInstr &MI,
assert(SrcTy.isFixedVector() && isPowerOf2_32(SrcTy.getNumElements()) &&
"Expected a power of 2 elements");
- LLT s16 = LLT::scalar(16);
- LLT s32 = LLT::scalar(32);
- LLT s64 = LLT::scalar(64);
- LLT v2s16 = LLT::fixed_vector(2, s16);
- LLT v4s16 = LLT::fixed_vector(4, s16);
- LLT v2s32 = LLT::fixed_vector(2, s32);
- LLT v4s32 = LLT::fixed_vector(4, s32);
- LLT v2s64 = LLT::fixed_vector(2, s64);
+ LLT v2s16 = DstTy.changeElementCount(2);
+ LLT v4s16 = DstTy.changeElementCount(4);
+ LLT v2s32 = SrcTy.changeElementCount(2).changeElementSize(32);
+ LLT v4s32 = SrcTy.changeElementCount(4).changeElementSize(32);
+ LLT v2s64 = SrcTy.changeElementCount(2);
SmallVector<Register> RegsToUnmergeTo;
SmallVector<Register> TruncOddDstRegs;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index fa7bb6ecc35ee..7275b60bbed9d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -223,7 +223,7 @@ bool matchAArch64MulConstCombine(
return false;
ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
- auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt);
+ auto Shift = B.buildConstant(LLT::integer(64), ShiftAmt);
auto ShiftedVal = B.buildShl(Ty, LHS, Shift);
Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS;
@@ -238,7 +238,8 @@ bool matchAArch64MulConstCombine(
}
// Shift the result.
if (TrailingZeroes) {
- B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes));
+ B.buildShl(DstReg, Res,
+ B.buildConstant(LLT::integer(64), TrailingZeroes));
return;
}
B.buildCopy(DstReg, Res.getReg(0));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 221a7bcd881bb..b656f2a3d87ca 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -543,9 +543,9 @@ void applyINS(MachineInstr &MI, MachineRegisterInfo &MRI,
Register DstVec, SrcVec;
int DstLane, SrcLane;
std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo;
- auto SrcCst = Builder.buildConstant(LLT::scalar(64), SrcLane);
+ auto SrcCst = Builder.buildConstant(LLT::integer(64), SrcLane);
auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst);
- auto DstCst = Builder.buildConstant(LLT::scalar(64), DstLane);
+ auto DstCst = Builder.buildConstant(LLT::integer(64), DstLane);
Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst);
MI.eraseFromParent();
}
@@ -958,7 +958,9 @@ void applySwapICmpOperands(MachineInstr &MI, GISelChangeObserver &Observer) {
std::function<Register(MachineIRBuilder &)>
getVectorFCMP(AArch64CC::CondCode CC, Register LHS, Register RHS, bool NoNans,
MachineRegisterInfo &MRI) {
- LLT DstTy = MRI.getType(LHS);
+ LLT OldTy = MRI.getType(LHS);
+ LLT DstTy =
+ LLT::fixed_vector(OldTy.getNumElements(), OldTy.getScalarSizeInBits());
assert(DstTy.isVector() && "Expected vector types only?");
assert(DstTy == MRI.getType(RHS) && "Src and Dst types must match!");
switch (CC) {
@@ -1090,7 +1092,7 @@ void applyLowerBuildToInsertVecElt(MachineInstr &MI, MachineRegisterInfo &MRI,
Register SrcReg = GBuildVec->getSourceReg(I);
if (mi_match(SrcReg, MRI, m_GImplicitDef()))
continue;
- auto IdxReg = B.buildConstant(LLT::scalar(64), I);
+ auto IdxReg = B.buildConstant(LLT::integer(64), I);
DstReg =
B.buildInsertVectorElement(DstTy, DstReg, SrcReg, IdxReg).getReg(0);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 29538d0f9ba1b..4d973ed572307 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -474,11 +474,14 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
LLT LeftoverTy;
SmallVector<Register, 4> LeftoverRegs;
if (SrcScalSize == 8)
- MainTy = LLT::fixed_vector(16, 8);
+ MainTy =
+ LLT::fixed_vector(16, SrcTy.getScalarType().changeElementSize(8));
else if (SrcScalSize == 16)
- MainTy = LLT::fixed_vector(8, 16);
+ MainTy =
+ LLT::fixed_vector(8, SrcTy.getScalarType().changeElementSize(16));
else if (SrcScalSize == 32)
- MainTy = LLT::fixed_vector(4, 32);
+ MainTy =
+ LLT::fixed_vector(4, SrcTy.getScalarType().changeElementSize(32));
else
llvm_unreachable("Source's Scalar Size not supported");
@@ -493,8 +496,9 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
}
unsigned MidScalarSize = MainTy.getScalarSizeInBits() * 2;
- LLT MidScalarLLT = LLT::scalar(MidScalarSize);
- Register ZeroReg = B.buildConstant(LLT::scalar(64), 0).getReg(0);
+ LLT MidScalarLLT =
+ MainTy.changeElementSize(MidScalarSize).changeElementCount(1);
+ Register ZeroReg = B.buildConstant(LLT::integer(64), 0).getReg(0);
for (unsigned I = 0; I < WorkingRegisters.size(); I++) {
// If the number of elements is too small to build an instruction, extend
// its size before applying addlv
@@ -510,8 +514,9 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
// Generate the {U/S}ADDLV instruction, whose output is always double of the
// Src's Scalar size
- LLT AddlvTy = MidScalarSize <= 32 ? LLT::fixed_vector(4, 32)
- : LLT::fixed_vector(2, 64);
+ LLT AddlvTy = MidScalarSize <= 32
+ ? MainTy.changeElementSize(32).changeElementCount(4)
+ : MainTy.changeElementSize(64).changeElementCount(2);
Register AddlvReg =
B.buildInstr(Opc, {AddlvTy}, {WorkingRegisters[I]}).getReg(0);
@@ -525,9 +530,10 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
{MidScalarLLT}, {AddlvReg, ZeroReg})
.getReg(0);
} else {
- Register ExtractReg = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT,
- {LLT::scalar(32)}, {AddlvReg, ZeroReg})
- .getReg(0);
+ Register ExtractReg =
+ B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT,
+ {DstTy.changeElementSize(32)}, {AddlvReg, ZeroReg})
+ .getReg(0);
WorkingRegisters[I] =
B.buildTrunc({MidScalarLLT}, {ExtractReg}).getReg(0);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index c5885b53b513b..963f6d32530bd 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -375,7 +375,9 @@ void AArch64RegisterBankInfo::applyMappingImpl(
case TargetOpcode::G_INSERT_VECTOR_ELT: {
// Extend smaller gpr operands to 32 bit.
Builder.setInsertPt(*MI.getParent(), MI.getIterator());
- auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg());
+ LLT OperandType = MRI.getType(MI.getOperand(2).getReg());
+ auto Ext = Builder.buildAnyExt(OperandType.changeElementSize(32),
+ MI.getOperand(2).getReg());
MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID));
MI.getOperand(2).setReg(Ext.getReg(0));
return applyDefaultMapping(OpdMapper);
>From f60c2c9d07184a976a453e20b741cab01637b0a2 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 15:59:40 +0000
Subject: [PATCH 34/41] Add bitcasts & copies to coerce types when necessary.
Allow select functions to 'see through' bitcasts to allow existing
optimisations to work. Additionally improve the register selection for
bitcasts.
---
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 23 ++++-
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 19 +++-
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 92 ++++++++++++++++---
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 24 ++++-
llvm/lib/CodeGen/MachineVerifier.cpp | 11 ++-
.../GISel/AArch64InstructionSelector.cpp | 9 ++
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 17 +++-
7 files changed, 168 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index a62973965564f..421050409f125 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -340,13 +340,25 @@ mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
if (LCMTy == LLTy) {
// Common case where no padding is needed.
assert(DstRegs.size() == 1);
- return B.buildConcatVectors(DstRegs[0], SrcRegs);
+
+ SmallVector<Register, 8> ConcatRegs(SrcRegs.size());
+ llvm::copy(SrcRegs, ConcatRegs.begin());
+
+ if (LLTy.getScalarType() != PartLLT.getScalarType())
+ for (int I = 0; I != SrcRegs.size(); ++I)
+ ConcatRegs[I] =
+ B.buildBitcast(MRI.getType(SrcRegs[I])
+ .changeElementType(LLTy.getScalarType()),
+ SrcRegs[I])
+ .getReg(0);
+
+ return B.buildConcatVectors(DstRegs[0], ConcatRegs);
}
// We need to create an unmerge to the result registers, which may require
// widening the original value.
Register UnmergeSrcReg;
- if (LCMTy != PartLLT) {
+ if (LCMTy.getSizeInBits() != PartLLT.getSizeInBits()) {
assert(DstRegs.size() == 1);
return B.buildDeleteTrailingVectorElements(
DstRegs[0], B.buildMergeLikeInstr(LCMTy, SrcRegs));
@@ -366,6 +378,9 @@ mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
for (int I = DstRegs.size(); I != NumDst; ++I)
PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);
+ if (PartLLT != LCMTy)
+ UnmergeSrcReg = B.buildBitcast(LCMTy, UnmergeSrcReg).getReg(0);
+
if (PadDstRegs.size() == 1)
return B.buildDeleteTrailingVectorElements(DstRegs[0], UnmergeSrcReg);
return B.buildUnmerge(PadDstRegs, UnmergeSrcReg);
@@ -456,7 +471,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
PartLLT = NewTy;
}
- if (LLTy.getScalarType() == PartLLT.getElementType()) {
+ if (LLTy.getScalarSizeInBits() == PartLLT.getScalarSizeInBits()) {
mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
} else {
unsigned I = 0;
@@ -1391,7 +1406,7 @@ static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) {
void CallLowering::IncomingValueHandler::assignValueToReg(
Register ValVReg, Register PhysReg, const CCValAssign &VA) {
const MVT LocVT = VA.getLocVT();
- const LLT LocTy(LocVT);
+ const LLT LocTy = getLLTForMVT(LocVT);
const LLT RegTy = MRI.getType(ValVReg);
if (isCopyCompatibleType(RegTy, LocTy)) {
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index c58969144dc2b..ac5b164b7ce16 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2330,9 +2330,22 @@ void CombinerHelper::applyCombineUnmergeConstant(
assert((MI.getNumOperands() - 1 == Csts.size()) &&
"Not enough operands to replace all defs");
unsigned NumElems = MI.getNumOperands() - 1;
- for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
- Register DstReg = MI.getOperand(Idx).getReg();
- Builder.buildConstant(DstReg, Csts[Idx]);
+
+ Register SrcReg = MI.getOperand(NumElems).getReg();
+
+ if (MRI.getType(SrcReg).isFloat()) {
+ APFloat Val(getFltSemanticForLLT(MRI.getType(MI.getOperand(0).getReg())));
+
+ for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
+ Register DstReg = MI.getOperand(Idx).getReg();
+ Val.convertFromAPInt(Csts[Idx], false, detail::rmTowardZero);
+ Builder.buildFConstant(DstReg, Val);
+ }
+ } else {
+ for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
+ Register DstReg = MI.getOperand(Idx).getReg();
+ Builder.buildConstant(DstReg, Csts[Idx]);
+ }
}
MI.eraseFromParent();
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 5ec47ca632903..6f3d1f52c6f69 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4586,12 +4586,30 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return Legalized;
}
case TargetOpcode::G_FNEG: {
- auto [Res, SubByReg] = MI.getFirst2Regs();
- LLT Ty = MRI.getType(Res);
+ auto [Res, ResTy, SubByReg, SubByRegTy] = MI.getFirst2RegLLTs();
+ LLT TyInt =
+ ResTy.changeElementType(LLT::integer(ResTy.getScalarSizeInBits()));
+ Register castedSubByReg = SubByReg;
+
+ if (!(SubByRegTy.getScalarType().isAnyScalar() ||
+ SubByRegTy.getScalarType().isInteger()))
+ castedSubByReg =
+ MIRBuilder
+ .buildBitcast(SubByRegTy.changeElementType(
+ LLT::integer(SubByRegTy.getScalarSizeInBits())),
+ SubByReg)
+ .getReg(0);
auto SignMask = MIRBuilder.buildConstant(
- Ty, APInt::getSignMask(Ty.getScalarSizeInBits()));
- MIRBuilder.buildXor(Res, SubByReg, SignMask);
+ TyInt, APInt::getSignMask(TyInt.getScalarSizeInBits()));
+
+ if (ResTy != TyInt) {
+ Register NewDst =
+ MIRBuilder.buildXor(TyInt, castedSubByReg, SignMask).getReg(0);
+ MIRBuilder.buildBitcast(Res, NewDst);
+ } else
+ MIRBuilder.buildXor(Res, castedSubByReg, SignMask).getReg(0);
+
MI.eraseFromParent();
return Legalized;
}
@@ -8782,7 +8800,12 @@ LegalizerHelper::lowerFCopySign(MachineInstr &MI) {
// We masked the sign bit and the not-sign bit, so these are disjoint.
Flags |= MachineInstr::Disjoint;
- MIRBuilder.buildOr(Dst, And0, And1, Flags);
+ if (DstTy == DstIntTy)
+ MIRBuilder.buildOr(Dst, And0, And1, Flags).getReg(0);
+ else {
+ Register NewDst = MIRBuilder.buildOr(DstIntTy, And0, And1, Flags).getReg(0);
+ MIRBuilder.buildBitcast(Dst, NewDst);
+ }
MI.eraseFromParent();
return Legalized;
@@ -10072,6 +10095,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] =
MI.getFirst4RegLLTs();
+ LLT Op1TyInt =
+ Op1Ty.changeElementType(LLT::integer(Op1Ty.getScalarSizeInBits()));
+
bool IsEltPtr = DstTy.isPointerOrPointerVector();
if (IsEltPtr) {
LLT ScalarPtrTy = LLT::scalar(DstTy.getScalarSizeInBits());
@@ -10112,6 +10138,18 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
return UnableToLegalize;
}
+ if (!(Op1Ty.getScalarType().isAnyScalar() ||
+ Op1Ty.getScalarType().isInteger()))
+ Op1Reg = MIRBuilder.buildBitcast(Op1TyInt, Op1Reg).getReg(0);
+
+ if (!(Op2Ty.getScalarType().isAnyScalar() ||
+ Op2Ty.getScalarType().isInteger()))
+ Op2Reg = MIRBuilder
+ .buildBitcast(Op2Ty.changeElementType(
+ LLT::integer(Op2Ty.getScalarSizeInBits())),
+ Op2Reg)
+ .getReg(0);
+
auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg);
auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg);
auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask);
@@ -10119,7 +10157,12 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
auto Or = MIRBuilder.buildOr(DstTy, NewOp1, NewOp2);
MIRBuilder.buildIntToPtr(DstReg, Or);
} else {
- MIRBuilder.buildOr(DstReg, NewOp1, NewOp2);
+ if (DstTy == Op1TyInt)
+ MIRBuilder.buildOr(DstReg, NewOp1, NewOp2);
+ else {
+ auto Or = MIRBuilder.buildOr(Op1TyInt, NewOp1, NewOp2);
+ MIRBuilder.buildBitcast(DstReg, Or.getReg(0));
+ }
}
MI.eraseFromParent();
return Legalized;
@@ -10235,16 +10278,37 @@ LegalizerHelper::lowerAbsDiffToMinMax(MachineInstr &MI) {
}
LegalizerHelper::LegalizeResult LegalizerHelper::lowerFAbs(MachineInstr &MI) {
- Register SrcReg = MI.getOperand(1).getReg();
- Register DstReg = MI.getOperand(0).getReg();
+ auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
+ LLT TyInt =
+ DstTy.changeElementType(LLT::integer(DstTy.getScalarSizeInBits()));
+ Register castedSrc = SrcReg;
+
+ if (!(SrcTy.getScalarType().isAnyScalar() ||
+ SrcTy.getScalarType().isInteger()))
+ castedSrc = MIRBuilder
+ .buildBitcast(SrcTy.changeElementType(LLT::integer(
+ SrcTy.getScalarSizeInBits())),
+ SrcReg)
+ .getReg(0);
- LLT Ty = MRI.getType(DstReg);
+ if (MRI.getType(DstReg) != TyInt) {
+ // Reset sign bit
+ Register NewDst =
+ MIRBuilder
+ .buildAnd(
+ TyInt, castedSrc,
+ MIRBuilder.buildConstant(
+ TyInt, APInt::getSignedMaxValue(DstTy.getScalarSizeInBits())))
+ .getReg(0);
- // Reset sign bit
- MIRBuilder.buildAnd(
- DstReg, SrcReg,
- MIRBuilder.buildConstant(
- Ty, APInt::getSignedMaxValue(Ty.getScalarSizeInBits())));
+ MIRBuilder.buildBitcast(DstReg, NewDst);
+ } else
+ MIRBuilder
+ .buildAnd(
+ DstReg, castedSrc,
+ MIRBuilder.buildConstant(
+ TyInt, APInt::getSignedMaxValue(DstTy.getScalarSizeInBits())))
+ .getReg(0);
MI.eraseFromParent();
return Legalized;
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 35e89cae9e929..cc1418f49b549 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -796,15 +796,35 @@ llvm::ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
return std::nullopt;
}
+static GBuildVector *getBuildVectorLikeDef(Register Reg,
+ const MachineRegisterInfo &MRI) {
+ if (auto *BV = getOpcodeDef<GBuildVector>(Reg, MRI))
+ return BV;
+
+ auto *Bitcast = getOpcodeDef(TargetOpcode::G_BITCAST, Reg, MRI);
+ if (!Bitcast)
+ return nullptr;
+
+ auto [Dst, DstTy, Src, SrcTy] = Bitcast->getFirst2RegLLTs();
+ if (!SrcTy.isVector() || !DstTy.isVector())
+ return nullptr;
+ if (SrcTy.getElementCount() != DstTy.getElementCount())
+ return nullptr;
+ if (SrcTy.getScalarSizeInBits() != DstTy.getScalarSizeInBits())
+ return nullptr;
+
+ return getOpcodeDef<GBuildVector>(Src, MRI);
+}
+
SmallVector<APInt>
llvm::ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
const Register Op2,
const MachineRegisterInfo &MRI) {
- auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI);
+ auto *SrcVec2 = getBuildVectorLikeDef(Op2, MRI);
if (!SrcVec2)
return SmallVector<APInt>();
- auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI);
+ auto *SrcVec1 = getBuildVectorLikeDef(Op1, MRI);
if (!SrcVec1)
return SmallVector<APInt>();
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 5ce7606b051a5..0145c24a19f95 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1338,7 +1338,16 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
report("bitcast sizes must match", MI);
- if (SrcTy == DstTy)
+ bool SameType = SrcTy.getKind() == DstTy.getKind();
+ if (SameType && SrcTy.isPointerOrPointerVector())
+ SameType &= SrcTy.getAddressSpace() == DstTy.getAddressSpace();
+
+ SameType &= SrcTy.getScalarSizeInBits() == DstTy.getScalarSizeInBits();
+
+ if (SameType && SrcTy.isVector())
+ SameType &= SrcTy.getElementCount() == DstTy.getElementCount();
+
+ if (SameType)
report("bitcast must change the type", MI);
break;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 9809675a6995a..b8059b111a8bc 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2196,6 +2196,15 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
return false;
if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) {
+ // Need to add a copy to change the type so that the existing patterns can
+ // match when there is an integer on an FPR bank.
+ if (SrcTy.getScalarType().isInteger()) {
+ auto Copy = MIB.buildCopy(DstTy, SrcReg);
+ I.getOperand(1).setReg(Copy.getReg(0));
+ MRI.setRegClass(Copy.getReg(0),
+ getRegClassForTypeOnBank(
+ SrcTy, RBI.getRegBank(AArch64::FPRRegBankID)));
+ }
if (I.getOpcode() == TargetOpcode::G_SITOFP)
I.setDesc(TII.get(AArch64::G_SITOF));
else
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 963f6d32530bd..507f4d044c396 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -569,6 +569,13 @@ bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
const AArch64RegisterInfo &TRI,
unsigned Depth) const {
switch (MI.getOpcode()) {
+ case TargetOpcode::G_BITCAST: {
+ Register SrcReg = MI.getOperand(1).getReg();
+ if (const MachineInstr *Def = MRI.getVRegDef(SrcReg))
+ return onlyUsesFP(*Def, MRI, TRI, Depth + 1);
+ return false;
+ }
+
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_FPTOSI_SAT:
@@ -783,8 +790,12 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
TypeSize Size = DstTy.getSizeInBits();
- bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64;
- bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;
+ bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64 &&
+ DstTy.getScalarType().isInteger() &&
+ !(SrcTy.getSizeInBits() <= 16);
+ bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64 &&
+ SrcTy.getScalarType().isInteger() &&
+ !(SrcTy.getSizeInBits() <= 16);
const RegisterBank &DstRB =
DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
const RegisterBank &SrcRB =
@@ -1101,7 +1112,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
OpRegBankIdx[2] = PMI_FirstFPR;
else {
- // If the type is i8/i16, and the regank will be GPR, then we change the
+ // If the type is i8/i16, and the regbank will be GPR, then we change the
// type to i32 in applyMappingImpl.
LLT Ty = MRI.getType(MI.getOperand(2).getReg());
if (Ty.getSizeInBits() == 8 || Ty.getSizeInBits() == 16) {
>From 7617dd01bc9dd53b22de76cb16ecc0ebd9293afa Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 16:01:16 +0000
Subject: [PATCH 35/41] Make floating point types legal, bf16 legal & convert
from bf16 when necessary.
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 74 ++++++++++++++-----
1 file changed, 57 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 1e663342527d8..c841d37428120 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -65,6 +65,23 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
const LLT nxv4s32 = LLT::scalable_vector(4, s32);
const LLT nxv2s64 = LLT::scalable_vector(2, s64);
+ const LLT bf16 = LLT::bfloat16();
+ const LLT v4bf16 = LLT::fixed_vector(4, bf16);
+ const LLT v8bf16 = LLT::fixed_vector(8, bf16);
+
+ const LLT fp16 = LLT::float16();
+ const LLT v4fp16 = LLT::fixed_vector(4, fp16);
+ const LLT v8fp16 = LLT::fixed_vector(8, fp16);
+
+ const LLT fp32 = LLT::float32();
+ const LLT v2fp32 = LLT::fixed_vector(2, fp32);
+ const LLT v4fp32 = LLT::fixed_vector(4, fp32);
+
+ const LLT fp64 = LLT::float64();
+ const LLT v2fp64 = LLT::fixed_vector(2, fp64);
+
+ const LLT fp128 = LLT::float128();
+
std::initializer_list<LLT> PackedVectorAllTypeList = {/* Begin 128bit types */
v16s8, v8s16, v4s32,
v2s64, v2p0,
@@ -86,7 +103,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Some instructions only support s16 if the subtarget has full 16-bit FP
// support.
const bool HasFP16 = ST.hasFullFP16();
- const LLT &MinFPScalar = HasFP16 ? s16 : s32;
+ const LLT &MinFPScalar = HasFP16 ? fp16 : fp32;
+
+ const bool HasBF16 = ST.hasBF16();
const bool HasCSSC = ST.hasCSSC();
const bool HasRCPC3 = ST.hasRCPC3();
@@ -97,6 +116,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor({p0, s8, s16, s32, s64})
.legalFor({v2s8, v4s8, v8s8, v16s8, v2s16, v4s16, v8s16, v2s32, v4s32,
v2s64, v2p0})
+ .legalFor(HasBF16, {bf16})
+ .legalFor(HasBF16, {v4bf16})
.widenScalarToNextPow2(0)
.clampScalar(0, s8, s64)
.moreElementsToNextPow2(0)
@@ -406,9 +427,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT, G_FMAXNUM, G_FMINNUM,
G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR, G_FRINT, G_FNEARBYINT,
G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
- .legalFor({s32, s64, v2s32, v4s32, v2s64})
- .legalFor(HasFP16, {s16, v4s16, v8s16})
- .libcallFor({s128})
+ .legalFor({fp32, fp64, v2fp32, v4fp32, v2fp64})
+ .convertBF16(HasBF16)
+ .legalFor(HasFP16, {fp16, s16, v4s16, v8s16})
+ .libcallFor({fp128})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.minScalarOrElt(0, MinFPScalar)
.clampNumElements(0, v4s16, v8s16)
@@ -417,19 +439,20 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0);
getActionDefinitionsBuilder({G_FABS, G_FNEG})
- .legalFor({s32, s64, v2s32, v4s32, v2s64})
- .legalFor(HasFP16, {s16, v4s16, v8s16})
+ .legalFor({fp32, fp64, v2fp32, v4fp32, v2fp64})
+ .legalFor(HasFP16, {fp16, v4fp16, v8fp16})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.lowerIf(scalarOrEltWiderThan(0, 64))
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.moreElementsToNextPow2(0)
- .lowerFor({s16, v4s16, v8s16});
+ .lowerFor({fp16, v4fp16, v8fp16});
getActionDefinitionsBuilder(G_FREM)
- .libcallFor({s32, s64, s128})
- .minScalar(0, s32)
+ .libcallFor({fp32, fp64, fp128})
+ .convertBF16(HasBF16)
+ .minScalar(0, fp32)
.scalarize(0);
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2,
@@ -438,12 +461,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
G_FSINH, G_FTANH, G_FMODF})
// We need a call for these, so we always need to scalarize.
.scalarize(0)
+ .convertBF16(HasBF16)
// Regardless of FP16 support, widen 16-bit elements to 32-bits.
- .minScalar(0, s32)
- .libcallFor({s32, s64, s128});
+ .minScalar(0, fp32)
+ .libcallFor({fp32, fp64, fp128});
getActionDefinitionsBuilder({G_FPOWI, G_FLDEXP})
.scalarize(0)
- .minScalar(0, s32)
+ .convertBF16(HasBF16)
+ .minScalar(0, fp32)
.libcallFor({{s32, s32}, {s64, s32}, {s128, s32}});
getActionDefinitionsBuilder({G_LROUND, G_INTRINSIC_LRINT})
@@ -689,7 +714,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampScalar(0, s8, s64);
getActionDefinitionsBuilder(G_FCONSTANT)
// Always legalize s16 to prevent G_FCONSTANT being widened to G_CONSTANT
- .legalFor({s16, s32, s64, s128})
+ .legalFor({s16, s32, s64, s128, bf16, fp16, fp32, fp64, fp128})
.clampScalar(0, MinFPScalar, s128);
// FIXME: fix moreElementsToNextPow2
@@ -731,6 +756,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v2s64, v2s64}})
.legalFor(HasFP16, {{s32, s16}, {v4s16, v4s16}, {v8s16, v8s16}})
.widenScalarOrEltToNextPow2(1)
+ .convertBF16(HasBF16, 1)
.clampScalar(0, s32, s32)
.minScalarOrElt(1, MinFPScalar)
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
@@ -826,6 +852,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor(
{{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
+ .legalFor(HasBF16, {{bf16, fp32}, {bf16, fp64}, {v4bf16, v4fp32}})
.libcallFor({{s16, s128}, {s32, s128}, {s64, s128}})
.moreElementsToNextPow2(1)
.customIf([](const LegalityQuery &Q) {
@@ -841,8 +868,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.scalarize(0);
getActionDefinitionsBuilder(G_FPEXT)
- .legalFor(
- {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
+ .legalFor({{fp32, fp16},
+ {fp64, fp16},
+ {fp64, fp32},
+ {v4fp32, v4fp16},
+ {v2fp64, v2fp32}})
+ .legalFor(HasBF16, {{fp32, bf16}, {v4fp32, v4bf16}})
.libcallFor({{s128, s64}, {s128, s32}, {s128, s16}})
.moreElementsToNextPow2(0)
.widenScalarIf(
@@ -853,9 +884,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
SrcTy.getScalarSizeInBits() == 16 &&
DstTy.getScalarSizeInBits() == 64;
},
- changeElementTo(1, s32))
+ changeElementTo(1, fp32))
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
+ // bf16 -> fp32
+ .convertBF16(HasBF16, 1)
.scalarize(0);
// Conversions
@@ -955,13 +988,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v2s32, v2s32},
{v4s32, v4s32},
{v2s64, v2s64}})
+ .convertBF16(HasBF16)
.legalFor(HasFP16,
{{s16, s32}, {s16, s64}, {v4s16, v4s16}, {v8s16, v8s16}})
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.moreElementsToNextPow2(1)
.widenScalarOrEltToNextPow2OrMinSize(1)
- .minScalar(1, s32)
+ .minScalar(1, fp32)
.lowerIf([](const LegalityQuery &Query) {
return Query.Types[1].isVector() &&
Query.Types[1].getScalarSizeInBits() == 64 &&
@@ -1042,6 +1076,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Casts for 32 and 64-bit width type are just copies.
// Same for 128-bit width type, except they are on the FPR bank.
getActionDefinitionsBuilder(G_BITCAST)
+ .legalForCartesianProduct({s16})
// Keeping 32-bit instructions legal to prevent regression in some tests
.legalForCartesianProduct({s32, v2s16, v4s8})
.legalForCartesianProduct({s64, v8s8, v4s16, v2s32})
@@ -1060,6 +1095,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v8s8, v16s8)
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
+ .clampMaxNumElements(0, s64, 2)
.lower();
getActionDefinitionsBuilder(G_VASTART).legalFor({p0});
@@ -1137,6 +1173,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{s16, nxv8s16, s64},
{s32, nxv4s32, s64},
{s64, nxv2s64, s64}})
+ .legalFor(HasBF16, {{bf16, v8bf16, s64}, {bf16, v4bf16, s64}})
.unsupportedIf([=](const LegalityQuery &Query) {
const LLT &EltTy = Query.Types[1].getElementType();
if (Query.Types[1].isScalableVector())
@@ -1188,6 +1225,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
.legalIf(
typeInSet(0, {v8s8, v16s8, v4s16, v8s16, v2s32, v4s32, v2s64, v2p0}))
+ .legalFor(HasBF16, {{v4bf16}, {v8bf16}})
.legalFor(HasSVE, {{nxv16s8, s32, s64},
{nxv8s16, s32, s64},
{nxv4s32, s32, s64},
@@ -1210,6 +1248,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v4s32, s32},
{v2s64, s64},
{v2p0, p0}})
+ .legalFor(HasBF16, {{v4bf16, bf16}, {v8bf16, bf16}})
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.minScalarOrElt(0, s8)
@@ -1257,6 +1296,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_CONCAT_VECTORS)
.legalFor({{v16s8, v8s8}, {v8s16, v4s16}, {v4s32, v2s32}})
+ .legalFor(HasBF16, {{v8bf16, v4bf16}})
.bitcastIf(
[=](const LegalityQuery &Query) {
return Query.Types[0].isFixedVector() &&
>From 5fc0eaff958adca3bb1f387ca7dfe73094002afe Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 16:02:29 +0000
Subject: [PATCH 36/41] Add slightly modified patterns to allow selection of
instructions that used to select but no longer do
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 4 +
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 10 +++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 90 +++++++++++++++++--
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 10 +++
4 files changed, 108 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 75adaf6602caa..d1d49596547c1 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -171,6 +171,10 @@ def extract_high_v4f32 :
def extract_high_v2f64 :
ComplexPattern<v1f64, 1, "SelectExtractHigh", [extract_subvector, bitconvert]>;
+def gi_extract_high_v8bf16 :
+ GIComplexOperandMatcher<v4s16, "selectExtractHigh">,
+ GIComplexPatternEquiv<extract_high_v8bf16>;
+
def gi_extract_high_v8f16 :
GIComplexOperandMatcher<v4s16, "selectExtractHigh">,
GIComplexPatternEquiv<extract_high_v8f16>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 497306dabaa97..e70dfdc77639c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -553,10 +553,18 @@ let AddedComplexity = 19 in {
defm : VecStoreLane64_0Pat<am_indexed16, store, v4i16, i16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane64_0Pat<am_indexed32, store, v2i32, i32, ssub, uimm12s4, STRSui>;
+ defm : VecStoreLane64_0Pat<am_indexed16, store, v4f16, f16, hsub, uimm12s2, STRHui>;
+ defm : VecStoreLane64_0Pat<am_indexed32, store, v2f32, f32, ssub, uimm12s4, STRSui>;
+
defm : VecStoreULane64_0Pat<store, v4i16, i16, hsub, STURHi>;
defm : VecStoreULane64_0Pat<store, v2i32, i32, ssub, STURSi>;
defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane64_0Pat<ro32, store, v2i32, i32, ssub, STRSroW, STRSroX>;
+
+ defm : VecStoreULane64_0Pat<store, v4f16, f16, hsub, STURHi>;
+ defm : VecStoreULane64_0Pat<store, v2f32, f32, ssub, STURSi>;
+ defm : VecROStoreLane64_0Pat<ro16, store, v4f16, f16, hsub, STRHroW, STRHroX>;
+ defm : VecROStoreLane64_0Pat<ro32, store, v2f32, f32, ssub, STRSroW, STRSroX>;
}
def : Pat<(v8i8 (AArch64dup (i8 (load GPR64sp:$Rn)))),
@@ -575,3 +583,5 @@ def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
(LD1Rv2d GPR64sp:$Rn)>;
def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
(LD1Rv1d GPR64sp:$Rn)>;
+
+def : Pat<(f64 (bitconvert (i64 0))), (FMOVD0)>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 5a471824ef513..9b5606883469f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4366,6 +4366,9 @@ defm : LoadInsertPatterns<extloadi8, v16i8, v8i8, nxv16i8, i32,
defm : LoadInsertPatterns<extloadi16, v8i16, v4i16, nxv8i16, i32,
LDRHui, LDURHi, LDRHroW, LDRHroX,
ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
+defm : LoadInsertPatterns<load, v8i16, v4i16, nxv8i16, i16,
+ LDRHui, LDURHi, LDRHroW, LDRHroX,
+ ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
defm : LoadInsertPatterns<load, v4i32, v2i32, nxv4i32, i32,
LDRSui, LDURSi, LDRSroW, LDRSroX,
ro32, am_indexed32, am_unscaled32, uimm12s4, ssub>;
@@ -4644,6 +4647,15 @@ let Predicates = [UseSTRQro], AddedComplexity = 10 in {
(ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
ro_Xextend128:$extend)),
(STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
+
+ def : Pat<(store (v2i64 FPR128:$Rt),
+ (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
+ ro_Wextend128:$extend)),
+ (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>;
+ def : Pat<(store (v2i64 FPR128:$Rt),
+ (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
+ ro_Xextend128:$extend)),
+ (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
}
multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
@@ -4727,6 +4739,7 @@ multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
let AddedComplexity = 19 in {
defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, f16, hsub, STRHroW, STRHroX>;
+ defm : VecROStoreLane0Pat<ro16, store, v8i16, i16, f16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, f16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, i32, ssub, STRSroW, STRSroX>;
defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, i32, ssub, STRSroW, STRSroX>;
@@ -4883,6 +4896,7 @@ multiclass VecStoreLane0Pat<ComplexPattern UIAddrMode, SDPatternOperator storeop
let AddedComplexity = 19 in {
defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, f16, hsub, uimm12s2, STRHui>;
+ defm : VecStoreLane0Pat<am_indexed16, store, v8i16, i16, f16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, f16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, i32, ssub, uimm12s4, STRSui>;
defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, i32, ssub, uimm12s4, STRSui>;
@@ -5036,6 +5050,7 @@ multiclass VecStoreULane0Pat<SDPatternOperator StoreOp,
let AddedComplexity = 19 in {
defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, f16, hsub, STURHi>;
+ defm : VecStoreULane0Pat<store, v8i16, i16, f16, hsub, STURHi>;
defm : VecStoreULane0Pat<store, v8f16, f16, f16, hsub, STURHi>;
defm : VecStoreULane0Pat<store, v4i32, i32, i32, ssub, STURSi>;
defm : VecStoreULane0Pat<store, v4f32, f32, i32, ssub, STURSi>;
@@ -7652,6 +7667,31 @@ def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
+def : Pat<(v4i32 (AArch64dup (i32 FPR32:$src))),
+ (v4i32 (DUPv4i32lane
+ (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$src, ssub),
+ (i64 0)))>;
+
+def : Pat<(v2i64 (AArch64dup (i64 FPR64:$Rn))),
+ (v2i64 (DUPv2i64lane
+ (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
+ (i64 0)))>;
+
+def : Pat<(v2i32 (AArch64dup (i32 FPR32:$Rn))),
+ (v2i32 (DUPv2i32lane
+ (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
+ (i64 0)))>;
+
+def : Pat<(v4i16 (AArch64dup (i16 FPR16:$Rn))),
+ (v4i16 (DUPv4i16lane
+ (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
+ (i64 0)))>;
+
+def : Pat<(v8i16 (AArch64dup (i16 FPR16:$Rn))),
+ (v8i16 (DUPv8i16lane
+ (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
+ (i64 0)))>;
+
// DUP from a 64-bit register to a 64-bit register is just a copy
def : Pat<(v1i64 (AArch64dup (i64 GPR64:$Rn))),
(COPY_TO_REGCLASS GPR64:$Rn, FPR64)>;
@@ -7817,6 +7857,11 @@ def : Pat<(v4i32 (vec_ins_or_scal_vec GPR32:$Rn)),
def : Pat<(v2i64 (vec_ins_or_scal_vec GPR64:$Rn)),
(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GPR64:$Rn, dsub)>;
+def : Pat<(v2i32 (vec_ins_or_scal_vec i32:$Rn)),
+ (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>;
+def : Pat<(v2i64 (vec_ins_or_scal_vec i64:$Rn)),
+ (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GPR64:$Rn, dsub)>;
+
def : Pat<(v4f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v8f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
@@ -7842,6 +7887,9 @@ def : Pat<(v4f32 (vec_ins_or_scal_vec (f32 FPR32:$Rn))),
def : Pat<(v2f32 (vec_ins_or_scal_vec (f32 FPR32:$Rn))),
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
+def : Pat<(v4i32 (vec_ins_or_scal_vec (i32 FPR32:$Rn))),
+ (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
+
def : Pat<(v2f64 (vec_ins_or_scal_vec (f64 FPR64:$Rn))),
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
@@ -7868,6 +7916,29 @@ def : Pat<(vector_insert v2f64:$Rn, (f64 fpimm0), (i64 VectorIndexD:$imm)),
(INSvi64gpr V128:$Rn, VectorIndexS:$imm, XZR)>;
}
+def : Pat<(v8i16 (vector_insert (v8i16 V128:$Rn),
+ (i16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
+ (INSvi16lane
+ V128:$Rn, VectorIndexH:$imm,
+ (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
+ (i64 0))>;
+
+def : Pat<(v4i16 (vector_insert (v4i16 V64:$Rn),
+ (i16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
+ (EXTRACT_SUBREG
+ (INSvi16lane
+ (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
+ VectorIndexH:$imm,
+ (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
+ (i64 0)),
+ dsub)>;
+
+def : Pat<(v4i16 (vector_insert (v4i16 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndexH:$imm))),
+ (EXTRACT_SUBREG
+ (INSvi16gpr (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
+ VectorIndexH:$imm, GPR32:$Rm),
+ dsub)>;
+
def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
(f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
(INSvi16lane
@@ -8032,21 +8103,24 @@ defm : Neon_INS_elt_pattern<v2f64, v1f64, nxv2f64, f64, VectorIndexD, INSvi6
// Accept i8 scalar argument in GlobalISel.
defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i8, VectorIndexB, INSvi8lane, DUPi8, bsub>;
defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i32, VectorIndexB, INSvi8lane, DUPi8, bsub>;
+defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i16, VectorIndexH, INSvi16lane, DUPi16, hsub>;
defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i32, VectorIndexH, INSvi16lane, DUPi16, hsub>;
defm : Neon_INS_elt_pattern<v4i32, v2i32, nxv4i32, i32, VectorIndexS, INSvi32lane, DUPi32, ssub>;
defm : Neon_INS_elt_pattern<v2i64, v1i64, nxv2i64, i64, VectorIndexD, INSvi64lane, DUPi64, dsub>;
// Insert from bitcast
-// vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
-def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
- (INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;
-def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
+// vector_insert(i32, n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
+def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 FPR32:$Sn), (i64 imm:$Immd))),
+ (INSvi32lane V128:$src, imm:$Immd,
+ (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;
+def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 FPR32:$Sn), (i64 imm:$Immd))),
(EXTRACT_SUBREG
(INSvi32lane (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$src, dsub)),
imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0),
dsub)>;
-def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), (i64 imm:$Immd))),
- (INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
+def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 FPR64:$Sn), (i64 imm:$Immd))),
+ (INSvi64lane V128:$src, imm:$Immd,
+ (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
// Patterns for i8/i16 -> v2i32/v4i16 lane moves via insert and extract that go via i32.
multiclass Neon_INS_elt_ext_pattern<ValueType VT128, ValueType VT64, ValueType OutVT,
@@ -9567,6 +9641,7 @@ class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
// Accept i8 scalar argument in GlobalISel.
def : Ld1Lane128Pat<load, VectorIndexB, v16i8, i8, LD1i8>;
def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
+def : Ld1Lane128Pat<load, VectorIndexH, v8i16, i16, LD1i16>;
def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
@@ -9642,6 +9717,7 @@ class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
// Accept i8 scalar argument in GlobalISel.
def : Ld1Lane64Pat<load, VectorIndexB, v8i8, i8, LD1i8>;
def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
+def : Ld1Lane64Pat<load, VectorIndexH, v4i16, i16, LD1i16>;
def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
@@ -9670,6 +9746,7 @@ class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
+def : St1Lane128Pat<store, VectorIndexH, v8i16, i16, ST1i16>;
def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
@@ -9688,6 +9765,7 @@ class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
+def : St1Lane64Pat<store, VectorIndexH, v4i16, i16, ST1i16>;
def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index d290d73fd0373..83a380cfb1fc0 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3554,6 +3554,14 @@ let Predicates = [HasSVE_or_SME] in {
def : Pat<(f64 (vector_extract nxv2f64:$vec, GPR64:$index)),
(LASTB_VPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>;
+ // LASTB_RPZ_* expect a GPR destination register, LASTB_VPZ_* expect FPR destination registers
+ def : Pat<(i16 (vector_extract nxv8i16:$vec, GPR64:$index)),
+ (LASTB_VPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>;
+ def : Pat<(i32 (vector_extract nxv4i32:$vec, GPR64:$index)),
+ (LASTB_VPZ_S (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>;
+ def : Pat<(i64 (vector_extract nxv2i64:$vec, GPR64:$index)),
+ (LASTB_VPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>;
+
// Extract element from vector with immediate index
def : Pat<(i32 (vector_extract nxv16i8:$vec, sve_elm_idx_extdup_b:$index)),
(EXTRACT_SUBREG (DUP_ZZI_B ZPR:$vec, sve_elm_idx_extdup_b:$index), ssub)>;
@@ -3650,6 +3658,8 @@ let Predicates = [HasSVE_or_SME] in {
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
def : Pat<(i32 (vector_extract nxv8i16:$Zs, (i64 0))),
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
+ def : Pat<(i16 (vector_extract nxv8i16:$Zs, (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
def : Pat<(i32 (vector_extract nxv4i32:$Zs, (i64 0))),
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
def : Pat<(i64 (vector_extract nxv2i64:$Zs, (i64 0))),
>From 3795feee4eb74ff7cc1f3b45e9d6cacfdb04586b Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 16:03:45 +0000
Subject: [PATCH 37/41] Add combine to store an i128 as a v2i64 when selecting
a store that can use register-indirect-offset addressing mode.
---
llvm/lib/Target/AArch64/AArch64Combine.td | 9 ++-
.../GISel/AArch64PostLegalizerLowering.cpp | 81 +++++++++++++++++++
2 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 278314792bfb9..4ae137efb4bca 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -200,6 +200,13 @@ def vector_unmerge_lowering : GICombineRule <
(apply [{ applyScalarizeVectorUnmerge(*${root}, MRI, B); }])
>;
+def store_i128_as_v2i64 : GICombineRule <
+ (defs root:$root),
+ (match (wip_match_opcode G_STORE):$root,
+ [{ return matchStorei128AsV2i64(*${root}, MRI); }]),
+ (apply [{ applyStorei128AsV2i64(*${root}, MRI, B); }])
+>;
+
def adjust_icmp_imm_matchdata :
GIDefMatchData<"std::pair<uint64_t, CmpInst::Predicate>">;
def adjust_icmp_imm : GICombineRule <
@@ -342,7 +349,7 @@ def AArch64PostLegalizerLowering
lower_vector_fcmp, form_truncstore, fconstant_to_constant,
vector_sext_inreg_to_shift,
unmerge_ext_to_unmerge, lower_mulv2s64,
- vector_unmerge_lowering, insertelt_nonconst,
+ vector_unmerge_lowering, insertelt_nonconst, store_i128_as_v2i64,
unmerge_duplanes]> {
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index b656f2a3d87ca..313185786d992 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -693,6 +693,87 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
return std::nullopt;
}
+// Helper function for matchStorei128AsV2i64. This aids in finding pointers that
+// can use the register-indirect-offset addressing mode
+bool isPointerRoX(const MachineRegisterInfo &MRI, llvm::GStore *&Store) {
+ auto Ptr = Store->getPointerReg();
+ auto *PtrAdd = getOpcodeDef<GPtrAdd>(Ptr, MRI);
+ if (!PtrAdd || !MRI.hasOneNonDBGUse(Ptr))
+ return false;
+
+ Register Offset = PtrAdd->getOperand(2).getReg();
+ if (auto C = getIConstantVRegValWithLookThrough(Offset, MRI))
+ return false;
+
+ auto *OffsetDef = getDefIgnoringCopies(Offset, MRI);
+ if (!OffsetDef)
+ return false;
+
+ if (OffsetDef->getOpcode() == TargetOpcode::G_SHL ||
+ OffsetDef->getOpcode() == TargetOpcode::G_MUL) {
+ auto MaybeImm = getIConstantVRegValWithLookThrough(
+ OffsetDef->getOperand(2).getReg(), MRI);
+
+ if (!MaybeImm)
+ return false;
+
+ uint64_t Shift = OffsetDef->getOpcode() == TargetOpcode::G_SHL
+ ? MaybeImm->Value.getZExtValue()
+ : Log2_64(MaybeImm->Value.getZExtValue());
+
+ if (Shift != Log2_32(16))
+ return false;
+ }
+ return true;
+}
+
+// FPR128 doesn't allow i128 but it does allow v2i64. This means we can't
+// duplicate the pattern for f128 used here (AArch64InstrInfo.td:4617 STRQroX).
+// Instead, we can detect when this instruction would be used and force the
+// types to be a v2i64 thus allowing matching.
+bool matchStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI) {
+ assert(MI.getOpcode() == TargetOpcode::G_STORE &&
+ "Expected a store instruction");
+
+ auto *Store = cast<GStore>(&MI);
+ Register ValReg = Store->getValueReg();
+ LLT ValTy = MRI.getType(ValReg);
+
+ if (!ValTy.isInteger() && ValTy.getScalarSizeInBits() != 128)
+ return false;
+
+ auto *Merge = getOpcodeDef<GMerge>(ValReg, MRI);
+ if (!Merge || Merge->getNumSources() != 2)
+ return false;
+
+ if (!MRI.hasOneNonDBGUse(ValReg))
+ return false;
+
+ auto MergeUser = MRI.use_instr_nodbg_begin(ValReg);
+ if (MergeUser == MRI.use_instr_nodbg_end() || &*MergeUser != &MI)
+ return false;
+
+ if (MRI.getType(Merge->getSourceReg(0)).getScalarSizeInBits() != 64 ||
+ MRI.getType(Merge->getSourceReg(1)).getScalarSizeInBits() != 64)
+ return false;
+
+ return isPointerRoX(MRI, Store);
+};
+
+void applyStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI,
+ MachineIRBuilder &MIB) {
+ auto *Store = cast<GStore>(&MI);
+ Register ValReg = Store->getValueReg();
+
+ auto *Merge = getOpcodeDef<GMerge>(ValReg, MRI);
+
+ auto BV =
+ MIB.buildBuildVector(LLT::fixed_vector(2, LLT::integer(64)),
+ {Merge->getSourceReg(0), Merge->getSourceReg(1)})
+ .getReg(0);
+ MI.getOperand(0).setReg(BV);
+};
+
/// Determine whether or not it is possible to update the RHS and predicate of
/// a G_ICMP instruction such that the RHS will be selected as an arithmetic
/// immediate.
>From eda8d692731ff0a573c26629d63e27fa4ddf763e Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 16:04:01 +0000
Subject: [PATCH 38/41] Update tests
---
.../Atomics/aarch64-atomic-store-rcpc_immo.ll | 2 +-
.../AArch64/Atomics/aarch64-atomicrmw-lsfe.ll | 100 +-
.../Atomics/aarch64-atomicrmw-v8a_fp.ll | 600 +--
.../AArch64/GlobalISel/arm64-atomic.ll | 80 +-
.../GlobalISel/arm64-callingconv-ios.ll | 136 +-
.../AArch64/GlobalISel/arm64-callingconv.ll | 250 +-
.../AArch64/GlobalISel/arm64-fallback.ll | 5 +-
.../GlobalISel/arm64-irtranslator-fmuladd.ll | 33 +-
.../GlobalISel/arm64-irtranslator-gep.ll | 68 +-
.../GlobalISel/arm64-irtranslator-switch.ll | 768 ++--
.../AArch64/GlobalISel/arm64-irtranslator.ll | 1334 +++----
.../AArch64/GlobalISel/arm64-pcsections.ll | 286 +-
.../GlobalISel/arm64-regbankselect.mir | 25 +-
.../AArch64/GlobalISel/bf16-fpext-fptrunc.ll | 127 +
.../AArch64/GlobalISel/bf16-promote.ll | 200 +
.../AArch64/GlobalISel/call-lowering-alias.ll | 2 +-
.../AArch64/GlobalISel/call-lowering-ifunc.ll | 2 +-
.../GlobalISel/call-lowering-signext.ll | 128 +-
.../GlobalISel/call-lowering-sret-demotion.ll | 156 +-
.../GlobalISel/call-lowering-vectors.ll | 57 +-
.../GlobalISel/call-lowering-zeroext.ll | 170 +-
.../AArch64/GlobalISel/call-translator-cse.ll | 19 +-
.../AArch64/GlobalISel/call-translator-ios.ll | 59 +-
.../call-translator-tail-call-sret.ll | 12 +-
.../GlobalISel/call-translator-tail-call.ll | 330 +-
.../AArch64/GlobalISel/call-translator.ll | 228 +-
.../AArch64/GlobalISel/combine-unmerge.mir | 8 +-
.../combiner-load-store-indexing.ll | 62 +-
.../AArch64/GlobalISel/constant-dbg-loc.ll | 18 +-
.../CodeGen/AArch64/GlobalISel/debug-insts.ll | 4 +-
.../AArch64/GlobalISel/dynamic-alloca.ll | 75 +-
.../AArch64/GlobalISel/fconstant-dbg-loc.ll | 2 +-
.../AArch64/GlobalISel/fold-fp-select.mir | 150 +-
.../GlobalISel/inline-memcpy-forced.mir | 36 +-
.../AArch64/GlobalISel/inline-memcpy.mir | 84 +-
.../AArch64/GlobalISel/inline-memmove.mir | 60 +-
.../AArch64/GlobalISel/inline-memset.mir | 60 +-
.../GlobalISel/inline-small-memcpy.mir | 8 +-
.../AArch64/GlobalISel/inttoptr_add.ll | 6 +-
.../AArch64/GlobalISel/invoke-region.ll | 52 +-
.../GlobalISel/irtranslater-samesign.ll | 44 +-
.../GlobalISel/irtranslator-arguments.ll | 38 +-
.../irtranslator-atomic-metadata.ll | 84 +-
.../GlobalISel/irtranslator-bitcast.ll | 4 +-
.../irtranslator-condbr-lower-tree.ll | 364 +-
.../irtranslator-convert-fp16-intrinsics.ll | 26 +-
.../irtranslator-delayed-stack-protector.ll | 9 +-
.../GlobalISel/irtranslator-exceptions.ll | 58 +-
.../GlobalISel/irtranslator-extends.ll | 20 +-
.../irtranslator-fixed-point-intrinsics.ll | 152 +-
.../irtranslator-fp-min-max-intrinsics.ll | 110 +-
.../AArch64/GlobalISel/irtranslator-fpenv.ll | 16 +-
.../GlobalISel/irtranslator-gep-flags.ll | 238 +-
.../irtranslator-hoisted-constants.ll | 46 +-
.../GlobalISel/irtranslator-inline-asm.ll | 166 +-
.../GlobalISel/irtranslator-load-metadata.ll | 24 +-
.../GlobalISel/irtranslator-localescape.ll | 20 +-
.../irtranslator-max-address-space.ll | 7 +-
.../GlobalISel/irtranslator-memcpy-inline.ll | 120 +-
.../GlobalISel/irtranslator-nneg-disjoint.ll | 68 +-
.../irtranslator-no-op-intrinsics.ll | 20 +-
.../irtranslator-one-by-n-vector-ptr-add.ll | 24 +-
.../GlobalISel/irtranslator-reductions.ll | 173 +-
.../AArch64/GlobalISel/irtranslator-sincos.ll | 78 +-
.../irtranslator-split-vector-arg.ll | 15 +-
.../irtranslator-stack-evt-bug47619.ll | 31 +-
.../GlobalISel/irtranslator-stack-objects.ll | 12 +-
...slator-stack-protector-trap-unreachable.ll | 16 +-
.../GlobalISel/irtranslator-stepvector.ll | 16 +-
.../GlobalISel/irtranslator-store-metadata.ll | 16 +-
.../GlobalISel/irtranslator-subvector.ll | 246 +-
.../AArch64/GlobalISel/irtranslator-sucmp.ll | 24 +-
.../GlobalISel/irtranslator-switch-bittest.ll | 276 +-
.../AArch64/GlobalISel/irtranslator-tbaa.ll | 11 +-
.../AArch64/GlobalISel/irtranslator-trunc.ll | 40 +-
.../irtranslator-unwind-inline-asm.ll | 6 +-
.../irtranslator-vector-deinterleave2.ll | 24 +-
.../irtranslator-vector-interleave2.ll | 16 +-
.../AArch64/GlobalISel/irtranslator-vscale.ll | 22 +-
.../AArch64/GlobalISel/legalize-and.mir | 49 +-
.../AArch64/GlobalISel/legalize-bitcast.mir | 120 +-
.../AArch64/GlobalISel/legalize-bswap.mir | 4 +-
.../GlobalISel/legalize-cmpxchg-128.mir | 18 +-
.../AArch64/GlobalISel/legalize-constant.mir | 32 +-
.../AArch64/GlobalISel/legalize-exceptions.ll | 10 +-
.../legalize-extract-vector-elt.mir | 16 +-
.../AArch64/GlobalISel/legalize-fcopysign.mir | 34 +-
.../GlobalISel/legalize-fp-arith-fp16.mir | 9 +-
.../AArch64/GlobalISel/legalize-fpext.mir | 42 +-
.../AArch64/GlobalISel/legalize-fptrunc.mir | 4 +-
.../GlobalISel/legalize-insert-vector-elt.mir | 8 +-
.../GlobalISel/legalize-intrinsic-min-max.mir | 32 +-
.../GlobalISel/legalize-load-store-vector.mir | 20 +-
.../GlobalISel/legalize-load-store.mir | 71 +-
.../AArch64/GlobalISel/legalize-min-max.mir | 192 +-
.../legalize-non-pow2-load-store.mir | 32 +-
.../AArch64/GlobalISel/legalize-or.mir | 16 +-
.../AArch64/GlobalISel/legalize-phi.mir | 16 +-
.../GlobalISel/legalize-reduce-add.mir | 7 +-
.../AArch64/GlobalISel/legalize-s128-div.mir | 36 +-
.../AArch64/GlobalISel/legalize-select.mir | 26 +-
.../GlobalISel/legalize-shuffle-vector.mir | 56 +-
.../legalize-store-vector-bools.mir | 104 +-
.../AArch64/GlobalISel/legalize-vacopy.mir | 18 +-
.../GlobalISel/legalize-vector-compress.mir | 4 +-
.../AArch64/GlobalISel/legalize-xor.mir | 40 +-
.../GlobalISel/load-addressing-modes.mir | 7 +-
.../AArch64/GlobalISel/localizer-arm64-tti.ll | 158 +-
.../AArch64/GlobalISel/phi-with-empty-type.ll | 4 +-
.../postlegalizer-combiner-unmergedup.mir | 8 +-
...legalizer-lowering-build-vector-to-dup.mir | 8 +-
.../postlegalizer-lowering-shuf-to-ins.mir | 72 +-
.../postlegalizer-lowering-shuffle-splat.mir | 48 +-
.../CodeGen/AArch64/GlobalISel/pr168872.ll | 46 +-
.../GlobalISel/preselect-process-phis.mir | 8 +-
.../GlobalISel/regbank-assert-sext.mir | 4 +-
.../GlobalISel/regbank-assert-zext.mir | 4 +-
.../CodeGen/AArch64/GlobalISel/ret-1x-vec.ll | 55 +-
.../AArch64/GlobalISel/ret-vec-promote.ll | 554 +--
.../AArch64/GlobalISel/select-binop.mir | 64 +-
.../AArch64/GlobalISel/select-ceil.mir | 42 +-
.../AArch64/GlobalISel/select-constant.mir | 16 +-
.../CodeGen/AArch64/GlobalISel/select-dup.mir | 126 +-
.../AArch64/GlobalISel/select-fabs.mir | 42 +-
.../AArch64/GlobalISel/select-faddp.mir | 28 +-
.../AArch64/GlobalISel/select-fcmp.mir | 50 +-
.../AArch64/GlobalISel/select-floor.mir | 42 +-
.../AArch64/GlobalISel/select-fmaximum.mir | 24 +-
.../AArch64/GlobalISel/select-fminimum.mir | 24 +-
.../GlobalISel/select-fmul-indexed.mir | 18 +-
.../AArch64/GlobalISel/select-fp-casts.mir | 168 +-
.../GlobalISel/select-fp16-fconstant.mir | 12 +-
.../GlobalISel/select-frint-nofp16.mir | 98 +-
.../AArch64/GlobalISel/select-frint.mir | 48 +-
.../CodeGen/AArch64/GlobalISel/select-imm.mir | 24 +-
.../GlobalISel/select-insert-vector-elt.mir | 10 +-
.../GlobalISel/select-intrinsic-round.mir | 48 +-
.../GlobalISel/select-intrinsic-trunc.mir | 48 +-
.../AArch64/GlobalISel/select-nearbyint.mir | 42 +-
.../AArch64/GlobalISel/select-reduce-fadd.mir | 12 +-
.../AArch64/GlobalISel/select-sqrt.mir | 42 +-
.../select-with-no-legality-check.mir | 520 +--
.../GlobalISel/store-addressing-modes.mir | 10 +-
.../GlobalISel/translate-constant-dag.ll | 45 +-
.../AArch64/GlobalISel/translate-gep.ll | 80 +-
.../AArch64/GlobalISel/translate-ret.ll | 47 +-
.../translate-sve-formal-argument-multiple.ll | 530 +--
.../translate-sve-formal-argument.ll | 264 +-
.../CodeGen/AArch64/GlobalISel/vec-param.ll | 378 +-
.../AArch64/GlobalISel/vec-s16-param.ll | 20 +-
llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll | 43 +-
llvm/test/CodeGen/AArch64/add.ll | 3 +-
llvm/test/CodeGen/AArch64/andorxor.ll | 9 +-
.../CodeGen/AArch64/arm64-arith-saturating.ll | 9 +-
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 818 ++--
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 5 -
.../AArch64/arm64-neon-simd-ldst-one.ll | 58 +-
llvm/test/CodeGen/AArch64/arm64-smaxv.ll | 85 +-
llvm/test/CodeGen/AArch64/arm64-sminv.ll | 85 +-
.../test/CodeGen/AArch64/arm64-this-return.ll | 179 +-
llvm/test/CodeGen/AArch64/arm64-vaddv.ll | 7 +-
.../test/CodeGen/AArch64/bf16-instructions.ll | 1341 ++++---
llvm/test/CodeGen/AArch64/bitcast-extend.ll | 49 +-
llvm/test/CodeGen/AArch64/bitcast.ll | 16 -
llvm/test/CodeGen/AArch64/concat-vector.ll | 4 +-
llvm/test/CodeGen/AArch64/ctlz.ll | 3 +-
llvm/test/CodeGen/AArch64/ctpop.ll | 3 +-
llvm/test/CodeGen/AArch64/cttz.ll | 3 +-
llvm/test/CodeGen/AArch64/fcmp.ll | 12 +-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 60 +-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 509 +--
.../test/CodeGen/AArch64/fptoui-sat-scalar.ll | 51 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 423 ++-
llvm/test/CodeGen/AArch64/insertextract.ll | 8 +-
llvm/test/CodeGen/AArch64/itofp-bf16.ll | 3299 +++++++++--------
llvm/test/CodeGen/AArch64/mul.ll | 3 +-
.../CodeGen/AArch64/neon-extadd-extract.ll | 2 +-
.../CodeGen/AArch64/neon-insextbitcast.ll | 24 +-
llvm/test/CodeGen/AArch64/popcount.ll | 43 +-
llvm/test/CodeGen/AArch64/ptrauth-isel.ll | 4 +-
llvm/test/CodeGen/AArch64/sadd_sat_vec.ll | 3 +-
llvm/test/CodeGen/AArch64/ssub_sat_vec.ll | 3 +-
llvm/test/CodeGen/AArch64/sub.ll | 3 +-
llvm/test/CodeGen/AArch64/uadd_sat_vec.ll | 3 +-
llvm/test/CodeGen/AArch64/usub_sat_vec.ll | 3 +-
185 files changed, 10791 insertions(+), 9778 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
index de12866fc2f4b..d67ff8eb21c87 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
@@ -421,7 +421,7 @@ define void @store_atomic_i128_from_gep() {
; GISEL-LABEL: store_atomic_i128_from_gep:
; GISEL: bl init
; GISEL: dmb ish
-; GISEL: stp x8, x8, [x9, #16]
+; GISEL: stp x8, x9, [x10, #16]
;
; SDAG-LABEL: store_atomic_i128_from_gep:
; SDAG: bl init
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index e0f2dd728c5e6..b18271dfd412c 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -379,10 +379,10 @@ define dso_local double @atomicrmw_fadd_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -393,10 +393,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -407,10 +407,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -421,10 +421,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -435,10 +435,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -539,9 +539,9 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_monotonic:
@@ -553,9 +553,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acquire:
@@ -567,9 +567,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_release:
@@ -581,9 +581,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
@@ -595,9 +595,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
@@ -609,9 +609,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_monotonic:
@@ -623,9 +623,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acquire:
@@ -637,9 +637,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_release:
@@ -651,9 +651,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
@@ -665,9 +665,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
index 4a1b7642eff4c..e56442e690645 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
@@ -5,10 +5,10 @@
define dso_local half @atomicrmw_fadd_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -19,10 +19,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fadd_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -33,10 +33,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -47,10 +47,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -61,10 +61,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -165,9 +165,9 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fadd_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_monotonic:
@@ -179,9 +179,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fadd_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_acquire:
@@ -193,9 +193,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_release:
@@ -207,9 +207,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_acq_rel:
@@ -221,9 +221,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_seq_cst:
@@ -235,9 +235,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fadd_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_monotonic:
@@ -249,9 +249,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fadd_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_acquire:
@@ -263,9 +263,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_release:
@@ -277,9 +277,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_acq_rel:
@@ -291,9 +291,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_seq_cst:
@@ -480,10 +480,10 @@ define dso_local double @atomicrmw_fadd_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -494,10 +494,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -508,10 +508,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -522,10 +522,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -536,10 +536,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -640,9 +640,9 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_monotonic:
@@ -654,9 +654,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acquire:
@@ -668,9 +668,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_release:
@@ -682,9 +682,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
@@ -696,9 +696,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
@@ -710,9 +710,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_monotonic:
@@ -724,9 +724,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acquire:
@@ -738,9 +738,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_release:
@@ -752,9 +752,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
@@ -766,9 +766,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
@@ -955,10 +955,10 @@ define dso_local double @atomicrmw_fsub_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmax_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -969,10 +969,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fmax_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -983,10 +983,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -997,10 +997,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1011,10 +1011,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1115,9 +1115,9 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fmax_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_monotonic:
@@ -1129,9 +1129,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fmax_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_acquire:
@@ -1143,9 +1143,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_release:
@@ -1157,9 +1157,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_acq_rel:
@@ -1171,9 +1171,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_seq_cst:
@@ -1185,9 +1185,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fmax_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_monotonic:
@@ -1199,9 +1199,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fmax_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_acquire:
@@ -1213,9 +1213,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_release:
@@ -1227,9 +1227,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_acq_rel:
@@ -1241,9 +1241,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_seq_cst:
@@ -1430,10 +1430,10 @@ define dso_local double @atomicrmw_fmax_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmin_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1444,10 +1444,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fmin_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1458,10 +1458,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1472,10 +1472,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1486,10 +1486,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1590,9 +1590,9 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fmin_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_monotonic:
@@ -1604,9 +1604,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fmin_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_acquire:
@@ -1618,9 +1618,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_release:
@@ -1632,9 +1632,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_acq_rel:
@@ -1646,9 +1646,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_seq_cst:
@@ -1660,9 +1660,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fmin_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_monotonic:
@@ -1674,9 +1674,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fmin_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_acquire:
@@ -1688,9 +1688,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_release:
@@ -1702,9 +1702,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_acq_rel:
@@ -1716,9 +1716,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_seq_cst:
@@ -1905,10 +1905,10 @@ define dso_local double @atomicrmw_fmin_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1919,10 +1919,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr, half
define dso_local half @atomicrmw_fmaximum_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1933,10 +1933,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_acquire(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1947,10 +1947,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_release(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1961,10 +1961,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_acq_rel(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2065,9 +2065,9 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_aligned_seq_cst(ptr %ptr, bfl
define dso_local float @atomicrmw_fmaximum_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_monotonic:
@@ -2079,9 +2079,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_monotonic(ptr %ptr, flo
define dso_local float @atomicrmw_fmaximum_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_acquire:
@@ -2093,9 +2093,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_acquire(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_release:
@@ -2107,9 +2107,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_release(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_acq_rel:
@@ -2121,9 +2121,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_acq_rel(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_seq_cst:
@@ -2135,9 +2135,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_seq_cst(ptr %ptr, float
define dso_local double @atomicrmw_fmaximum_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_monotonic:
@@ -2149,9 +2149,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_monotonic(ptr %ptr, d
define dso_local double @atomicrmw_fmaximum_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_acquire:
@@ -2163,9 +2163,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_acquire(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_release:
@@ -2177,9 +2177,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_release(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_acq_rel:
@@ -2191,9 +2191,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_acq_rel(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_seq_cst:
@@ -2380,10 +2380,10 @@ define dso_local double @atomicrmw_fmaximum_double_unaligned_seq_cst(ptr %ptr, d
define dso_local half @atomicrmw_fminimum_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -2394,10 +2394,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_monotonic(ptr %ptr, half
define dso_local half @atomicrmw_fminimum_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -2408,10 +2408,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_acquire(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -2422,10 +2422,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_release(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -2436,10 +2436,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_acq_rel(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2540,9 +2540,9 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_aligned_seq_cst(ptr %ptr, bfl
define dso_local float @atomicrmw_fminimum_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_monotonic:
@@ -2554,9 +2554,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_monotonic(ptr %ptr, flo
define dso_local float @atomicrmw_fminimum_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_acquire:
@@ -2568,9 +2568,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_acquire(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_release:
@@ -2582,9 +2582,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_release(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_acq_rel:
@@ -2596,9 +2596,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_acq_rel(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_seq_cst:
@@ -2610,9 +2610,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_seq_cst(ptr %ptr, float
define dso_local double @atomicrmw_fminimum_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_monotonic:
@@ -2624,9 +2624,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_monotonic(ptr %ptr, d
define dso_local double @atomicrmw_fminimum_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_acquire:
@@ -2638,9 +2638,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_acquire(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_release:
@@ -2652,9 +2652,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_release(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_acq_rel:
@@ -2666,9 +2666,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_acq_rel(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_seq_cst:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index 3f51ec747182a..1e204e431d5e1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -2953,6 +2953,10 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB37_1
; CHECK-NOLSE-O0-NEXT: b LBB37_5
@@ -3045,6 +3049,10 @@ define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB38_1
; CHECK-NOLSE-O0-NEXT: b LBB38_5
@@ -3139,6 +3147,10 @@ define i16 @atomicrmw_sub_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB39_1
; CHECK-NOLSE-O0-NEXT: b LBB39_5
@@ -3237,6 +3249,10 @@ define i16 @atomicrmw_and_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB40_1
; CHECK-NOLSE-O0-NEXT: b LBB40_5
@@ -3335,6 +3351,10 @@ define i16 @atomicrmw_or_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB41_1
; CHECK-NOLSE-O0-NEXT: b LBB41_5
@@ -3429,6 +3449,10 @@ define i16 @atomicrmw_xor_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB42_1
; CHECK-NOLSE-O0-NEXT: b LBB42_5
@@ -3528,6 +3552,10 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB43_1
; CHECK-NOLSE-O0-NEXT: b LBB43_5
@@ -3545,8 +3573,8 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB43_1
; CHECK-OUTLINE-O0-NEXT: LBB43_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3563,7 +3591,11 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB43_1
; CHECK-OUTLINE-O0-NEXT: b LBB43_2
; CHECK-OUTLINE-O0-NEXT: LBB43_2: ; %atomicrmw.end
@@ -3648,6 +3680,10 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB44_1
; CHECK-NOLSE-O0-NEXT: b LBB44_5
@@ -3665,8 +3701,8 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB44_1
; CHECK-OUTLINE-O0-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3683,7 +3719,11 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB44_1
; CHECK-OUTLINE-O0-NEXT: b LBB44_2
; CHECK-OUTLINE-O0-NEXT: LBB44_2: ; %atomicrmw.end
@@ -3770,6 +3810,10 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB45_1
; CHECK-NOLSE-O0-NEXT: b LBB45_5
@@ -3787,8 +3831,8 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB45_1
; CHECK-OUTLINE-O0-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3805,7 +3849,11 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB45_1
; CHECK-OUTLINE-O0-NEXT: b LBB45_2
; CHECK-OUTLINE-O0-NEXT: LBB45_2: ; %atomicrmw.end
@@ -3892,6 +3940,10 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB46_1
; CHECK-NOLSE-O0-NEXT: b LBB46_5
@@ -3909,8 +3961,8 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB46_1
; CHECK-OUTLINE-O0-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3927,7 +3979,11 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB46_1
; CHECK-OUTLINE-O0-NEXT: b LBB46_2
; CHECK-OUTLINE-O0-NEXT: LBB46_2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
index b34e5ae45f7dd..16ddaba8b29a0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
@@ -8,39 +8,39 @@ declare void @varargs(i32, double, i64, ...)
define void @test_varargs() {
; CHECK-LABEL: name: test_varargs
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double 2.000000e+00
; CHECK-NEXT: ADJCALLSTACKDOWN 40, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C3]](s8)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[C3]](i8)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ANYEXT]](s32)
- ; CHECK-NEXT: G_STORE [[ANYEXT1]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 1)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[C4]](s16)
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s64)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[ANYEXT2]](s32)
- ; CHECK-NEXT: G_STORE [[ANYEXT3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into stack + 8, align 1)
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C10]](s64)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
- ; CHECK-NEXT: G_STORE [[ANYEXT4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into stack + 16, align 1)
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C11]](s64)
- ; CHECK-NEXT: G_STORE [[C6]](s32), [[PTR_ADD3]](p0) :: (store (s32) into stack + 24, align 1)
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
- ; CHECK-NEXT: G_STORE [[C7]](s64), [[PTR_ADD4]](p0) :: (store (s64) into stack + 32, align 1)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
- ; CHECK-NEXT: $d0 = COPY [[C1]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C2]](s64)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](i64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i64) = G_ANYEXT [[ANYEXT]](i32)
+ ; CHECK-NEXT: G_STORE [[ANYEXT1]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack, align 1)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[C4]](i16)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](i64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i64) = G_ANYEXT [[ANYEXT2]](i32)
+ ; CHECK-NEXT: G_STORE [[ANYEXT3]](i64), [[PTR_ADD1]](p0) :: (store (i64) into stack + 8, align 1)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C10]](i64)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i64) = G_ANYEXT [[C5]](i32)
+ ; CHECK-NEXT: G_STORE [[ANYEXT4]](i64), [[PTR_ADD2]](p0) :: (store (i64) into stack + 16, align 1)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C11]](i64)
+ ; CHECK-NEXT: G_STORE [[C6]](f32), [[PTR_ADD3]](p0) :: (store (f32) into stack + 24, align 1)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](i64)
+ ; CHECK-NEXT: G_STORE [[C7]](f64), [[PTR_ADD4]](p0) :: (store (f64) into stack + 32, align 1)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY [[C1]](f64)
+ ; CHECK-NEXT: $x1 = COPY [[C2]](i64)
; CHECK-NEXT: BL @varargs, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1
; CHECK-NEXT: ADJCALLSTACKUP 40, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
@@ -53,47 +53,47 @@ declare i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext
define i32 @i8i16caller() nounwind readnone {
; CHECK-LABEL: name: i8i16caller
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s8) = G_CONSTANT i8 97
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 98
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s8) = G_CONSTANT i8 99
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s8) = G_CONSTANT i8 100
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i8) = G_CONSTANT i8 97
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i16) = G_CONSTANT i16 98
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i8) = G_CONSTANT i8 99
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i8) = G_CONSTANT i8 100
; CHECK-NEXT: ADJCALLSTACKDOWN 6, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
- ; CHECK-NEXT: G_STORE [[C8]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s64)
- ; CHECK-NEXT: G_STORE [[C9]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 2, align 1)
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](s64)
- ; CHECK-NEXT: G_STORE [[C10]](s8), [[PTR_ADD2]](p0) :: (store (s8) into stack + 4)
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](s64)
- ; CHECK-NEXT: G_STORE [[C11]](s8), [[PTR_ADD3]](p0) :: (store (s8) into stack + 5)
- ; CHECK-NEXT: $x0 = COPY [[C]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[C2]](s64)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C3]](s8)
- ; CHECK-NEXT: $w3 = COPY [[SEXT]](s32)
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C4]](s16)
- ; CHECK-NEXT: $w4 = COPY [[SEXT1]](s32)
- ; CHECK-NEXT: $x5 = COPY [[C5]](s64)
- ; CHECK-NEXT: $x6 = COPY [[C6]](s64)
- ; CHECK-NEXT: $x7 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](i64)
+ ; CHECK-NEXT: G_STORE [[C8]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](i64)
+ ; CHECK-NEXT: G_STORE [[C9]](i16), [[PTR_ADD1]](p0) :: (store (i16) into stack + 2, align 1)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](i64)
+ ; CHECK-NEXT: G_STORE [[C10]](i8), [[PTR_ADD2]](p0) :: (store (i8) into stack + 4)
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](i64)
+ ; CHECK-NEXT: G_STORE [[C11]](i8), [[PTR_ADD3]](p0) :: (store (i8) into stack + 5)
+ ; CHECK-NEXT: $x0 = COPY [[C]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[C1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[C2]](i64)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[C3]](i8)
+ ; CHECK-NEXT: $w3 = COPY [[SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i32) = G_SEXT [[C4]](i16)
+ ; CHECK-NEXT: $w4 = COPY [[SEXT1]](i32)
+ ; CHECK-NEXT: $x5 = COPY [[C5]](i64)
+ ; CHECK-NEXT: $x6 = COPY [[C6]](i64)
+ ; CHECK-NEXT: $x7 = COPY [[C7]](i64)
; CHECK-NEXT: BL @i8i16callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 6, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%call = tail call i64 @i8i16callee(i64 0, i64 1, i64 2, i8 signext 3, i16 signext 4, i64 5, i64 6, i64 7, i8 97, i16 98, i8 99, i8 100)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
index 048063823d1c1..91c57b718efca 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
@@ -9,15 +9,15 @@ define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4, $w5, $w6, $w7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $w6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $w7
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $w6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $w7
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
i32 %w4, i32 %w5, i32 %w6, i32 %w7) {
ret i32 %w0
@@ -28,15 +28,15 @@ define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
ret i64 %x0
@@ -67,8 +67,8 @@ define [1 x double] @args_arr([1 x double] %d0) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: $d0 = COPY [[COPY]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret [1 x double] %d0
}
@@ -77,25 +77,25 @@ declare void @varargs(i32, double, i64, ...)
define void @test_varargs() {
; CHECK-LABEL: name: test_varargs
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double 2.000000e+00
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C3]](s8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C4]](s16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
- ; CHECK-NEXT: $d0 = COPY [[C1]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C2]](s64)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w3 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w4 = COPY [[C5]](s32)
- ; CHECK-NEXT: $s1 = COPY [[C6]](s32)
- ; CHECK-NEXT: $d2 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[C3]](i8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[C4]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY [[C1]](f64)
+ ; CHECK-NEXT: $x1 = COPY [[C2]](i64)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w3 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w4 = COPY [[C5]](i32)
+ ; CHECK-NEXT: $s1 = COPY [[C6]](f32)
+ ; CHECK-NEXT: $d2 = COPY [[C7]](f64)
; CHECK-NEXT: BL @varargs, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1, implicit $w2, implicit $w3, implicit $w4, implicit $s1, implicit $d2
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
@@ -111,21 +111,21 @@ declare void @stack_ext_needed([8 x i64], i8 signext %in)
define void @test_stack_ext_needed() {
; CHECK-LABEL: name: test_stack_ext_needed
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 42
; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; CHECK-NEXT: $x0 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x1 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x2 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x3 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x4 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x5 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x6 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x7 = COPY [[DEF]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; CHECK-NEXT: $x0 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x4 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x5 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x6 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x7 = COPY [[DEF]](i64)
; CHECK-NEXT: BL @stack_ext_needed, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7
; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
@@ -133,40 +133,40 @@ define void @test_stack_ext_needed() {
ret void
}
-; Check that we can lower incoming i128 types into constituent s64 gprs.
+; Check that we can lower incoming i128 types into constituent i64 gprs.
define void @callee_s128(i128 %a, i128 %b, ptr %ptr) {
; CHECK-LABEL: name: callee_s128
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x4
- ; CHECK-NEXT: G_STORE [[MV1]](s128), [[COPY4]](p0) :: (store (s128) into %ir.ptr)
+ ; CHECK-NEXT: G_STORE [[MV1]](i128), [[COPY4]](p0) :: (store (i128) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store i128 %b, ptr %ptr
ret void
}
-; Check we can lower outgoing s128 arguments into s64 gprs.
+; Check we can lower outgoing s128 arguments into i64 gprs.
define void @caller_s128(ptr %ptr) {
; CHECK-LABEL: name: caller_s128
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.ptr)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i128) = G_LOAD [[COPY]](p0) :: (load (i128) from %ir.ptr)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](i128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](i128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: $x4 = COPY [[COPY]](p0)
; CHECK-NEXT: BL @callee_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -182,47 +182,47 @@ declare i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext
define i32 @i8i16caller() nounwind readnone {
; CHECK-LABEL: name: i8i16caller
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s8) = G_CONSTANT i8 97
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 98
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s8) = G_CONSTANT i8 99
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s8) = G_CONSTANT i8 100
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i8) = G_CONSTANT i8 97
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i16) = G_CONSTANT i16 98
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i8) = G_CONSTANT i8 99
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i8) = G_CONSTANT i8 100
; CHECK-NEXT: ADJCALLSTACKDOWN 32, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
- ; CHECK-NEXT: G_STORE [[C8]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s64)
- ; CHECK-NEXT: G_STORE [[C9]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 8, align 1)
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](s64)
- ; CHECK-NEXT: G_STORE [[C10]](s8), [[PTR_ADD2]](p0) :: (store (s8) into stack + 16)
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](s64)
- ; CHECK-NEXT: G_STORE [[C11]](s8), [[PTR_ADD3]](p0) :: (store (s8) into stack + 24)
- ; CHECK-NEXT: $x0 = COPY [[C]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[C2]](s64)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C3]](s8)
- ; CHECK-NEXT: $w3 = COPY [[SEXT]](s32)
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C4]](s16)
- ; CHECK-NEXT: $w4 = COPY [[SEXT1]](s32)
- ; CHECK-NEXT: $x5 = COPY [[C5]](s64)
- ; CHECK-NEXT: $x6 = COPY [[C6]](s64)
- ; CHECK-NEXT: $x7 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](i64)
+ ; CHECK-NEXT: G_STORE [[C8]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](i64)
+ ; CHECK-NEXT: G_STORE [[C9]](i16), [[PTR_ADD1]](p0) :: (store (i16) into stack + 8, align 1)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](i64)
+ ; CHECK-NEXT: G_STORE [[C10]](i8), [[PTR_ADD2]](p0) :: (store (i8) into stack + 16)
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](i64)
+ ; CHECK-NEXT: G_STORE [[C11]](i8), [[PTR_ADD3]](p0) :: (store (i8) into stack + 24)
+ ; CHECK-NEXT: $x0 = COPY [[C]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[C1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[C2]](i64)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[C3]](i8)
+ ; CHECK-NEXT: $w3 = COPY [[SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i32) = G_SEXT [[C4]](i16)
+ ; CHECK-NEXT: $w4 = COPY [[SEXT1]](i32)
+ ; CHECK-NEXT: $x5 = COPY [[C5]](i64)
+ ; CHECK-NEXT: $x6 = COPY [[C6]](i64)
+ ; CHECK-NEXT: $x7 = COPY [[C7]](i64)
; CHECK-NEXT: BL @i8i16callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%call = tail call i64 @i8i16callee(i64 0, i64 1, i64 2, i8 signext 3, i16 signext 4, i64 5, i64 6, i64 7, i8 97, i16 98, i8 99, i8 100)
@@ -235,9 +235,9 @@ define void @arg_v2i64(<2 x i64> %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[COPY]](<2 x s64>), [[DEF]](p0) :: (store (<2 x s64>) into `ptr undef`)
+ ; CHECK-NEXT: G_STORE [[COPY]](<2 x i64>), [[DEF]](p0) :: (store (<2 x i64>) into `ptr undef`)
; CHECK-NEXT: RET_ReallyLR
store <2 x i64> %arg, ptr undef
ret void
@@ -248,13 +248,13 @@ define void @arg_v8i64(<8 x i64> %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>), [[COPY3]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x i64>) = G_CONCAT_VECTORS [[COPY]](<2 x i64>), [[COPY1]](<2 x i64>), [[COPY2]](<2 x i64>), [[COPY3]](<2 x i64>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<8 x s64>), [[DEF]](p0) :: (store (<8 x s64>) into `ptr undef`)
+ ; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<8 x i64>), [[DEF]](p0) :: (store (<8 x i64>) into `ptr undef`)
; CHECK-NEXT: RET_ReallyLR
store <8 x i64> %arg, ptr undef
ret void
@@ -265,10 +265,10 @@ define void @arg_v4f32(<4 x float> %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[DEF]](p0) :: (store (<4 x s32>) into `ptr undef`)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](<4 x f32>), [[DEF]](p0) :: (store (<4 x f32>) into `ptr undef`)
; CHECK-NEXT: RET_ReallyLR
store <4 x float> %arg, ptr undef
ret void
@@ -279,17 +279,17 @@ define void @ret_arg_v16f32(<16 x float> %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY3]](<2 x s64>)
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x s32>), [[BITCAST1]](<4 x s32>), [[BITCAST2]](<4 x s32>), [[BITCAST3]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x f32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x f32>), [[BITCAST1]](<4 x f32>), [[BITCAST2]](<4 x f32>), [[BITCAST3]](<4 x f32>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<16 x s32>), [[DEF]](p0) :: (store (<16 x s32>) into `ptr undef`)
+ ; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<16 x f32>), [[DEF]](p0) :: (store (<16 x f32>) into `ptr undef`)
; CHECK-NEXT: RET_ReallyLR
store <16 x float> %arg, ptr undef
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index f8cd868a4c755..3b56d062ffc5c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
@@ -16,7 +17,7 @@ target triple = "aarch64--"
; Make sure we don't mess up metadata arguments.
declare void @llvm.write_register.i64(metadata, i64)
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_WRITE_REGISTER !0, %0:_(s64) (in function: test_write_register_intrin)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_WRITE_REGISTER !0, %0:_(i64) (in function: test_write_register_intrin)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_register_intrin
; FALLBACK-WITH-REPORT-LABEL: test_write_register_intrin:
define void @test_write_register_intrin() {
@@ -101,7 +102,7 @@ entry:
ret void
}
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %4:_(s128), %5:_(s1) = G_UMULO %0:_, %6:_ (in function: umul_s128)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %4:_(i128), %5:_(i1) = G_UMULO %0:_, %6:_ (in function: umul_s128)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for umul_s128
; FALLBACK-WITH-REPORT-OUT-LABEL: umul_s128
declare {i128, i1} @llvm.umul.with.overflow.i128(i128, i128) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
index 371255a11dea9..b742689a3ca45 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
@@ -7,23 +7,26 @@ target triple = "aarch64--"
define float @test_fmuladd(float %x, float %y, float %z) {
; FPFAST-LABEL: name: test_fmuladd
; FPFAST: bb.1 (%ir-block.0):
- ; FPFAST: liveins: $s0, $s1, $s2
- ; FPFAST: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; FPFAST: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; FPFAST: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
- ; FPFAST: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
- ; FPFAST: $s0 = COPY [[FMA]](s32)
- ; FPFAST: RET_ReallyLR implicit $s0
+ ; FPFAST-NEXT: liveins: $s0, $s1, $s2
+ ; FPFAST-NEXT: {{ $}}
+ ; FPFAST-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; FPFAST-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; FPFAST-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
+ ; FPFAST-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; FPFAST-NEXT: $s0 = COPY [[FMA]](f32)
+ ; FPFAST-NEXT: RET_ReallyLR implicit $s0
+ ;
; FPOFF-LABEL: name: test_fmuladd
; FPOFF: bb.1 (%ir-block.0):
- ; FPOFF: liveins: $s0, $s1, $s2
- ; FPOFF: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; FPOFF: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; FPOFF: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
- ; FPOFF: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
- ; FPOFF: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
- ; FPOFF: $s0 = COPY [[FADD]](s32)
- ; FPOFF: RET_ReallyLR implicit $s0
+ ; FPOFF-NEXT: liveins: $s0, $s1, $s2
+ ; FPOFF-NEXT: {{ $}}
+ ; FPOFF-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; FPOFF-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; FPOFF-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
+ ; FPOFF-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[COPY1]]
+ ; FPOFF-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[COPY2]]
+ ; FPOFF-NEXT: $s0 = COPY [[FADD]](f32)
+ ; FPOFF-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.fmuladd.f32(float %x, float %y, float %z)
ret float %res
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
index da171edb03808..269597cbd730b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
@@ -10,20 +10,20 @@ define i32 @cse_gep(ptr %ptr, i32 %idx) {
; O0-NEXT: liveins: $w1, $x0
; O0-NEXT: {{ $}}
; O0-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; O0-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; O0-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; O0-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; O0-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; O0-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; O0-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; O0-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; O0-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; O0-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; O0-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; O0-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; O0-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; O0-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; O0-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; O0-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; O0-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; O0-NEXT: $w0 = COPY [[ADD]](s32)
+ ; O0-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; O0-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; O0-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; O0-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; O0-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; O0-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; O0-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; O0-NEXT: $w0 = COPY [[ADD]](i32)
; O0-NEXT: RET_ReallyLR implicit $w0
;
; O3-LABEL: name: cse_gep
@@ -31,18 +31,18 @@ define i32 @cse_gep(ptr %ptr, i32 %idx) {
; O3-NEXT: liveins: $w1, $x0
; O3-NEXT: {{ $}}
; O3-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; O3-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; O3-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; O3-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; O3-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; O3-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; O3-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; O3-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; O3-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; O3-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; O3-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; O3-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; O3-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
- ; O3-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from %ir.gep2)
- ; O3-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; O3-NEXT: $w0 = COPY [[ADD]](s32)
+ ; O3-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; O3-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; O3-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C1]](i64)
+ ; O3-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p0) :: (load (i32) from %ir.gep2)
+ ; O3-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; O3-NEXT: $w0 = COPY [[ADD]](i32)
; O3-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -60,11 +60,11 @@ define void @ossfuzz65052() {
; O0-NEXT: successors: %bb.2(0x80000000)
; O0-NEXT: {{ $}}
; O0-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; O0-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -170141183460469231731687303715884105728
- ; O0-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128)
- ; O0-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; O0-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[TRUNC]], [[C1]]
- ; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](s64)
+ ; O0-NEXT: [[C:%[0-9]+]]:_(i128) = G_CONSTANT i128 -170141183460469231731687303715884105728
+ ; O0-NEXT: [[TRUNC:%[0-9]+]]:_(i64) = G_TRUNC [[C]](i128)
+ ; O0-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; O0-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[TRUNC]], [[C1]]
+ ; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](i64)
; O0-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; O0-NEXT: G_BR %bb.2
; O0-NEXT: {{ $}}
@@ -78,11 +78,11 @@ define void @ossfuzz65052() {
; O3-NEXT: successors: %bb.2(0x80000000)
; O3-NEXT: {{ $}}
; O3-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; O3-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -170141183460469231731687303715884105728
- ; O3-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128)
- ; O3-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; O3-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[TRUNC]], [[C1]]
- ; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](s64)
+ ; O3-NEXT: [[C:%[0-9]+]]:_(i128) = G_CONSTANT i128 -170141183460469231731687303715884105728
+ ; O3-NEXT: [[TRUNC:%[0-9]+]]:_(i64) = G_TRUNC [[C]](i128)
+ ; O3-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; O3-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[TRUNC]], [[C1]]
+ ; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](i64)
; O3-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; O3-NEXT: {{ $}}
; O3-NEXT: bb.2.BB:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
index 02a8a4f618156..46efce8004c9c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
@@ -6,36 +6,36 @@ define i32 @switch(i32 %argc) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 200
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 100
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 200
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.default:
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C4]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[C4]]
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.case100:
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C3]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[C3]]
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.case200:
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[C2]]
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.return:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.2, [[ADD1]](s32), %bb.3, [[ADD2]](s32), %bb.4
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[ADD]](i32), %bb.2, [[ADD1]](i32), %bb.3, [[ADD2]](i32), %bb.4
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %argc, label %default [
@@ -65,30 +65,30 @@ define i32 @test_cfg_remap(i32 %in) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 57
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 57
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.next:
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.other:
- ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[DEF]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.phi.block:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.5, [[C2]](s32), %bb.2
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C]](i32), %bb.5, [[C2]](i32), %bb.2
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %in, label %phi.block [i32 1, label %next
@@ -110,25 +110,25 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 57
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 57
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 128
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.entry:
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.5
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.5
; CHECK-NEXT: G_BR %bb.8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.entry:
@@ -141,12 +141,12 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.other:
- ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[DEF]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.phi.block:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.7, [[C]](s32), %bb.8, [[C4]](s32), %bb.3
- ; CHECK-NEXT: $w0 = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C]](i32), %bb.7, [[C]](i32), %bb.8, [[C4]](i32), %bb.3
+ ; CHECK-NEXT: $w0 = COPY [[C3]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %in, label %odd [i32 1, label %next
@@ -172,17 +172,17 @@ define i32 @jt_test(i32 %x) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 71
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C4]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 71
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C4]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.3, %bb.4, %bb.2
@@ -191,16 +191,16 @@ define i32 @jt_test(i32 %x) {
; CHECK-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[ZEXT]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.bb:
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = nsw G_ADD [[COPY]], [[C2]]
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.sw.bb1:
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i32) = nsw G_MUL [[COPY]], [[C1]]
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.return:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C3]](s32), %bb.1, [[C3]](s32), %bb.5
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[MUL]](i32), %bb.3, [[ADD]](i32), %bb.2, [[C3]](i32), %bb.1, [[C3]](i32), %bb.5
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %x, label %return [
@@ -238,393 +238,393 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: liveins: $w1, $x0, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
- ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
- ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
- ; CHECK-NEXT: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
- ; CHECK-NEXT: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
- ; CHECK-NEXT: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
- ; CHECK-NEXT: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 34
- ; CHECK-NEXT: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 35
- ; CHECK-NEXT: [[C32:%[0-9]+]]:_(s32) = G_CONSTANT i32 36
- ; CHECK-NEXT: [[C33:%[0-9]+]]:_(s32) = G_CONSTANT i32 37
- ; CHECK-NEXT: [[C34:%[0-9]+]]:_(s32) = G_CONSTANT i32 38
- ; CHECK-NEXT: [[C35:%[0-9]+]]:_(s32) = G_CONSTANT i32 39
- ; CHECK-NEXT: [[C36:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
- ; CHECK-NEXT: [[C37:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C38:%[0-9]+]]:_(s32) = G_CONSTANT i32 43
- ; CHECK-NEXT: [[C39:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
- ; CHECK-NEXT: [[C40:%[0-9]+]]:_(s32) = G_CONSTANT i32 45
- ; CHECK-NEXT: [[C41:%[0-9]+]]:_(s32) = G_CONSTANT i32 46
- ; CHECK-NEXT: [[C42:%[0-9]+]]:_(s32) = G_CONSTANT i32 47
- ; CHECK-NEXT: [[C43:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
- ; CHECK-NEXT: [[C44:%[0-9]+]]:_(s32) = G_CONSTANT i32 49
- ; CHECK-NEXT: [[C45:%[0-9]+]]:_(s32) = G_CONSTANT i32 50
- ; CHECK-NEXT: [[C46:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
- ; CHECK-NEXT: [[C47:%[0-9]+]]:_(s32) = G_CONSTANT i32 52
- ; CHECK-NEXT: [[C48:%[0-9]+]]:_(s32) = G_CONSTANT i32 53
- ; CHECK-NEXT: [[C49:%[0-9]+]]:_(s32) = G_CONSTANT i32 54
- ; CHECK-NEXT: [[C50:%[0-9]+]]:_(s32) = G_CONSTANT i32 55
- ; CHECK-NEXT: [[C51:%[0-9]+]]:_(s32) = G_CONSTANT i32 4352
- ; CHECK-NEXT: [[C52:%[0-9]+]]:_(s32) = G_CONSTANT i32 4353
- ; CHECK-NEXT: [[C53:%[0-9]+]]:_(s32) = G_CONSTANT i32 4354
- ; CHECK-NEXT: [[C54:%[0-9]+]]:_(s32) = G_CONSTANT i32 4355
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 14
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 17
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i32) = G_CONSTANT i32 18
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 19
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 22
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 23
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(i32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(i32) = G_CONSTANT i32 26
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(i32) = G_CONSTANT i32 27
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(i32) = G_CONSTANT i32 28
+ ; CHECK-NEXT: [[C25:%[0-9]+]]:_(i32) = G_CONSTANT i32 29
+ ; CHECK-NEXT: [[C26:%[0-9]+]]:_(i32) = G_CONSTANT i32 30
+ ; CHECK-NEXT: [[C27:%[0-9]+]]:_(i32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[C28:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[C29:%[0-9]+]]:_(i32) = G_CONSTANT i32 33
+ ; CHECK-NEXT: [[C30:%[0-9]+]]:_(i32) = G_CONSTANT i32 34
+ ; CHECK-NEXT: [[C31:%[0-9]+]]:_(i32) = G_CONSTANT i32 35
+ ; CHECK-NEXT: [[C32:%[0-9]+]]:_(i32) = G_CONSTANT i32 36
+ ; CHECK-NEXT: [[C33:%[0-9]+]]:_(i32) = G_CONSTANT i32 37
+ ; CHECK-NEXT: [[C34:%[0-9]+]]:_(i32) = G_CONSTANT i32 38
+ ; CHECK-NEXT: [[C35:%[0-9]+]]:_(i32) = G_CONSTANT i32 39
+ ; CHECK-NEXT: [[C36:%[0-9]+]]:_(i32) = G_CONSTANT i32 41
+ ; CHECK-NEXT: [[C37:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C38:%[0-9]+]]:_(i32) = G_CONSTANT i32 43
+ ; CHECK-NEXT: [[C39:%[0-9]+]]:_(i32) = G_CONSTANT i32 44
+ ; CHECK-NEXT: [[C40:%[0-9]+]]:_(i32) = G_CONSTANT i32 45
+ ; CHECK-NEXT: [[C41:%[0-9]+]]:_(i32) = G_CONSTANT i32 46
+ ; CHECK-NEXT: [[C42:%[0-9]+]]:_(i32) = G_CONSTANT i32 47
+ ; CHECK-NEXT: [[C43:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
+ ; CHECK-NEXT: [[C44:%[0-9]+]]:_(i32) = G_CONSTANT i32 49
+ ; CHECK-NEXT: [[C45:%[0-9]+]]:_(i32) = G_CONSTANT i32 50
+ ; CHECK-NEXT: [[C46:%[0-9]+]]:_(i32) = G_CONSTANT i32 51
+ ; CHECK-NEXT: [[C47:%[0-9]+]]:_(i32) = G_CONSTANT i32 52
+ ; CHECK-NEXT: [[C48:%[0-9]+]]:_(i32) = G_CONSTANT i32 53
+ ; CHECK-NEXT: [[C49:%[0-9]+]]:_(i32) = G_CONSTANT i32 54
+ ; CHECK-NEXT: [[C50:%[0-9]+]]:_(i32) = G_CONSTANT i32 55
+ ; CHECK-NEXT: [[C51:%[0-9]+]]:_(i32) = G_CONSTANT i32 4352
+ ; CHECK-NEXT: [[C52:%[0-9]+]]:_(i32) = G_CONSTANT i32 4353
+ ; CHECK-NEXT: [[C53:%[0-9]+]]:_(i32) = G_CONSTANT i32 4354
+ ; CHECK-NEXT: [[C54:%[0-9]+]]:_(i32) = G_CONSTANT i32 4355
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global
; CHECK-NEXT: [[C55:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C56:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C57:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C58:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C59:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C60:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C61:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C62:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C63:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[C64:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[C65:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
- ; CHECK-NEXT: [[C66:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
- ; CHECK-NEXT: [[C67:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
- ; CHECK-NEXT: [[C68:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[C69:%[0-9]+]]:_(s64) = G_CONSTANT i64 13
- ; CHECK-NEXT: [[C70:%[0-9]+]]:_(s64) = G_CONSTANT i64 14
- ; CHECK-NEXT: [[C71:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK-NEXT: [[C72:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[C73:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
- ; CHECK-NEXT: [[C74:%[0-9]+]]:_(s64) = G_CONSTANT i64 18
- ; CHECK-NEXT: [[C75:%[0-9]+]]:_(s64) = G_CONSTANT i64 19
- ; CHECK-NEXT: [[C76:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
- ; CHECK-NEXT: [[C77:%[0-9]+]]:_(s64) = G_CONSTANT i64 21
- ; CHECK-NEXT: [[C78:%[0-9]+]]:_(s64) = G_CONSTANT i64 22
- ; CHECK-NEXT: [[C79:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
- ; CHECK-NEXT: [[C80:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[C81:%[0-9]+]]:_(s64) = G_CONSTANT i64 25
- ; CHECK-NEXT: [[C82:%[0-9]+]]:_(s64) = G_CONSTANT i64 26
- ; CHECK-NEXT: [[C83:%[0-9]+]]:_(s64) = G_CONSTANT i64 27
- ; CHECK-NEXT: [[C84:%[0-9]+]]:_(s64) = G_CONSTANT i64 28
- ; CHECK-NEXT: [[C85:%[0-9]+]]:_(s64) = G_CONSTANT i64 29
- ; CHECK-NEXT: [[C86:%[0-9]+]]:_(s64) = G_CONSTANT i64 30
- ; CHECK-NEXT: [[C87:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
- ; CHECK-NEXT: [[C88:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[C89:%[0-9]+]]:_(s64) = G_CONSTANT i64 33
- ; CHECK-NEXT: [[C90:%[0-9]+]]:_(s64) = G_CONSTANT i64 34
- ; CHECK-NEXT: [[C91:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
- ; CHECK-NEXT: [[C92:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; CHECK-NEXT: [[C93:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C94:%[0-9]+]]:_(s64) = G_CONSTANT i64 38
- ; CHECK-NEXT: [[C95:%[0-9]+]]:_(s64) = G_CONSTANT i64 39
- ; CHECK-NEXT: [[C96:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[C97:%[0-9]+]]:_(s64) = G_CONSTANT i64 41
- ; CHECK-NEXT: [[C98:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[C99:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
- ; CHECK-NEXT: [[C100:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; CHECK-NEXT: [[C101:%[0-9]+]]:_(s64) = G_CONSTANT i64 45
- ; CHECK-NEXT: [[C102:%[0-9]+]]:_(s64) = G_CONSTANT i64 46
- ; CHECK-NEXT: [[C103:%[0-9]+]]:_(s64) = G_CONSTANT i64 47
- ; CHECK-NEXT: [[C104:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[C105:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
- ; CHECK-NEXT: [[C106:%[0-9]+]]:_(s64) = G_CONSTANT i64 50
- ; CHECK-NEXT: [[C107:%[0-9]+]]:_(s64) = G_CONSTANT i64 51
- ; CHECK-NEXT: [[C108:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; CHECK-NEXT: [[C109:%[0-9]+]]:_(s64) = G_CONSTANT i64 53
- ; CHECK-NEXT: [[C110:%[0-9]+]]:_(s64) = G_CONSTANT i64 54
+ ; CHECK-NEXT: [[C56:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C57:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C58:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C59:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C60:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C61:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C62:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C63:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[C64:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[C65:%[0-9]+]]:_(i64) = G_CONSTANT i64 9
+ ; CHECK-NEXT: [[C66:%[0-9]+]]:_(i64) = G_CONSTANT i64 10
+ ; CHECK-NEXT: [[C67:%[0-9]+]]:_(i64) = G_CONSTANT i64 11
+ ; CHECK-NEXT: [[C68:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[C69:%[0-9]+]]:_(i64) = G_CONSTANT i64 13
+ ; CHECK-NEXT: [[C70:%[0-9]+]]:_(i64) = G_CONSTANT i64 14
+ ; CHECK-NEXT: [[C71:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[C72:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[C73:%[0-9]+]]:_(i64) = G_CONSTANT i64 17
+ ; CHECK-NEXT: [[C74:%[0-9]+]]:_(i64) = G_CONSTANT i64 18
+ ; CHECK-NEXT: [[C75:%[0-9]+]]:_(i64) = G_CONSTANT i64 19
+ ; CHECK-NEXT: [[C76:%[0-9]+]]:_(i64) = G_CONSTANT i64 20
+ ; CHECK-NEXT: [[C77:%[0-9]+]]:_(i64) = G_CONSTANT i64 21
+ ; CHECK-NEXT: [[C78:%[0-9]+]]:_(i64) = G_CONSTANT i64 22
+ ; CHECK-NEXT: [[C79:%[0-9]+]]:_(i64) = G_CONSTANT i64 23
+ ; CHECK-NEXT: [[C80:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[C81:%[0-9]+]]:_(i64) = G_CONSTANT i64 25
+ ; CHECK-NEXT: [[C82:%[0-9]+]]:_(i64) = G_CONSTANT i64 26
+ ; CHECK-NEXT: [[C83:%[0-9]+]]:_(i64) = G_CONSTANT i64 27
+ ; CHECK-NEXT: [[C84:%[0-9]+]]:_(i64) = G_CONSTANT i64 28
+ ; CHECK-NEXT: [[C85:%[0-9]+]]:_(i64) = G_CONSTANT i64 29
+ ; CHECK-NEXT: [[C86:%[0-9]+]]:_(i64) = G_CONSTANT i64 30
+ ; CHECK-NEXT: [[C87:%[0-9]+]]:_(i64) = G_CONSTANT i64 31
+ ; CHECK-NEXT: [[C88:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[C89:%[0-9]+]]:_(i64) = G_CONSTANT i64 33
+ ; CHECK-NEXT: [[C90:%[0-9]+]]:_(i64) = G_CONSTANT i64 34
+ ; CHECK-NEXT: [[C91:%[0-9]+]]:_(i64) = G_CONSTANT i64 35
+ ; CHECK-NEXT: [[C92:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; CHECK-NEXT: [[C93:%[0-9]+]]:_(i64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C94:%[0-9]+]]:_(i64) = G_CONSTANT i64 38
+ ; CHECK-NEXT: [[C95:%[0-9]+]]:_(i64) = G_CONSTANT i64 39
+ ; CHECK-NEXT: [[C96:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[C97:%[0-9]+]]:_(i64) = G_CONSTANT i64 41
+ ; CHECK-NEXT: [[C98:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[C99:%[0-9]+]]:_(i64) = G_CONSTANT i64 43
+ ; CHECK-NEXT: [[C100:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; CHECK-NEXT: [[C101:%[0-9]+]]:_(i64) = G_CONSTANT i64 45
+ ; CHECK-NEXT: [[C102:%[0-9]+]]:_(i64) = G_CONSTANT i64 46
+ ; CHECK-NEXT: [[C103:%[0-9]+]]:_(i64) = G_CONSTANT i64 47
+ ; CHECK-NEXT: [[C104:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[C105:%[0-9]+]]:_(i64) = G_CONSTANT i64 49
+ ; CHECK-NEXT: [[C106:%[0-9]+]]:_(i64) = G_CONSTANT i64 50
+ ; CHECK-NEXT: [[C107:%[0-9]+]]:_(i64) = G_CONSTANT i64 51
+ ; CHECK-NEXT: [[C108:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; CHECK-NEXT: [[C109:%[0-9]+]]:_(i64) = G_CONSTANT i64 53
+ ; CHECK-NEXT: [[C110:%[0-9]+]]:_(i64) = G_CONSTANT i64 54
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.tmp
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.56
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.56
; CHECK-NEXT: G_BR %bb.61
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.61.bb:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.62
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.62.bb:
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.63
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.63.bb:
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP3]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.64
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.64.bb:
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP4]](s1), %bb.5
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP4]](i1), %bb.5
; CHECK-NEXT: G_BR %bb.65
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.65.bb:
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C5]]
- ; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.6
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C5]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP5]](i1), %bb.6
; CHECK-NEXT: G_BR %bb.66
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.66.bb:
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C6]]
- ; CHECK-NEXT: G_BRCOND [[ICMP6]](s1), %bb.7
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C6]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP6]](i1), %bb.7
; CHECK-NEXT: G_BR %bb.67
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.67.bb:
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP7]](s1), %bb.8
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP7]](i1), %bb.8
; CHECK-NEXT: G_BR %bb.68
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.68.bb:
- ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C8]]
- ; CHECK-NEXT: G_BRCOND [[ICMP8]](s1), %bb.9
+ ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C8]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP8]](i1), %bb.9
; CHECK-NEXT: G_BR %bb.69
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.69.bb:
- ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C9]]
- ; CHECK-NEXT: G_BRCOND [[ICMP9]](s1), %bb.10
+ ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C9]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP9]](i1), %bb.10
; CHECK-NEXT: G_BR %bb.70
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.70.bb:
- ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C10]]
- ; CHECK-NEXT: G_BRCOND [[ICMP10]](s1), %bb.11
+ ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C10]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP10]](i1), %bb.11
; CHECK-NEXT: G_BR %bb.71
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.71.bb:
- ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C11]]
- ; CHECK-NEXT: G_BRCOND [[ICMP11]](s1), %bb.12
+ ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C11]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP11]](i1), %bb.12
; CHECK-NEXT: G_BR %bb.72
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.72.bb:
- ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C12]]
- ; CHECK-NEXT: G_BRCOND [[ICMP12]](s1), %bb.13
+ ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C12]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP12]](i1), %bb.13
; CHECK-NEXT: G_BR %bb.73
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.73.bb:
- ; CHECK-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C13]]
- ; CHECK-NEXT: G_BRCOND [[ICMP13]](s1), %bb.14
+ ; CHECK-NEXT: [[ICMP13:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C13]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP13]](i1), %bb.14
; CHECK-NEXT: G_BR %bb.74
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.74.bb:
- ; CHECK-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C14]]
- ; CHECK-NEXT: G_BRCOND [[ICMP14]](s1), %bb.15
+ ; CHECK-NEXT: [[ICMP14:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C14]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP14]](i1), %bb.15
; CHECK-NEXT: G_BR %bb.75
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.75.bb:
- ; CHECK-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C15]]
- ; CHECK-NEXT: G_BRCOND [[ICMP15]](s1), %bb.16
+ ; CHECK-NEXT: [[ICMP15:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C15]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP15]](i1), %bb.16
; CHECK-NEXT: G_BR %bb.76
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.76.bb:
- ; CHECK-NEXT: [[ICMP16:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C16]]
- ; CHECK-NEXT: G_BRCOND [[ICMP16]](s1), %bb.17
+ ; CHECK-NEXT: [[ICMP16:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C16]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP16]](i1), %bb.17
; CHECK-NEXT: G_BR %bb.77
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.77.bb:
- ; CHECK-NEXT: [[ICMP17:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C17]]
- ; CHECK-NEXT: G_BRCOND [[ICMP17]](s1), %bb.18
+ ; CHECK-NEXT: [[ICMP17:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C17]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP17]](i1), %bb.18
; CHECK-NEXT: G_BR %bb.78
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.78.bb:
- ; CHECK-NEXT: [[ICMP18:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C18]]
- ; CHECK-NEXT: G_BRCOND [[ICMP18]](s1), %bb.19
+ ; CHECK-NEXT: [[ICMP18:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C18]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP18]](i1), %bb.19
; CHECK-NEXT: G_BR %bb.79
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.79.bb:
- ; CHECK-NEXT: [[ICMP19:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C19]]
- ; CHECK-NEXT: G_BRCOND [[ICMP19]](s1), %bb.20
+ ; CHECK-NEXT: [[ICMP19:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C19]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP19]](i1), %bb.20
; CHECK-NEXT: G_BR %bb.80
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.80.bb:
- ; CHECK-NEXT: [[ICMP20:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C20]]
- ; CHECK-NEXT: G_BRCOND [[ICMP20]](s1), %bb.21
+ ; CHECK-NEXT: [[ICMP20:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C20]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP20]](i1), %bb.21
; CHECK-NEXT: G_BR %bb.81
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.81.bb:
- ; CHECK-NEXT: [[ICMP21:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C21]]
- ; CHECK-NEXT: G_BRCOND [[ICMP21]](s1), %bb.22
+ ; CHECK-NEXT: [[ICMP21:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C21]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP21]](i1), %bb.22
; CHECK-NEXT: G_BR %bb.82
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.82.bb:
- ; CHECK-NEXT: [[ICMP22:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C22]]
- ; CHECK-NEXT: G_BRCOND [[ICMP22]](s1), %bb.23
+ ; CHECK-NEXT: [[ICMP22:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C22]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP22]](i1), %bb.23
; CHECK-NEXT: G_BR %bb.83
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.83.bb:
- ; CHECK-NEXT: [[ICMP23:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C23]]
- ; CHECK-NEXT: G_BRCOND [[ICMP23]](s1), %bb.24
+ ; CHECK-NEXT: [[ICMP23:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C23]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP23]](i1), %bb.24
; CHECK-NEXT: G_BR %bb.84
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.84.bb:
- ; CHECK-NEXT: [[ICMP24:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C24]]
- ; CHECK-NEXT: G_BRCOND [[ICMP24]](s1), %bb.25
+ ; CHECK-NEXT: [[ICMP24:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C24]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP24]](i1), %bb.25
; CHECK-NEXT: G_BR %bb.85
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.85.bb:
- ; CHECK-NEXT: [[ICMP25:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C25]]
- ; CHECK-NEXT: G_BRCOND [[ICMP25]](s1), %bb.26
+ ; CHECK-NEXT: [[ICMP25:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C25]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP25]](i1), %bb.26
; CHECK-NEXT: G_BR %bb.86
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.86.bb:
- ; CHECK-NEXT: [[ICMP26:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C26]]
- ; CHECK-NEXT: G_BRCOND [[ICMP26]](s1), %bb.27
+ ; CHECK-NEXT: [[ICMP26:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C26]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP26]](i1), %bb.27
; CHECK-NEXT: G_BR %bb.87
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.87.bb:
- ; CHECK-NEXT: [[ICMP27:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C27]]
- ; CHECK-NEXT: G_BRCOND [[ICMP27]](s1), %bb.28
+ ; CHECK-NEXT: [[ICMP27:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C27]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP27]](i1), %bb.28
; CHECK-NEXT: G_BR %bb.88
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.88.bb:
- ; CHECK-NEXT: [[ICMP28:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C28]]
- ; CHECK-NEXT: G_BRCOND [[ICMP28]](s1), %bb.29
+ ; CHECK-NEXT: [[ICMP28:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C28]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP28]](i1), %bb.29
; CHECK-NEXT: G_BR %bb.89
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.89.bb:
- ; CHECK-NEXT: [[ICMP29:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C29]]
- ; CHECK-NEXT: G_BRCOND [[ICMP29]](s1), %bb.30
+ ; CHECK-NEXT: [[ICMP29:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C29]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP29]](i1), %bb.30
; CHECK-NEXT: G_BR %bb.90
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.90.bb:
- ; CHECK-NEXT: [[ICMP30:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C30]]
- ; CHECK-NEXT: G_BRCOND [[ICMP30]](s1), %bb.31
+ ; CHECK-NEXT: [[ICMP30:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C30]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP30]](i1), %bb.31
; CHECK-NEXT: G_BR %bb.91
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.91.bb:
- ; CHECK-NEXT: [[ICMP31:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C31]]
- ; CHECK-NEXT: G_BRCOND [[ICMP31]](s1), %bb.32
+ ; CHECK-NEXT: [[ICMP31:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C31]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP31]](i1), %bb.32
; CHECK-NEXT: G_BR %bb.92
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.92.bb:
- ; CHECK-NEXT: [[ICMP32:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C32]]
- ; CHECK-NEXT: G_BRCOND [[ICMP32]](s1), %bb.33
+ ; CHECK-NEXT: [[ICMP32:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C32]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP32]](i1), %bb.33
; CHECK-NEXT: G_BR %bb.93
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.93.bb:
- ; CHECK-NEXT: [[ICMP33:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C33]]
- ; CHECK-NEXT: G_BRCOND [[ICMP33]](s1), %bb.34
+ ; CHECK-NEXT: [[ICMP33:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C33]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP33]](i1), %bb.34
; CHECK-NEXT: G_BR %bb.94
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.94.bb:
- ; CHECK-NEXT: [[ICMP34:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C34]]
- ; CHECK-NEXT: G_BRCOND [[ICMP34]](s1), %bb.35
+ ; CHECK-NEXT: [[ICMP34:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C34]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP34]](i1), %bb.35
; CHECK-NEXT: G_BR %bb.95
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.95.bb:
- ; CHECK-NEXT: [[ICMP35:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C35]]
- ; CHECK-NEXT: G_BRCOND [[ICMP35]](s1), %bb.36
+ ; CHECK-NEXT: [[ICMP35:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C35]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP35]](i1), %bb.36
; CHECK-NEXT: G_BR %bb.96
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.96.bb:
- ; CHECK-NEXT: [[ICMP36:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C36]]
- ; CHECK-NEXT: G_BRCOND [[ICMP36]](s1), %bb.37
+ ; CHECK-NEXT: [[ICMP36:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C36]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP36]](i1), %bb.37
; CHECK-NEXT: G_BR %bb.97
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.97.bb:
- ; CHECK-NEXT: [[ICMP37:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C37]]
- ; CHECK-NEXT: G_BRCOND [[ICMP37]](s1), %bb.38
+ ; CHECK-NEXT: [[ICMP37:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C37]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP37]](i1), %bb.38
; CHECK-NEXT: G_BR %bb.98
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.98.bb:
- ; CHECK-NEXT: [[ICMP38:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C38]]
- ; CHECK-NEXT: G_BRCOND [[ICMP38]](s1), %bb.39
+ ; CHECK-NEXT: [[ICMP38:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C38]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP38]](i1), %bb.39
; CHECK-NEXT: G_BR %bb.99
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.99.bb:
- ; CHECK-NEXT: [[ICMP39:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C39]]
- ; CHECK-NEXT: G_BRCOND [[ICMP39]](s1), %bb.40
+ ; CHECK-NEXT: [[ICMP39:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C39]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP39]](i1), %bb.40
; CHECK-NEXT: G_BR %bb.100
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.100.bb:
- ; CHECK-NEXT: [[ICMP40:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C40]]
- ; CHECK-NEXT: G_BRCOND [[ICMP40]](s1), %bb.41
+ ; CHECK-NEXT: [[ICMP40:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C40]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP40]](i1), %bb.41
; CHECK-NEXT: G_BR %bb.101
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.101.bb:
- ; CHECK-NEXT: [[ICMP41:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C41]]
- ; CHECK-NEXT: G_BRCOND [[ICMP41]](s1), %bb.42
+ ; CHECK-NEXT: [[ICMP41:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C41]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP41]](i1), %bb.42
; CHECK-NEXT: G_BR %bb.102
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.102.bb:
- ; CHECK-NEXT: [[ICMP42:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C42]]
- ; CHECK-NEXT: G_BRCOND [[ICMP42]](s1), %bb.43
+ ; CHECK-NEXT: [[ICMP42:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C42]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP42]](i1), %bb.43
; CHECK-NEXT: G_BR %bb.103
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.103.bb:
- ; CHECK-NEXT: [[ICMP43:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C43]]
- ; CHECK-NEXT: G_BRCOND [[ICMP43]](s1), %bb.44
+ ; CHECK-NEXT: [[ICMP43:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C43]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP43]](i1), %bb.44
; CHECK-NEXT: G_BR %bb.104
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.104.bb:
- ; CHECK-NEXT: [[ICMP44:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C44]]
- ; CHECK-NEXT: G_BRCOND [[ICMP44]](s1), %bb.45
+ ; CHECK-NEXT: [[ICMP44:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C44]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP44]](i1), %bb.45
; CHECK-NEXT: G_BR %bb.105
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.105.bb:
- ; CHECK-NEXT: [[ICMP45:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C45]]
- ; CHECK-NEXT: G_BRCOND [[ICMP45]](s1), %bb.46
+ ; CHECK-NEXT: [[ICMP45:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C45]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP45]](i1), %bb.46
; CHECK-NEXT: G_BR %bb.106
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.106.bb:
- ; CHECK-NEXT: [[ICMP46:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C46]]
- ; CHECK-NEXT: G_BRCOND [[ICMP46]](s1), %bb.47
+ ; CHECK-NEXT: [[ICMP46:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C46]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP46]](i1), %bb.47
; CHECK-NEXT: G_BR %bb.107
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.107.bb:
- ; CHECK-NEXT: [[ICMP47:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C47]]
- ; CHECK-NEXT: G_BRCOND [[ICMP47]](s1), %bb.48
+ ; CHECK-NEXT: [[ICMP47:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C47]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP47]](i1), %bb.48
; CHECK-NEXT: G_BR %bb.108
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.108.bb:
- ; CHECK-NEXT: [[ICMP48:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C48]]
- ; CHECK-NEXT: G_BRCOND [[ICMP48]](s1), %bb.49
+ ; CHECK-NEXT: [[ICMP48:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C48]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP48]](i1), %bb.49
; CHECK-NEXT: G_BR %bb.109
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.109.bb:
- ; CHECK-NEXT: [[ICMP49:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C49]]
- ; CHECK-NEXT: G_BRCOND [[ICMP49]](s1), %bb.50
+ ; CHECK-NEXT: [[ICMP49:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C49]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP49]](i1), %bb.50
; CHECK-NEXT: G_BR %bb.110
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.110.bb:
- ; CHECK-NEXT: [[ICMP50:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C50]]
- ; CHECK-NEXT: G_BRCOND [[ICMP50]](s1), %bb.51
+ ; CHECK-NEXT: [[ICMP50:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C50]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP50]](i1), %bb.51
; CHECK-NEXT: G_BR %bb.111
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.111.bb:
- ; CHECK-NEXT: [[ICMP51:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C51]]
- ; CHECK-NEXT: G_BRCOND [[ICMP51]](s1), %bb.52
+ ; CHECK-NEXT: [[ICMP51:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C51]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP51]](i1), %bb.52
; CHECK-NEXT: G_BR %bb.112
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.112.bb:
- ; CHECK-NEXT: [[ICMP52:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C52]]
- ; CHECK-NEXT: G_BRCOND [[ICMP52]](s1), %bb.53
+ ; CHECK-NEXT: [[ICMP52:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C52]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP52]](i1), %bb.53
; CHECK-NEXT: G_BR %bb.113
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.113.bb:
- ; CHECK-NEXT: [[ICMP53:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C53]]
- ; CHECK-NEXT: G_BRCOND [[ICMP53]](s1), %bb.54
+ ; CHECK-NEXT: [[ICMP53:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C53]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP53]](i1), %bb.54
; CHECK-NEXT: G_BR %bb.114
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.114.bb:
- ; CHECK-NEXT: [[ICMP54:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C54]]
- ; CHECK-NEXT: G_BRCOND [[ICMP54]](s1), %bb.55
+ ; CHECK-NEXT: [[ICMP54:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C54]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP54]](i1), %bb.55
; CHECK-NEXT: G_BR %bb.60
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb3:
@@ -790,12 +790,12 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: G_BR %bb.56
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.56.bb57:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[C56]](s64), %bb.1, [[C57]](s64), %bb.2, [[C58]](s64), %bb.3, [[C59]](s64), %bb.4, [[C60]](s64), %bb.5, [[C61]](s64), %bb.6, [[C62]](s64), %bb.7, [[C63]](s64), %bb.8, [[C64]](s64), %bb.9, [[C65]](s64), %bb.10, [[C66]](s64), %bb.11, [[C67]](s64), %bb.12, [[C68]](s64), %bb.13, [[C69]](s64), %bb.14, [[C70]](s64), %bb.15, [[C71]](s64), %bb.16, [[C72]](s64), %bb.17, [[C73]](s64), %bb.18, [[C74]](s64), %bb.19, [[C75]](s64), %bb.20, [[C76]](s64), %bb.21, [[C77]](s64), %bb.22, [[C78]](s64), %bb.23, [[C79]](s64), %bb.24, [[C80]](s64), %bb.25, [[C81]](s64), %bb.26, [[C82]](s64), %bb.27, [[C83]](s64), %bb.28, [[C84]](s64), %bb.29, [[C85]](s64), %bb.30, [[C86]](s64), %bb.31, [[C87]](s64), %bb.32, [[C88]](s64), %bb.33, [[C89]](s64), %bb.34, [[C90]](s64), %bb.35, [[C91]](s64), %bb.36, [[C92]](s64), %bb.37, [[C93]](s64), %bb.38, [[C94]](s64), %bb.39, [[C95]](s64), %bb.40, [[C96]](s64), %bb.41, [[C97]](s64), %bb.42, [[C98]](s64), %bb.43, [[C99]](s64), %bb.44, [[C100]](s64), %bb.45, [[C101]](s64), %bb.46, [[C102]](s64), %bb.47, [[C103]](s64), %bb.48, [[C104]](s64), %bb.49, [[C105]](s64), %bb.50, [[C106]](s64), %bb.51, [[C107]](s64), %bb.52, [[C108]](s64), %bb.53, [[C109]](s64), %bb.54, [[C110]](s64), %bb.55
- ; CHECK-NEXT: [[C111:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[PHI]], [[C111]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[GV]], [[MUL]](s64)
- ; CHECK-NEXT: [[C112:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C112]](s64)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i64) = G_PHI [[C56]](i64), %bb.1, [[C57]](i64), %bb.2, [[C58]](i64), %bb.3, [[C59]](i64), %bb.4, [[C60]](i64), %bb.5, [[C61]](i64), %bb.6, [[C62]](i64), %bb.7, [[C63]](i64), %bb.8, [[C64]](i64), %bb.9, [[C65]](i64), %bb.10, [[C66]](i64), %bb.11, [[C67]](i64), %bb.12, [[C68]](i64), %bb.13, [[C69]](i64), %bb.14, [[C70]](i64), %bb.15, [[C71]](i64), %bb.16, [[C72]](i64), %bb.17, [[C73]](i64), %bb.18, [[C74]](i64), %bb.19, [[C75]](i64), %bb.20, [[C76]](i64), %bb.21, [[C77]](i64), %bb.22, [[C78]](i64), %bb.23, [[C79]](i64), %bb.24, [[C80]](i64), %bb.25, [[C81]](i64), %bb.26, [[C82]](i64), %bb.27, [[C83]](i64), %bb.28, [[C84]](i64), %bb.29, [[C85]](i64), %bb.30, [[C86]](i64), %bb.31, [[C87]](i64), %bb.32, [[C88]](i64), %bb.33, [[C89]](i64), %bb.34, [[C90]](i64), %bb.35, [[C91]](i64), %bb.36, [[C92]](i64), %bb.37, [[C93]](i64), %bb.38, [[C94]](i64), %bb.39, [[C95]](i64), %bb.40, [[C96]](i64), %bb.41, [[C97]](i64), %bb.42, [[C98]](i64), %bb.43, [[C99]](i64), %bb.44, [[C100]](i64), %bb.45, [[C101]](i64), %bb.46, [[C102]](i64), %bb.47, [[C103]](i64), %bb.48, [[C104]](i64), %bb.49, [[C105]](i64), %bb.50, [[C106]](i64), %bb.51, [[C107]](i64), %bb.52, [[C108]](i64), %bb.53, [[C109]](i64), %bb.54, [[C110]](i64), %bb.55
+ ; CHECK-NEXT: [[C111:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[PHI]], [[C111]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[GV]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C112:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C112]](i64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load (p0) from %ir.tmp59)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
@@ -816,7 +816,7 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.58.bb64:
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]](i32)
; CHECK-NEXT: $x1 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @baz, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $x1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -832,8 +832,8 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.60.bb69:
- ; CHECK-NEXT: [[ICMP55:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](p0), [[C55]]
- ; CHECK-NEXT: G_BRCOND [[ICMP55]](s1), %bb.58
+ ; CHECK-NEXT: [[ICMP55:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY2]](p0), [[C55]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP55]](i1), %bb.58
; CHECK-NEXT: G_BR %bb.57
bb:
%tmp = alloca [16 x i32], align 4
@@ -1092,53 +1092,53 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-LABEL: name: jt_2_tables_phi_edge_from_second
; CHECK: bb.1.entry:
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 123
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 263
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 265
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 270
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 279
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 37
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 43
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 45
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 278
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 280
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 281
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 283
- ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef`, align 8)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.6
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 123
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 263
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 265
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 270
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 279
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 37
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 43
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 45
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 60
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 278
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 280
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 281
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i32) = G_CONSTANT i32 283
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(i1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[DEF]](p0) :: (load (i32) from `ptr undef`, align 8)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.6
; CHECK-NEXT: G_BR %bb.19
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.19.entry:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.20
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.20.entry:
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.7
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.7
; CHECK-NEXT: G_BR %bb.21
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.21.entry:
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP3]](s1), %bb.2
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.22
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.22.entry:
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP4]](s1), %bb.5
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP4]](i1), %bb.5
; CHECK-NEXT: G_BR %bb.23
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.23.entry:
@@ -1160,43 +1160,43 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C5]]
- ; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.10
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C5]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP5]](i1), %bb.10
; CHECK-NEXT: G_BR %bb.24
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.24.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C6]]
- ; CHECK-NEXT: G_BRCOND [[ICMP6]](s1), %bb.16
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C6]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP6]](i1), %bb.16
; CHECK-NEXT: G_BR %bb.25
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.25.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP7]](s1), %bb.9
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP7]](i1), %bb.9
; CHECK-NEXT: G_BR %bb.26
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.26.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C8]]
- ; CHECK-NEXT: G_BRCOND [[ICMP8]](s1), %bb.14
+ ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C8]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP8]](i1), %bb.14
; CHECK-NEXT: G_BR %bb.27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.27.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C9]]
- ; CHECK-NEXT: G_BRCOND [[ICMP9]](s1), %bb.11
+ ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C9]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP9]](i1), %bb.11
; CHECK-NEXT: G_BR %bb.28
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.28.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C10]]
- ; CHECK-NEXT: G_BRCOND [[ICMP10]](s1), %bb.13
+ ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C10]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP10]](i1), %bb.13
; CHECK-NEXT: G_BR %bb.29
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.29.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C11]]
- ; CHECK-NEXT: G_BRCOND [[ICMP11]](s1), %bb.15
+ ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C11]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP11]](i1), %bb.15
; CHECK-NEXT: G_BR %bb.30
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.30.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C12]]
- ; CHECK-NEXT: G_BRCOND [[ICMP12]](s1), %bb.12
+ ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C12]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP12]](i1), %bb.12
; CHECK-NEXT: G_BR %bb.18
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.sw.default.i49:
@@ -1224,8 +1224,8 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: G_BR %bb.16
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.16.land.rhs.lr.ph:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C13]](s32), %bb.24, [[C14]](s32), %bb.9, [[C15]](s32), %bb.10, [[C16]](s32), %bb.11, [[C17]](s32), %bb.12, [[C18]](s32), %bb.13, [[C19]](s32), %bb.14, [[C20]](s32), %bb.15
- ; CHECK-NEXT: G_BRCOND [[DEF2]](s1), %bb.17
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C13]](i32), %bb.24, [[C14]](i32), %bb.9, [[C15]](i32), %bb.10, [[C16]](i32), %bb.11, [[C17]](i32), %bb.12, [[C18]](i32), %bb.13, [[C19]](i32), %bb.14, [[C20]](i32), %bb.15
+ ; CHECK-NEXT: G_BRCOND [[DEF2]](i1), %bb.17
; CHECK-NEXT: G_BR %bb.18
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.17.while.body:
@@ -1236,7 +1236,7 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.18.while.end:
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C21]](s32), %bb.30, [[PHI]](s32), %bb.16
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(i32) = G_PHI [[C21]](i32), %bb.30, [[PHI]](i32), %bb.16
; CHECK-NEXT: RET_ReallyLR
entry:
%0 = load i32, ptr undef, align 8
@@ -1319,34 +1319,34 @@ define i32 @range_test(i32 %x) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[SUB]](s32), [[C5]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ule), [[SUB]](i32), [[C5]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.bb:
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C3]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = nsw G_ADD [[COPY]], [[C3]]
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.sw.bb1:
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i32) = nsw G_MUL [[COPY]], [[C2]]
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.return:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C4]](s32), %bb.5
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[MUL]](i32), %bb.3, [[ADD]](i32), %bb.2, [[C4]](i32), %bb.5
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %x, label %return [
@@ -1372,29 +1372,29 @@ return:
define ptr @test_range_phi_switch_cycle() {
; CHECK-LABEL: name: test_range_phi_switch_cycle
; CHECK: bb.1.bb:
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 305
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 307
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 497
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 305
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 307
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 497
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb1:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[DEF]](s32), %bb.1, [[C3]](s32), %bb.3, [[C4]](s32), %bb.4, [[C5]](s32), %bb.2
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[DEF]](i32), %bb.1, [[C3]](i32), %bb.3, [[C4]](i32), %bb.4, [[C5]](i32), %bb.2
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.bb1:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.bb1:
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF]](s32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.bb2:
@@ -1405,7 +1405,7 @@ define ptr @test_range_phi_switch_cycle() {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.bb4:
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: BL @ham, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
@@ -1444,14 +1444,14 @@ define i1 @i1_value_cmp_is_signed(i1) {
; CHECK: bb.1.Entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC]], 1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[TRUNC1]](s1), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC]], 1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(sle), [[TRUNC1]](i1), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.BadValue:
@@ -1462,9 +1462,9 @@ define i1 @i1_value_cmp_is_signed(i1) {
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.OkValue:
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC1]](s1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[TRUNC1]](i1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
Entry:
switch i1 %0, label %BadValue [
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index c68ae925d4295..d54a0581ceac8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CV
; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CI
; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
@@ -9,9 +10,9 @@ target triple = "aarch64--"
; Tests for add.
; CHECK-LABEL: name: addi64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_ADD [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @addi64(i64 %arg1, i64 %arg2) {
@@ -20,9 +21,9 @@ define i64 @addi64(i64 %arg1, i64 %arg2) {
}
; CHECK-LABEL: name: muli64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_MUL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_MUL [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @muli64(i64 %arg1, i64 %arg2) {
@@ -110,8 +111,8 @@ end:
; CHECK: [[ADDR:%.*]]:_(p0) = COPY $x0
;
; Check that we emit the correct branch.
-; CHECK: [[TST:%.*]]:_(s1) = G_LOAD [[ADDR]](p0)
-; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
+; CHECK: [[TST:%.*]]:_(i1) = G_LOAD [[ADDR]](p0)
+; CHECK: G_BRCOND [[TST]](i1), %[[TRUE]]
; CHECK: G_BR %[[FALSE]]
;
; Check that each successor contains the return instruction.
@@ -165,9 +166,9 @@ L2: ; preds = %L1
; Tests for or.
; CHECK-LABEL: name: ori64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_OR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_OR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @ori64(i64 %arg1, i64 %arg2) {
@@ -176,9 +177,9 @@ define i64 @ori64(i64 %arg1, i64 %arg2) {
}
; CHECK-LABEL: name: ori32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_OR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_OR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @ori32(i32 %arg1, i32 %arg2) {
@@ -188,9 +189,9 @@ define i32 @ori32(i32 %arg1, i32 %arg2) {
; Tests for xor.
; CHECK-LABEL: name: xori64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_XOR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_XOR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @xori64(i64 %arg1, i64 %arg2) {
@@ -198,10 +199,11 @@ define i64 @xori64(i64 %arg1, i64 %arg2) {
ret i64 %res
}
+
; CHECK-LABEL: name: xori32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_XOR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_XOR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @xori32(i32 %arg1, i32 %arg2) {
@@ -211,9 +213,9 @@ define i32 @xori32(i32 %arg1, i32 %arg2) {
; Tests for and.
; CHECK-LABEL: name: andi64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_AND [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_AND [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @andi64(i64 %arg1, i64 %arg2) {
@@ -222,9 +224,9 @@ define i64 @andi64(i64 %arg1, i64 %arg2) {
}
; CHECK-LABEL: name: andi32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_AND [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_AND [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @andi32(i32 %arg1, i32 %arg2) {
@@ -234,9 +236,9 @@ define i32 @andi32(i32 %arg1, i32 %arg2) {
; Tests for sub.
; CHECK-LABEL: name: subi64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_SUB [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @subi64(i64 %arg1, i64 %arg2) {
@@ -245,9 +247,9 @@ define i64 @subi64(i64 %arg1, i64 %arg2) {
}
; CHECK-LABEL: name: subi32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_SUB [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @subi32(i32 %arg1, i32 %arg2) {
@@ -257,7 +259,7 @@ define i32 @subi32(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: ptrtoint
; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[ARG1]]
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_PTRTOINT [[ARG1]]
; CHECK: $x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit $x0
define i64 @ptrtoint(ptr %a) {
@@ -266,7 +268,7 @@ define i64 @ptrtoint(ptr %a) {
}
; CHECK-LABEL: name: inttoptr
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
; CHECK: [[RES:%[0-9]+]]:_(p0) = G_INTTOPTR [[ARG1]]
; CHECK: $x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit $x0
@@ -284,7 +286,7 @@ define ptr @trivial_bitcast(ptr %a) {
}
; CHECK-LABEL: name: trivial_bitcast_with_copy
-; CHECK: [[A:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK: [[A:%[0-9]+]]:_(i64) = COPY $x0
; CHECK: G_BR %[[CAST:bb\.[0-9]+]]
; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}:
@@ -292,21 +294,21 @@ define ptr @trivial_bitcast(ptr %a) {
; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}:
; CHECK: G_BR %[[END]]
-define i64 @trivial_bitcast_with_copy(double %a) {
+define i64 @trivial_bitcast_with_copy(i64 %a) {
br label %cast
end:
ret i64 %val
cast:
- %val = bitcast double %a to i64
+ %val = bitcast i64 %a to i64
br label %end
}
; CHECK-LABEL: name: bitcast
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[RES1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[ARG1]]
-; CHECK: [[RES2:%[0-9]+]]:_(s64) = G_BITCAST [[RES1]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[RES1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(i64) = G_BITCAST [[RES1]]
; CHECK: $x0 = COPY [[RES2]]
; CHECK: RET_ReallyLR implicit $x0
define i64 @bitcast(i64 %a) {
@@ -328,10 +330,10 @@ define ptr @addrspacecast(ptr addrspace(1) %a) {
}
; CHECK-LABEL: name: trunc
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_LOAD
-; CHECK: [[RES1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1]]
-; CHECK: [[RES2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[VEC]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x i32>) = G_LOAD
+; CHECK: [[RES1:%[0-9]+]]:_(i8) = G_TRUNC [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(<4 x i16>) = G_TRUNC [[VEC]]
define void @trunc(i64 %a) {
%vecptr = alloca <4 x i32>
%vec = load <4 x i32>, ptr %vecptr
@@ -343,13 +345,13 @@ define void @trunc(i64 %a) {
; CHECK-LABEL: name: load
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY $x1
-; CHECK: [[VAL1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr, align 16)
-; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load (s64) from %ir.addr42, addrspace 42)
-; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]
-; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load (s64) from %ir.addr)
-; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]
-; CHECK: [[VAL4:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr, !range !0)
-; CHECK: [[SUM4:%[0-9]+]]:_(s64) = G_ADD [[SUM3]], [[VAL4]]
+; CHECK: [[VAL1:%[0-9]+]]:_(i64) = G_LOAD [[ADDR]](p0) :: (load (i64) from %ir.addr, align 16)
+; CHECK: [[VAL2:%[0-9]+]]:_(i64) = G_LOAD [[ADDR42]](p42) :: (load (i64) from %ir.addr42, addrspace 42)
+; CHECK: [[SUM2:%.*]]:_(i64) = G_ADD [[VAL1]], [[VAL2]]
+; CHECK: [[VAL3:%[0-9]+]]:_(i64) = G_LOAD [[ADDR]](p0) :: (volatile load (i64) from %ir.addr)
+; CHECK: [[SUM3:%[0-9]+]]:_(i64) = G_ADD [[SUM2]], [[VAL3]]
+; CHECK: [[VAL4:%[0-9]+]]:_(i64) = G_LOAD [[ADDR]](p0) :: (load (i64) from %ir.addr, !range !0)
+; CHECK: [[SUM4:%[0-9]+]]:_(i64) = G_ADD [[SUM3]], [[VAL4]]
; CHECK: $x0 = COPY [[SUM4]]
; CHECK: RET_ReallyLR implicit $x0
define i64 @load(ptr %addr, ptr addrspace(42) %addr42) {
@@ -369,11 +371,11 @@ define i64 @load(ptr %addr, ptr addrspace(42) %addr42) {
; CHECK-LABEL: name: store
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY $x1
-; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY $x3
-; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store (s64) into %ir.addr, align 16)
-; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store (s64) into %ir.addr42, addrspace 42)
-; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store (s64) into %ir.addr)
+; CHECK: [[VAL1:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: [[VAL2:%[0-9]+]]:_(i64) = COPY $x3
+; CHECK: G_STORE [[VAL1]](i64), [[ADDR]](p0) :: (store (i64) into %ir.addr, align 16)
+; CHECK: G_STORE [[VAL2]](i64), [[ADDR42]](p42) :: (store (i64) into %ir.addr42, addrspace 42)
+; CHECK: G_STORE [[VAL1]](i64), [[ADDR]](p0) :: (volatile store (i64) into %ir.addr)
; CHECK: RET_ReallyLR
define void @store(ptr %addr, ptr addrspace(42) %addr42, i64 %val1, i64 %val2) {
store i64 %val1, ptr %addr, align 16
@@ -384,12 +386,12 @@ define void @store(ptr %addr, ptr addrspace(42) %addr42, i64 %val1, i64 %val2) {
}
; CHECK-LABEL: name: intrinsics
-; CHECK: [[CUR:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[BITS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[CUR:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[BITS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
; CHECK: [[PTR_VEC:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr.vec
-; CHECK: [[VEC:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[PTR_VEC]]
-; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x s8>), [[VEC]](<8 x s8>), [[PTR]](p0)
+; CHECK: [[VEC:%[0-9]+]]:_(<8 x i8>) = G_LOAD [[PTR_VEC]]
+; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x i8>), [[VEC]](<8 x i8>), [[PTR]](p0)
; CHECK: RET_ReallyLR
declare ptr @llvm.returnaddress(i32)
declare void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8>, <8 x i8>, ptr)
@@ -407,12 +409,12 @@ define void @intrinsics(i32 %cur, i32 %bits) {
; CHECK: G_BR %[[FALSE:bb\.[0-9]+]]
; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:
-; CHECK: [[RES1:%[0-9]+]]:_(s32) = G_LOAD
+; CHECK: [[RES1:%[0-9]+]]:_(i32) = G_LOAD
; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:
-; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_LOAD
+; CHECK: [[RES2:%[0-9]+]]:_(i32) = G_LOAD
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_PHI [[RES1]](i32), %[[TRUE]], [[RES2]](i32), %[[FALSE]]
; CHECK: $w0 = COPY [[RES]]
define i32 @test_phi(ptr %addr1, ptr %addr2, i1 %tst) {
br i1 %tst, label %true, label %false
@@ -441,13 +443,13 @@ define void @unreachable(i32 %a) {
; It's important that constants are after argument passing, but before the
; rest of the entry block.
; CHECK-LABEL: name: constant_int
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[ONE:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
-; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
-; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]
+; CHECK: [[SUM1:%[0-9]+]]:_(i32) = G_ADD [[IN]], [[ONE]]
+; CHECK: [[SUM2:%[0-9]+]]:_(i32) = G_ADD [[IN]], [[ONE]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_ADD [[SUM1]], [[SUM2]]
; CHECK: $w0 = COPY [[RES]]
define i32 @constant_int(i32 %in) {
@@ -461,23 +463,23 @@ next:
}
; CHECK-LABEL: name: constant_int_start
-; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
+; CHECK: [[TWO:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+; CHECK: [[ANSWER:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CONSTANT i32 44
define i32 @constant_int_start() {
%res = add i32 2, 42
ret i32 %res
}
; CHECK-LABEL: name: test_undef
-; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+; CHECK: [[UNDEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
; CHECK: $w0 = COPY [[UNDEF]]
define i32 @test_undef() {
ret i32 undef
}
; CHECK-LABEL: name: test_constant_inttoptr
-; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK: [[ONE:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ONE]]
; CHECK: $x0 = COPY [[PTR]]
define ptr @test_constant_inttoptr() {
@@ -487,15 +489,15 @@ define ptr @test_constant_inttoptr() {
; This failed purely because the Constant -> VReg map was kept across
; functions, so reuse the "i64 1" from above.
; CHECK-LABEL: name: test_reused_constant
-; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK: [[ONE:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK: $x0 = COPY [[ONE]]
define i64 @test_reused_constant() {
ret i64 1
}
; CHECK-LABEL: name: test_sext
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SEXT [[IN]]
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_SEXT [[IN]]
; CHECK: $x0 = COPY [[RES]]
define i64 @test_sext(i32 %in) {
%res = sext i32 %in to i64
@@ -503,8 +505,8 @@ define i64 @test_sext(i32 %in) {
}
; CHECK-LABEL: name: test_zext
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ZEXT [[IN]]
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_ZEXT [[IN]]
; CHECK: $x0 = COPY [[RES]]
define i64 @test_zext(i32 %in) {
%res = zext i32 %in to i64
@@ -512,9 +514,9 @@ define i64 @test_zext(i32 %in) {
}
; CHECK-LABEL: name: test_shl
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SHL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_SHL [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_shl(i32 %arg1, i32 %arg2) {
@@ -524,9 +526,9 @@ define i32 @test_shl(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: test_lshr
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_LSHR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_LSHR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_lshr(i32 %arg1, i32 %arg2) {
@@ -535,9 +537,9 @@ define i32 @test_lshr(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_ashr
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_ASHR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_ASHR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_ashr(i32 %arg1, i32 %arg2) {
@@ -546,9 +548,9 @@ define i32 @test_ashr(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_sdiv
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_SDIV [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
@@ -557,9 +559,9 @@ define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_udiv
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_UDIV [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_udiv(i32 %arg1, i32 %arg2) {
@@ -568,9 +570,9 @@ define i32 @test_udiv(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_srem
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_SREM [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_srem(i32 %arg1, i32 %arg2) {
@@ -579,9 +581,9 @@ define i32 @test_srem(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_urem
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_UREM [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_urem(i32 %arg1, i32 %arg2) {
@@ -598,13 +600,13 @@ define ptr @test_constant_null() {
; CHECK-LABEL: name: test_struct_memops
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)
-; CHECK: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load (s32) from %ir.addr + 4)
-; CHECK: G_STORE [[VAL1]](s8), [[ADDR]](p0) :: (store (s8) into %ir.addr, align 4)
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)
-; CHECK: G_STORE [[VAL2]](s32), [[GEP2]](p0) :: (store (s32) into %ir.addr + 4)
+; CHECK: [[VAL1:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](i64)
+; CHECK: [[VAL2:%[0-9]+]]:_(i32) = G_LOAD [[GEP1]](p0) :: (load (i32) from %ir.addr + 4)
+; CHECK: G_STORE [[VAL1]](i8), [[ADDR]](p0) :: (store (i8) into %ir.addr, align 4)
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](i64)
+; CHECK: G_STORE [[VAL2]](i32), [[GEP2]](p0) :: (store (i32) into %ir.addr + 4)
define void @test_struct_memops(ptr %addr) {
%val = load { i8, i32 }, ptr %addr
store { i8, i32 } %val, ptr %addr
@@ -613,8 +615,8 @@ define void @test_struct_memops(ptr %addr) {
; CHECK-LABEL: name: test_i1_memops
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL:%[0-9]+]]:_(s1) = G_LOAD [[ADDR]](p0) :: (load (s1) from %ir.addr)
-; CHECK: G_STORE [[VAL]](s1), [[ADDR]](p0) :: (store (s1) into %ir.addr)
+; CHECK: [[VAL:%[0-9]+]]:_(i1) = G_LOAD [[ADDR]](p0) :: (load (i1) from %ir.addr)
+; CHECK: G_STORE [[VAL]](i1), [[ADDR]](p0) :: (store (i1) into %ir.addr)
define void @test_i1_memops(ptr %addr) {
%val = load i1, ptr %addr
store i1 %val, ptr %addr
@@ -622,11 +624,11 @@ define void @test_i1_memops(ptr %addr) {
}
; CHECK-LABEL: name: int_comparison
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
-; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LHS]](i32), [[RHS]]
+; CHECK: G_STORE [[TST]](i1), [[ADDR]](p0)
define void @int_comparison(i32 %a, i32 %b, ptr %addr) {
%res = icmp ne i32 %a, %b
store i1 %res, ptr %addr
@@ -637,8 +639,8 @@ define void @int_comparison(i32 %a, i32 %b, ptr %addr) {
; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
-; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
+; CHECK: G_STORE [[TST]](i1), [[ADDR]](p0)
define void @ptr_comparison(ptr %a, ptr %b, ptr %addr) {
%res = icmp eq ptr %a, %b
store i1 %res, ptr %addr
@@ -646,9 +648,9 @@ define void @ptr_comparison(ptr %a, ptr %b, ptr %addr) {
}
; CHECK-LABEL: name: test_fadd
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FADD [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FADD [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_fadd(float %arg1, float %arg2) {
@@ -657,9 +659,9 @@ define float @test_fadd(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_fsub
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FSUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FSUB [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_fsub(float %arg1, float %arg2) {
@@ -668,9 +670,9 @@ define float @test_fsub(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_fmul
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FMUL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FMUL [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_fmul(float %arg1, float %arg2) {
@@ -679,9 +681,9 @@ define float @test_fmul(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_fdiv
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FDIV [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_fdiv(float %arg1, float %arg2) {
@@ -690,9 +692,9 @@ define float @test_fdiv(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_frem
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FREM [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_frem(float %arg1, float %arg2) {
@@ -701,14 +703,14 @@ define float @test_frem(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_sadd_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SADDO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_SADDO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.addr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.addr + 4, align 4)
declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
define void @test_sadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
%res = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -717,14 +719,14 @@ define void @test_sadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
}
; CHECK-LABEL: name: test_uadd_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UADDO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_UADDO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.addr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.addr + 4, align 4)
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
define void @test_uadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
%res = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -733,14 +735,14 @@ define void @test_uadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
}
; CHECK-LABEL: name: test_ssub_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SSUBO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.subr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.subr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_SSUBO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.subr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.subr + 4, align 4)
declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)
define void @test_ssub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {
%res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -749,14 +751,14 @@ define void @test_ssub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {
}
; CHECK-LABEL: name: test_usub_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_USUBO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.subr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.subr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_USUBO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.subr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.subr + 4, align 4)
declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)
define void @test_usub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {
%res = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -765,14 +767,14 @@ define void @test_usub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {
}
; CHECK-LABEL: name: test_smul_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SMULO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_SMULO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.addr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.addr + 4, align 4)
declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
define void @test_smul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
%res = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -781,14 +783,14 @@ define void @test_smul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
}
; CHECK-LABEL: name: test_umul_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UMULO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_UMULO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.addr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.addr + 4, align 4)
declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
define void @test_umul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
%res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -798,17 +800,17 @@ define void @test_umul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
; CHECK-LABEL: name: test_extractvalue
; CHECK: %0:_(p0) = COPY $x0
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)
-; CHECK: $w0 = COPY [[LD3]](s32)
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i8) = G_LOAD [[GEP1]](p0) :: (load (i8) from %ir.addr + 4, align 4)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.addr + 8)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i32) = G_LOAD [[GEP3]](p0) :: (load (i32) from %ir.addr + 12)
+; CHECK: $w0 = COPY [[LD3]](i32)
%struct.nested = type {i8, { i8, i32 }, i32}
define i32 @test_extractvalue(ptr %addr) {
%struct = load %struct.nested, ptr %addr
@@ -819,19 +821,19 @@ define i32 @test_extractvalue(ptr %addr) {
; CHECK-LABEL: name: test_extractvalue_agg
; CHECK: %0:_(p0) = COPY $x0
; CHECK: %1:_(p0) = COPY $x1
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)
-; CHECK: G_STORE [[LD2]](s8), %1(p0) :: (store (s8) into %ir.addr2, align 4)
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](s64)
-; CHECK: G_STORE [[LD3]](s32), [[GEP4]](p0) :: (store (s32) into %ir.addr2 + 4)
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i8) = G_LOAD [[GEP1]](p0) :: (load (i8) from %ir.addr + 4, align 4)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.addr + 8)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i32) = G_LOAD [[GEP3]](p0) :: (load (i32) from %ir.addr + 12)
+; CHECK: G_STORE [[LD2]](i8), %1(p0) :: (store (i8) into %ir.addr2, align 4)
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](i64)
+; CHECK: G_STORE [[LD3]](i32), [[GEP4]](p0) :: (store (i32) into %ir.addr2 + 4)
define void @test_extractvalue_agg(ptr %addr, ptr %addr2) {
%struct = load %struct.nested, ptr %addr
%res = extractvalue %struct.nested %struct, 1
@@ -841,9 +843,9 @@ define void @test_extractvalue_agg(ptr %addr, ptr %addr2) {
; CHECK-LABEL: name: test_trivial_extract_ptr
; CHECK: [[STRUCT:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL32:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_TRUNC [[VAL32]]
-; CHECK: G_STORE [[VAL]](s8), [[STRUCT]](p0)
+; CHECK: [[VAL32:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[VAL:%[0-9]+]]:_(i8) = G_TRUNC [[VAL32]]
+; CHECK: G_STORE [[VAL]](i8), [[STRUCT]](p0)
define void @test_trivial_extract_ptr([1 x ptr] %s, i8 %val) {
%addr = extractvalue [1 x ptr] %s, 0
store i8 %val, ptr %addr
@@ -852,24 +854,24 @@ define void @test_trivial_extract_ptr([1 x ptr] %s, i8 %val) {
; CHECK-LABEL: name: test_insertvalue
; CHECK: %0:_(p0) = COPY $x0
-; CHECK: %1:_(s32) = COPY $w1
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)
-; CHECK: G_STORE [[LD1]](s8), %0(p0) :: (store (s8) into %ir.addr, align 4)
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: G_STORE [[LD2]](s8), [[GEP4]](p0) :: (store (s8) into %ir.addr + 4, align 4)
-; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: G_STORE %1(s32), [[GEP5]](p0) :: (store (s32) into %ir.addr + 8)
-; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: G_STORE [[LD4]](s32), [[GEP6]](p0) :: (store (s32) into %ir.addr + 12)
+; CHECK: %1:_(i32) = COPY $w1
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i8) = G_LOAD [[GEP1]](p0) :: (load (i8) from %ir.addr + 4, align 4)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.addr + 8)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i32) = G_LOAD [[GEP3]](p0) :: (load (i32) from %ir.addr + 12)
+; CHECK: G_STORE [[LD1]](i8), %0(p0) :: (store (i8) into %ir.addr, align 4)
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: G_STORE [[LD2]](i8), [[GEP4]](p0) :: (store (i8) into %ir.addr + 4, align 4)
+; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: G_STORE %1(i32), [[GEP5]](p0) :: (store (i32) into %ir.addr + 8)
+; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: G_STORE [[LD4]](i32), [[GEP6]](p0) :: (store (i32) into %ir.addr + 12)
define void @test_insertvalue(ptr %addr, i32 %val) {
%struct = load %struct.nested, ptr %addr
%newstruct = insertvalue %struct.nested %struct, i32 %val, 1, 1
@@ -879,8 +881,8 @@ define void @test_insertvalue(ptr %addr, i32 %val) {
define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {
; CHECK-LABEL: name: test_trivial_insert
-; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[VAL:%[0-9]+]]:_(s64) = COPY $x1
+; CHECK: [[STRUCT:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[VAL:%[0-9]+]]:_(i64) = COPY $x1
; CHECK: $x0 = COPY [[VAL]]
%res = insertvalue [1 x i64] %s, i64 %val, 0
ret [1 x i64] %res
@@ -898,26 +900,26 @@ define [1 x ptr] @test_trivial_insert_ptr([1 x ptr] %s, ptr %val) {
; CHECK-LABEL: name: test_insertvalue_agg
; CHECK: %0:_(p0) = COPY $x0
; CHECK: %1:_(p0) = COPY $x1
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %1(p0) :: (load (s8) from %ir.addr2, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load (s32) from %ir.addr2 + 4)
-; CHECK: [[LD3:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[GEP2]](p0) :: (load (s8) from %ir.addr + 4, align 4)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD5:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 8)
-; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](s64)
-; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load (s32) from %ir.addr + 12)
-; CHECK: G_STORE [[LD3]](s8), %0(p0) :: (store (s8) into %ir.addr, align 4)
-; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: G_STORE [[LD1]](s8), [[GEP5]](p0) :: (store (s8) into %ir.addr + 4, align 4)
-; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: G_STORE [[LD2]](s32), [[GEP6]](p0) :: (store (s32) into %ir.addr + 8)
-; CHECK: [[GEP7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](s64)
-; CHECK: G_STORE [[LD6]](s32), [[GEP7]](p0) :: (store (s32) into %ir.addr + 12)
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD %1(p0) :: (load (i8) from %ir.addr2, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i32) = G_LOAD [[GEP1]](p0) :: (load (i32) from %ir.addr2 + 4)
+; CHECK: [[LD3:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i8) = G_LOAD [[GEP2]](p0) :: (load (i8) from %ir.addr + 4, align 4)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD5:%[0-9]+]]:_(i32) = G_LOAD [[GEP3]](p0) :: (load (i32) from %ir.addr + 8)
+; CHECK: [[CST4:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](i64)
+; CHECK: [[LD6:%[0-9]+]]:_(i32) = G_LOAD [[GEP4]](p0) :: (load (i32) from %ir.addr + 12)
+; CHECK: G_STORE [[LD3]](i8), %0(p0) :: (store (i8) into %ir.addr, align 4)
+; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: G_STORE [[LD1]](i8), [[GEP5]](p0) :: (store (i8) into %ir.addr + 4, align 4)
+; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: G_STORE [[LD2]](i32), [[GEP6]](p0) :: (store (i32) into %ir.addr + 8)
+; CHECK: [[GEP7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](i64)
+; CHECK: G_STORE [[LD6]](i32), [[GEP7]](p0) :: (store (i32) into %ir.addr + 12)
define void @test_insertvalue_agg(ptr %addr, ptr %addr2) {
%smallstruct = load {i8, i32}, ptr %addr2
%struct = load %struct.nested, ptr %addr
@@ -927,13 +929,13 @@ define void @test_insertvalue_agg(ptr %addr, ptr %addr2) {
}
; CHECK-LABEL: name: test_select
-; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w2
-; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[TSTEXT:%[0-9]+]]:_(i8) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w2
+; CHECK: [[TSTASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TSTEXT]], 1
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_TRUNC [[TSTASSERT]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_SELECT [[TST]](i1), [[LHS]], [[RHS]]
; CHECK: $w0 = COPY [[RES]]
define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
%res = select i1 %tst, i32 %lhs, i32 %rhs
@@ -941,13 +943,13 @@ define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
}
; CHECK-LABEL: name: test_select_flags
-; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]]
-; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC8]], 1
-; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNCASSERT]]
-; CHECK: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+; CHECK: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[TRUNC8:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]]
+; CHECK: [[COPY1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[COPY2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC8]], 1
+; CHECK: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[TRUNCASSERT]]
+; CHECK: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[TRUNC]](i1), [[COPY1]], [[COPY2]]
define float @test_select_flags(i1 %tst, float %lhs, float %rhs) {
%res = select nnan i1 %tst, float %lhs, float %rhs
ret float %res
@@ -955,12 +957,12 @@ define float @test_select_flags(i1 %tst, float %lhs, float %rhs) {
; Don't take the flags from the compare condition
; CHECK-LABEL: name: test_select_cmp_flags
-; CHECK: [[COPY0:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
-; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s3
-; CHECK: [[CMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(oeq), [[COPY0]](s32), [[COPY1]]
-; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[COPY2]], [[COPY3]]
+; CHECK: [[COPY0:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
+; CHECK: [[COPY3:%[0-9]+]]:_(f32) = COPY $s3
+; CHECK: [[CMP:%[0-9]+]]:_(i1) = nsz G_FCMP floatpred(oeq), [[COPY0]](f32), [[COPY1]]
+; CHECK: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[CMP]](i1), [[COPY2]], [[COPY3]]
define float @test_select_cmp_flags(float %cmp0, float %cmp1, float %lhs, float %rhs) {
%tst = fcmp nsz oeq float %cmp0, %cmp1
%res = select i1 %tst, float %lhs, float %rhs
@@ -968,13 +970,13 @@ define float @test_select_cmp_flags(float %cmp0, float %cmp1, float %lhs, float
}
; CHECK-LABEL: name: test_select_ptr
-; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]
+; CHECK: [[TST_C:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[TSTEXT:%[0-9]+]]:_(i8) = G_TRUNC [[TST_C]]
; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]
-; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TSTASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TSTEXT]], 1
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_TRUNC [[TSTASSERT]]
+; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](i1), [[LHS]], [[RHS]]
; CHECK: $x0 = COPY [[RES]]
define ptr @test_select_ptr(i1 %tst, ptr %lhs, ptr %rhs) {
%res = select i1 %tst, ptr %lhs, ptr %rhs
@@ -982,13 +984,13 @@ define ptr @test_select_ptr(i1 %tst, ptr %lhs, ptr %rhs) {
}
; CHECK-LABEL: name: test_select_vec
-; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]
-; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY $q0
-; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY $q1
-; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]
-; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[TSTEXT:%[0-9]+]]:_(i8) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+; CHECK: [[RHS:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+; CHECK: [[TSTASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TSTEXT]], 1
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_TRUNC [[TSTASSERT]]
+; CHECK: [[RES:%[0-9]+]]:_(<4 x i32>) = G_SELECT [[TST]](i1), [[LHS]], [[RHS]]
; CHECK: $q0 = COPY [[RES]]
define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
%res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs
@@ -996,11 +998,11 @@ define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
}
; CHECK-LABEL: name: test_vselect_vec
-; CHECK: [[TST32:%[0-9]+]]:_(<4 x s32>) = COPY $q0
-; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY $q1
-; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY $q2
-; CHECK: [[TST:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
-; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
+; CHECK: [[TST32:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+; CHECK: [[LHS:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+; CHECK: [[RHS:%[0-9]+]]:_(<4 x i32>) = COPY $q2
+; CHECK: [[TST:%[0-9]+]]:_(<4 x i1>) = G_TRUNC [[TST32]](<4 x i32>)
+; CHECK: [[RES:%[0-9]+]]:_(<4 x i32>) = G_SELECT [[TST]](<4 x i1>), [[LHS]], [[RHS]]
; CHECK: $q0 = COPY [[RES]]
define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %rhs) {
%tst = trunc <4 x i32> %tst32 to <4 x i1>
@@ -1010,8 +1012,8 @@ define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %
; CHECK-LABEL: name: test_fptosi
; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOSI [[FP]](s32)
+; CHECK: [[FP:%[0-9]+]]:_(f32) = G_LOAD [[FPADDR]](p0)
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_FPTOSI [[FP]](f32)
; CHECK: $x0 = COPY [[RES]]
define i64 @test_fptosi(ptr %fp.addr) {
%fp = load float, ptr %fp.addr
@@ -1021,8 +1023,8 @@ define i64 @test_fptosi(ptr %fp.addr) {
; CHECK-LABEL: name: test_fptoui
; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOUI [[FP]](s32)
+; CHECK: [[FP:%[0-9]+]]:_(f32) = G_LOAD [[FPADDR]](p0)
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_FPTOUI [[FP]](f32)
; CHECK: $x0 = COPY [[RES]]
define i64 @test_fptoui(ptr %fp.addr) {
%fp = load float, ptr %fp.addr
@@ -1032,9 +1034,9 @@ define i64 @test_fptoui(ptr %fp.addr) {
; CHECK-LABEL: name: test_sitofp
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[FP:%[0-9]+]]:_(s64) = G_SITOFP [[IN]](s32)
-; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[FP:%[0-9]+]]:_(f64) = G_SITOFP [[IN]](i32)
+; CHECK: G_STORE [[FP]](f64), [[ADDR]](p0)
define void @test_sitofp(ptr %addr, i32 %in) {
%fp = sitofp i32 %in to double
store double %fp, ptr %addr
@@ -1043,9 +1045,9 @@ define void @test_sitofp(ptr %addr, i32 %in) {
; CHECK-LABEL: name: test_uitofp
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[FP:%[0-9]+]]:_(s64) = G_UITOFP [[IN]](s32)
-; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[FP:%[0-9]+]]:_(f64) = G_UITOFP [[IN]](i32)
+; CHECK: G_STORE [[FP]](f64), [[ADDR]](p0)
define void @test_uitofp(ptr %addr, i32 %in) {
%fp = uitofp i32 %in to double
store double %fp, ptr %addr
@@ -1053,8 +1055,8 @@ define void @test_uitofp(ptr %addr, i32 %in) {
}
; CHECK-LABEL: name: test_fpext
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPEXT [[IN]](s32)
+; CHECK: [[IN:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f64) = G_FPEXT [[IN]](f32)
; CHECK: $d0 = COPY [[RES]]
define double @test_fpext(float %in) {
%res = fpext float %in to double
@@ -1062,8 +1064,8 @@ define double @test_fpext(float %in) {
}
; CHECK-LABEL: name: test_fptrunc
-; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPTRUNC [[IN]](s64)
+; CHECK: [[IN:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_FPTRUNC [[IN]](f64)
; CHECK: $s0 = COPY [[RES]]
define float @test_fptrunc(double %in) {
%res = fptrunc double %in to float
@@ -1072,8 +1074,8 @@ define float @test_fptrunc(double %in) {
; CHECK-LABEL: name: test_constant_float
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[TMP:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+00
-; CHECK: G_STORE [[TMP]](s32), [[ADDR]](p0)
+; CHECK: [[TMP:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.500000e+00
+; CHECK: G_STORE [[TMP]](f32), [[ADDR]](p0)
define void @test_constant_float(ptr %addr) {
store float 1.5, ptr %addr
ret void
@@ -1083,10 +1085,10 @@ define void @test_constant_float(ptr %addr) {
; CHECK: [[LHSADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[RHSADDR:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_LOAD [[LHSADDR]](p0)
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_LOAD [[RHSADDR]](p0)
-; CHECK: [[TST:%[0-9]+]]:_(s1) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
-; CHECK: G_STORE [[TST]](s1), [[BOOLADDR]](p0)
+; CHECK: [[LHS:%[0-9]+]]:_(f32) = G_LOAD [[LHSADDR]](p0)
+; CHECK: [[RHS:%[0-9]+]]:_(f32) = G_LOAD [[RHSADDR]](p0)
+; CHECK: [[TST:%[0-9]+]]:_(i1) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(oge), [[LHS]](f32), [[RHS]]
+; CHECK: G_STORE [[TST]](i1), [[BOOLADDR]](p0)
define void @float_comparison(ptr %a.addr, ptr %b.addr, ptr %bool.addr) {
%a = load float, ptr %a.addr
%b = load float, ptr %b.addr
@@ -1096,10 +1098,10 @@ define void @float_comparison(ptr %a.addr, ptr %b.addr, ptr %bool.addr) {
}
; CHECK-LABEL: name: trivial_float_comparison
-; CHECK: [[ENTRY_R1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
-; CHECK: [[ENTRY_R2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
-; CHECK: [[R1:%[0-9]+]]:_(s1) = COPY [[ENTRY_R1]](s1)
-; CHECK: [[R2:%[0-9]+]]:_(s1) = COPY [[ENTRY_R2]](s1)
+; CHECK: [[ENTRY_R1:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+; CHECK: [[ENTRY_R2:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+; CHECK: [[R1:%[0-9]+]]:_(i1) = COPY [[ENTRY_R1]](i1)
+; CHECK: [[R2:%[0-9]+]]:_(i1) = COPY [[ENTRY_R2]](i1)
; CHECK: G_ADD [[R1]], [[R2]]
define i1 @trivial_float_comparison(double %a, double %b) {
%r1 = fcmp false double %a, %b
@@ -1141,8 +1143,8 @@ define void @test_memcpy(ptr %dst, ptr %src, i64 %size) {
; CHECK-LABEL: name: test_memcpy
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](i64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
call void @llvm.memcpy.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)
ret void
}
@@ -1151,8 +1153,8 @@ define void @test_memcpy_tail(ptr %dst, ptr %src, i64 %size) {
; CHECK-LABEL: name: test_memcpy_tail
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](i64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
tail call void @llvm.memcpy.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)
ret void
}
@@ -1162,8 +1164,8 @@ define void @test_memcpy_nonzero_as(ptr addrspace(1) %dst, ptr addrspace(1) %src
; CHECK-LABEL: name: test_memcpy_nonzero_as
; CHECK: [[DST:%[0-9]+]]:_(p1) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p1) = COPY $x1
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMCPY [[DST]](p1), [[SRC]](p1), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst, addrspace 1), (load (s8) from %ir.src, addrspace 1)
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMCPY [[DST]](p1), [[SRC]](p1), [[SIZE]](i64), 0 :: (store (s8) into %ir.dst, addrspace 1), (load (s8) from %ir.src, addrspace 1)
call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) %dst, ptr addrspace(1) %src, i64 %size, i1 0)
ret void
}
@@ -1173,8 +1175,8 @@ define void @test_memmove(ptr %dst, ptr %src, i64 %size) {
; CHECK-LABEL: name: test_memmove
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMMOVE [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMMOVE [[DST]](p0), [[SRC]](p0), [[SIZE]](i64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
call void @llvm.memmove.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)
ret void
}
@@ -1183,10 +1185,10 @@ declare void @llvm.memset.p0.i64(ptr, i8, i64, i1)
define void @test_memset(ptr %dst, i8 %val, i64 %size) {
; CHECK-LABEL: name: test_memset
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]]
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMSET [[DST]](p0), [[SRC]](s8), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst)
+; CHECK: [[SRC_C:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[SRC:%[0-9]+]]:_(i8) = G_TRUNC [[SRC_C]]
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMSET [[DST]](p0), [[SRC]](i8), [[SIZE]](i64), 0 :: (store (s8) into %ir.dst)
call void @llvm.memset.p0.i64(ptr %dst, i8 %val, i64 %size, i1 0)
ret void
}
@@ -1194,8 +1196,8 @@ define void @test_memset(ptr %dst, i8 %val, i64 %size) {
define void @test_large_const(ptr %addr) {
; CHECK-LABEL: name: test_large_const
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL:%[0-9]+]]:_(s128) = G_CONSTANT i128 42
-; CHECK: G_STORE [[VAL]](s128), [[ADDR]](p0)
+; CHECK: [[VAL:%[0-9]+]]:_(i128) = G_CONSTANT i128 42
+; CHECK: G_STORE [[VAL]](i128), [[ADDR]](p0)
store i128 42, ptr %addr
ret void
}
@@ -1207,8 +1209,8 @@ define void @test_large_const(ptr %addr) {
define ptr @test_const_placement() {
; CHECK-LABEL: name: test_const_placement
; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
-; CHECK: [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
-; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32)
+; CHECK: [[VAL_INT:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](i32)
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
br label %next
@@ -1242,9 +1244,9 @@ define void @test_va_arg(ptr %list) {
declare float @llvm.pow.f32(float, float)
define float @test_pow_intrin(float %l, float %r) {
; CHECK-LABEL: name: test_pow_intrin
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOW [[LHS]], [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RHS:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FPOW [[LHS]], [[RHS]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.pow.f32(float %l, float %r)
ret float %res
@@ -1253,9 +1255,9 @@ define float @test_pow_intrin(float %l, float %r) {
declare float @llvm.powi.f32.i32(float, i32)
define float @test_powi_intrin(float %l, i32 %r) {
; CHECK-LABEL: name: test_powi_intrin
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOWI [[LHS]], [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FPOWI [[LHS]], [[RHS]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.powi.f32.i32(float %l, i32 %r)
ret float %res
@@ -1264,10 +1266,10 @@ define float @test_powi_intrin(float %l, i32 %r) {
declare float @llvm.fma.f32(float, float, float)
define float @test_fma_intrin(float %a, float %b, float %c) {
; CHECK-LABEL: name: test_fma_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $s2
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[A]], [[B]], [[C]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[B:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[C:%[0-9]+]]:_(f32) = COPY $s2
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[A]], [[B]], [[C]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.fma.f32(float %a, float %b, float %c)
ret float %res
@@ -1276,8 +1278,8 @@ define float @test_fma_intrin(float %a, float %b, float %c) {
declare float @llvm.exp.f32(float)
define float @test_exp_intrin(float %a) {
; CHECK-LABEL: name: test_exp_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FEXP [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FEXP [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.exp.f32(float %a)
ret float %res
@@ -1286,8 +1288,8 @@ define float @test_exp_intrin(float %a) {
declare float @llvm.exp2.f32(float)
define float @test_exp2_intrin(float %a) {
; CHECK-LABEL: name: test_exp2_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FEXP2 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FEXP2 [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.exp2.f32(float %a)
ret float %res
@@ -1296,8 +1298,8 @@ define float @test_exp2_intrin(float %a) {
declare float @llvm.log.f32(float)
define float @test_log_intrin(float %a) {
; CHECK-LABEL: name: test_log_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FLOG [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FLOG [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.log.f32(float %a)
ret float %res
@@ -1306,8 +1308,8 @@ define float @test_log_intrin(float %a) {
declare float @llvm.log2.f32(float)
define float @test_log2_intrin(float %a) {
; CHECK-LABEL: name: test_log2_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG2 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_FLOG2 [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.log2.f32(float %a)
ret float %res
@@ -1316,8 +1318,8 @@ define float @test_log2_intrin(float %a) {
declare float @llvm.log10.f32(float)
define float @test_log10_intrin(float %a) {
; CHECK-LABEL: name: test_log10_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FLOG10 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FLOG10 [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.log10.f32(float %a)
ret float %res
@@ -1326,8 +1328,8 @@ define float @test_log10_intrin(float %a) {
declare float @llvm.fabs.f32(float)
define float @test_fabs_intrin(float %a) {
; CHECK-LABEL: name: test_fabs_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FABS [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FABS [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.fabs.f32(float %a)
ret float %res
@@ -1336,9 +1338,9 @@ define float @test_fabs_intrin(float %a) {
declare float @llvm.copysign.f32(float, float)
define float @test_fcopysign_intrin(float %a, float %b) {
; CHECK-LABEL: name: test_fcopysign_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FCOPYSIGN [[A]], [[B]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[B:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FCOPYSIGN [[A]], [[B]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.copysign.f32(float %a, float %b)
@@ -1348,8 +1350,8 @@ define float @test_fcopysign_intrin(float %a, float %b) {
declare float @llvm.canonicalize.f32(float)
define float @test_fcanonicalize_intrin(float %a) {
; CHECK-LABEL: name: test_fcanonicalize_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FCANONICALIZE [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FCANONICALIZE [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.canonicalize.f32(float %a)
ret float %res
@@ -1358,8 +1360,8 @@ define float @test_fcanonicalize_intrin(float %a) {
declare float @llvm.trunc.f32(float)
define float @test_intrinsic_trunc(float %a) {
; CHECK-LABEL: name: test_intrinsic_trunc
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.trunc.f32(float %a)
ret float %res
@@ -1368,8 +1370,8 @@ define float @test_intrinsic_trunc(float %a) {
declare float @llvm.round.f32(float)
define float @test_intrinsic_round(float %a) {
; CHECK-LABEL: name: test_intrinsic_round
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUND [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.round.f32(float %a)
ret float %res
@@ -1378,8 +1380,8 @@ define float @test_intrinsic_round(float %a) {
declare i32 @llvm.lrint.i32.f32(float)
define i32 @test_intrinsic_lrint(float %a) {
; CHECK-LABEL: name: test_intrinsic_lrint
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_LRINT [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_INTRINSIC_LRINT [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.lrint.i32.f32(float %a)
ret i32 %res
@@ -1388,8 +1390,8 @@ define i32 @test_intrinsic_lrint(float %a) {
declare i32 @llvm.llrint.i32.f32(float)
define i32 @test_intrinsic_llrint(float %a) {
; CHECK-LABEL: name: test_intrinsic_llrint
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_LLRINT [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_INTRINSIC_LLRINT [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.llrint.i32.f32(float %a)
ret i32 %res
@@ -1398,8 +1400,8 @@ define i32 @test_intrinsic_llrint(float %a) {
declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTLZ [[A]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CTLZ [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.ctlz.i32(i32 %a, i1 0)
ret i32 %res
@@ -1408,8 +1410,8 @@ define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
declare i32 @llvm.cttz.i32(i32, i1)
define i32 @test_cttz_intrinsic_zero_undef(i32 %a) {
; CHECK-LABEL: name: test_cttz_intrinsic_zero_undef
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[A]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CTTZ_ZERO_UNDEF [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.cttz.i32(i32 %a, i1 1)
ret i32 %res
@@ -1418,8 +1420,8 @@ define i32 @test_cttz_intrinsic_zero_undef(i32 %a) {
declare i32 @llvm.ctpop.i32(i32)
define i32 @test_ctpop_intrinsic(i32 %a) {
; CHECK-LABEL: name: test_ctpop
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTPOP [[A]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CTPOP [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %res
@@ -1428,8 +1430,8 @@ define i32 @test_ctpop_intrinsic(i32 %a) {
declare i32 @llvm.bitreverse.i32(i32)
define i32 @test_bitreverse_intrinsic(i32 %a) {
; CHECK-LABEL: name: test_bitreverse
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_BITREVERSE [[A]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_BITREVERSE [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.bitreverse.i32(i32 %a)
ret i32 %res
@@ -1438,10 +1440,10 @@ define i32 @test_bitreverse_intrinsic(i32 %a) {
declare i32 @llvm.fshl.i32(i32, i32, i32)
define i32 @test_fshl_intrinsic(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: name: test_fshl_intrinsic
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $w2
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FSHL [[A]], [[B]], [[C]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[B:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[C:%[0-9]+]]:_(i32) = COPY $w2
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_FSHL [[A]], [[B]], [[C]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
ret i32 %res
@@ -1450,10 +1452,10 @@ define i32 @test_fshl_intrinsic(i32 %a, i32 %b, i32 %c) {
declare i32 @llvm.fshr.i32(i32, i32, i32)
define i32 @test_fshr_intrinsic(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: name: test_fshr_intrinsic
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $w2
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FSHR [[A]], [[B]], [[C]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[B:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[C:%[0-9]+]]:_(i32) = COPY $w2
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_FSHR [[A]], [[B]], [[C]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
ret i32 %res
@@ -1494,12 +1496,12 @@ define void @test_lifetime_intrin_optnone() optnone noinline {
define void @test_load_store_atomics(ptr %addr) {
; CHECK-LABEL: name: test_load_store_atomics
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[V0:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load unordered (s8) from %ir.addr)
-; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic (s8) into %ir.addr)
-; CHECK: [[V1:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load acquire (s8) from %ir.addr)
-; CHECK: G_STORE [[V1]](s8), [[ADDR]](p0) :: (store release (s8) into %ir.addr)
-; CHECK: [[V2:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst (s8) from %ir.addr)
-; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic (s8) into %ir.addr)
+; CHECK: [[V0:%[0-9]+]]:_(i8) = G_LOAD [[ADDR]](p0) :: (load unordered (i8) from %ir.addr)
+; CHECK: G_STORE [[V0]](i8), [[ADDR]](p0) :: (store monotonic (i8) into %ir.addr)
+; CHECK: [[V1:%[0-9]+]]:_(i8) = G_LOAD [[ADDR]](p0) :: (load acquire (i8) from %ir.addr)
+; CHECK: G_STORE [[V1]](i8), [[ADDR]](p0) :: (store release (i8) into %ir.addr)
+; CHECK: [[V2:%[0-9]+]]:_(i8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst (i8) from %ir.addr)
+; CHECK: G_STORE [[V2]](i8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic (i8) into %ir.addr)
%v0 = load atomic i8, ptr %addr unordered, align 1
store atomic i8 %v0, ptr %addr monotonic, align 1
@@ -1514,36 +1516,36 @@ define void @test_load_store_atomics(ptr %addr) {
define float @test_fneg_f32(float %x) {
; CHECK-LABEL: name: test_fneg_f32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
-; CHECK: $s0 = COPY [[RES]](s32)
+; CHECK: [[ARG:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_FNEG [[ARG]]
+; CHECK: $s0 = COPY [[RES]](f32)
%neg = fneg float %x
ret float %neg
}
define float @test_fneg_f32_fmf(float %x) {
; CHECK-LABEL: name: test_fneg_f32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
-; CHECK: $s0 = COPY [[RES]](s32)
+; CHECK: [[ARG:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
+; CHECK: $s0 = COPY [[RES]](f32)
%neg = fneg fast float %x
ret float %neg
}
define double @test_fneg_f64(double %x) {
; CHECK-LABEL: name: test_fneg_f64
-; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
-; CHECK: $d0 = COPY [[RES]](s64)
+; CHECK: [[ARG:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[RES:%[0-9]+]]:_(f64) = G_FNEG [[ARG]]
+; CHECK: $d0 = COPY [[RES]](f64)
%neg = fneg double %x
ret double %neg
}
define double @test_fneg_f64_fmf(double %x) {
; CHECK-LABEL: name: test_fneg_f64
-; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
-; CHECK: $d0 = COPY [[RES]](s64)
+; CHECK: [[ARG:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[RES:%[0-9]+]]:_(f64) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
+; CHECK: $d0 = COPY [[RES]](f64)
%neg = fneg fast double %x
ret double %neg
}
@@ -1559,53 +1561,53 @@ define void @test_trivial_inlineasm() {
define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){
; CHECK-LABEL: name: test_insertelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[IDX2:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]]
-; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX2]](s64)
-; CHECK: $d0 = COPY [[RES]](<2 x s32>)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[ELT:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[IDX:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[IDX2:%[0-9]+]]:_(i64) = G_ZEXT [[IDX]]
+; CHECK: [[RES:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](i32), [[IDX2]](i64)
+; CHECK: $d0 = COPY [[RES]](<2 x i32>)
%res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx
ret <2 x i32> %res
}
define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[IDXEXT:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]]
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDXEXT]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[IDXEXT:%[0-9]+]]:_(i64) = G_ZEXT [[IDX]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x i32>), [[IDXEXT]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%res = extractelement <2 x i32> %vec, i32 %idx
ret i32 %res
}
define i32 @test_extractelement_const_idx(<2 x i32> %vec) {
; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x i32>), [[IDX]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%res = extractelement <2 x i32> %vec, i32 1
ret i32 %res
}
define i32 @test_extractelement_const_idx_zext_i1(<2 x i32> %vec) {
; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x i32>), [[IDX]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%res = extractelement <2 x i32> %vec, i1 true
ret i32 %res
}
define i32 @test_extractelement_const_idx_zext_i8(<2 x i32> %vec) {
; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 255
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x i32>), [[IDX]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%res = extractelement <2 x i32> %vec, i8 255
ret i32 %res
}
@@ -1613,10 +1615,10 @@ define i32 @test_extractelement_const_idx_zext_i8(<2 x i32> %vec) {
define i32 @test_singleelementvector(i32 %elt){
; CHECK-LABEL: name: test_singleelementvector
-; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0
+; CHECK: [[ELT:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NOT: G_INSERT_VECTOR_ELT
; CHECK-NOT: G_EXTRACT_VECTOR_ELT
-; CHECK: $w0 = COPY [[ELT]](s32)
+; CHECK: $w0 = COPY [[ELT]](i32)
%vec = insertelement <1 x i32> undef, i32 %elt, i32 0
%res = extractelement <1 x i32> %vec, i32 0
ret i32 %res
@@ -1624,75 +1626,75 @@ define i32 @test_singleelementvector(i32 %elt){
define <2 x i32> @test_constantaggzerovector_v2i32() {
; CHECK-LABEL: name: test_constantaggzerovector_v2i32
-; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+; CHECK: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[ZERO]](i32), [[ZERO]](i32)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
ret <2 x i32> zeroinitializer
}
define <2 x float> @test_constantaggzerovector_v2f32() {
; CHECK-LABEL: name: test_constantaggzerovector_v2f32
-; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+; CHECK: [[ZERO:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[ZERO]](f32), [[ZERO]](f32)
+; CHECK: $d0 = COPY [[VEC]](<2 x f32>)
ret <2 x float> zeroinitializer
}
define i32 @test_constantaggzerovector_v3i32() {
; CHECK-LABEL: name: test_constantaggzerovector_v3i32
-; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
+; CHECK: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ZERO]](i32), [[ZERO]](i32), [[ZERO]](i32)
+; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x i32>)
%elt = extractelement <3 x i32> zeroinitializer, i32 1
ret i32 %elt
}
define <2 x i32> @test_constantdatavector_v2i32() {
; CHECK-LABEL: name: test_constantdatavector_v2i32
-; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+; CHECK: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C2]](i32)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
ret <2 x i32> <i32 1, i32 2>
}
define i32 @test_constantdatavector_v3i32() {
; CHECK-LABEL: name: test_constantdatavector_v3i32
-; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C3]](s32)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
+; CHECK: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C2]](i32), [[C3]](i32)
+; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x i32>)
%elt = extractelement <3 x i32> <i32 1, i32 2, i32 3>, i32 1
ret i32 %elt
}
define <4 x i32> @test_constantdatavector_v4i32() {
; CHECK-LABEL: name: test_constantdatavector_v4i32
-; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
-; CHECK: $q0 = COPY [[VEC]](<4 x s32>)
+; CHECK: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+; CHECK: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C2]](i32), [[C3]](i32), [[C4]](i32)
+; CHECK: $q0 = COPY [[VEC]](<4 x i32>)
ret <4 x i32> <i32 1, i32 2, i32 3, i32 4>
}
define <2 x double> @test_constantdatavector_v2f64() {
; CHECK-LABEL: name: test_constantdatavector_v2f64
-; CHECK: [[FC1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
-; CHECK: [[FC2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FC1]](s64), [[FC2]](s64)
-; CHECK: $q0 = COPY [[VEC]](<2 x s64>)
+; CHECK: [[FC1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+; CHECK: [[FC2:%[0-9]+]]:_(f64) = G_FCONSTANT double 2.000000e+00
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FC1]](f64), [[FC2]](f64)
+; CHECK: $q0 = COPY [[VEC]](<2 x f64>)
ret <2 x double> <double 1.0, double 2.0>
}
-define i32 @test_constantaggzerovector_v1s32(i32 %arg){
-; CHECK-LABEL: name: test_constantaggzerovector_v1s32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+define i32 @test_constantaggzerovector_v1i32(i32 %arg){
+; CHECK-LABEL: name: test_constantaggzerovector_v1i32
+; CHECK: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NOT: G_MERGE_VALUES
-; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C0]]
+; CHECK: [[COPY:%[0-9]+]]:_(i32) = COPY [[C0]]
; CHECK-NOT: G_MERGE_VALUES
; CHECK: G_ADD [[ARG]], [[COPY]]
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
@@ -1701,18 +1703,18 @@ define i32 @test_constantaggzerovector_v1s32(i32 %arg){
ret i32 %res
}
-define i32 @test_constantdatavector_v1s32(i32 %arg){
-; CHECK-CV-LABEL: name: test_constantdatavector_v1s32
-; CHECK-CV: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-CV: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+define i32 @test_constantdatavector_v1i32(i32 %arg){
+; CHECK-CV-LABEL: name: test_constantdatavector_v1i32
+; CHECK-CV: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-CV: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-CV-NOT: G_MERGE_VALUES
-; CHECK-CV: [[COPY:%[0-9]+]]:_(s32) = COPY [[C0]]
+; CHECK-CV: [[COPY:%[0-9]+]]:_(i32) = COPY [[C0]]
; CHECK-CV-NOT: G_MERGE_VALUES
; CHECK-CV: G_ADD [[ARG]], [[COPY]]
;
-; CHECK-CI-LABEL: name: test_constantdatavector_v1s32
-; CHECK-CI: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-CI: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-CI-LABEL: name: test_constantdatavector_v1i32
+; CHECK-CI: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-CI: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-CI-NOT: G_MERGE_VALUES
; CHECK-CI: G_ADD [[ARG]], [[C0]]
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
@@ -1724,111 +1726,111 @@ define i32 @test_constantdatavector_v1s32(i32 %arg){
declare ghccc float @different_call_conv_target(float %x)
define float @test_different_call_conv_target(float %x) {
; CHECK-LABEL: name: test_different_call_conv
-; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[X:%[0-9]+]]:_(f32) = COPY $s0
; CHECK: $s8 = COPY [[X]]
; CHECK: BL @different_call_conv_target, csr_aarch64_noregs, implicit-def $lr, implicit $sp, implicit $s8, implicit-def $s0
%res = call ghccc float @different_call_conv_target(float %x)
ret float %res
}
-define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
-; CHECK-LABEL: name: test_shufflevector_s32_v2s32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ARG]](s32), [[ARG]](s32)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_i32_v2i32(i32 %arg) {
+; CHECK-LABEL: name: test_shufflevector_i32_v2i32
+; CHECK: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[ARG]](i32), [[ARG]](i32)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
%res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
ret <2 x i32> %res
}
-define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_s32
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ARG]](<2 x s32>), [[IDX]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+define i32 @test_shufflevector_v2i32_i32(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_i32
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[ARG]](<2 x i32>), [[IDX]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1>
%res = extractelement <1 x i32> %vec, i32 0
ret i32 %res
}
-define <2 x i32> @test_shufflevector_v2s32_v2s32_undef(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(undef, undef)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_v2i32_v2i32_undef(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_undef
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(undef, undef)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> undef
ret <2 x i32> %res
}
-define <2 x i32> @test_shufflevector_v2s32_v2s32_undef_0(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef_0
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(undef, 0)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_v2i32_v2i32_undef_0(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_undef_0
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(undef, 0)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 undef, i32 0>
ret <2 x i32> %res
}
-define <2 x i32> @test_shufflevector_v2s32_v2s32_0_undef(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_0_undef
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(0, undef)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_v2i32_v2i32_0_undef(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_0_undef
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(0, undef)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 0, i32 undef>
ret <2 x i32> %res
}
-define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(1, 0, 1)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
+define i32 @test_shufflevector_v2i32_v3i32(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v3i32
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(1, 0, 1)
+; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x i32>)
%vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
%res = extractelement <3 x i32> %vec, i32 0
ret i32 %res
}
-define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
-; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY $d1
-; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], shufflemask(0, 1, 2, 3)
-; CHECK: $q0 = COPY [[VEC]](<4 x s32>)
+define <4 x i32> @test_shufflevector_v2i32_v4i32(<2 x i32> %arg1, <2 x i32> %arg2) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v4i32
+; CHECK: [[ARG1:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[ARG2:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x i32>), [[ARG2]], shufflemask(0, 1, 2, 3)
+; CHECK: $q0 = COPY [[VEC]](<4 x i32>)
%res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i32> %res
}
-define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
-; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY $q0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], shufflemask(1, 3)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_v4i32_v2i32(<4 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v4i32_v2i32
+; CHECK: [[ARG:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x i32>), [[UNDEF]], shufflemask(1, 3)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
ret <2 x i32> %res
}
-define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
-; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
-; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY $d0
-; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY $d1
-; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], shufflemask(0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15)
-; CHECK: $q0 = COPY [[VEC]](<16 x s8>)
+define <16 x i8> @test_shufflevector_v8i8_v16i8(<8 x i8> %arg1, <8 x i8> %arg2) {
+; CHECK-LABEL: name: test_shufflevector_v8i8_v16i8
+; CHECK: [[ARG1:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+; CHECK: [[ARG2:%[0-9]+]]:_(<8 x i8>) = COPY $d1
+; CHECK: [[VEC:%[0-9]+]]:_(<16 x i8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x i8>), [[ARG2]], shufflemask(0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15)
+; CHECK: $q0 = COPY [[VEC]](<16 x i8>)
%res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i8> %res
}
; CHECK-LABEL: test_constant_vector
-; CHECK: [[UNDEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
-; CHECK: [[F:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
-; CHECK: [[M:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
-; CHECK: $d0 = COPY [[M]](<4 x s16>)
+; CHECK: [[UNDEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+; CHECK: [[F:%[0-9]+]]:_(f16) = G_FCONSTANT half 0xH3C00
+; CHECK: [[M:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UNDEF]](f16), [[UNDEF]](f16), [[UNDEF]](f16), [[F]](f16)
+; CHECK: $d0 = COPY [[M]](<4 x f16>)
define <4 x half> @test_constant_vector() {
ret <4 x half> <half undef, half undef, half undef, half 0xH3C00>
}
@@ -1836,8 +1838,8 @@ define <4 x half> @test_constant_vector() {
define i32 @test_target_mem_intrinsic(ptr %addr) {
; CHECK-LABEL: name: test_target_mem_intrinsic
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load (s32) from %ir.addr)
-; CHECK: G_TRUNC [[VAL]](s64)
+; CHECK: [[VAL:%[0-9]+]]:_(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load (i32) from %ir.addr)
+; CHECK: G_TRUNC [[VAL]](i64)
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) %addr)
%trunc = trunc i64 %val to i32
ret i32 %trunc
@@ -1861,22 +1863,22 @@ entry:
define i64 @test_phi_loop(i32 %n) {
; CHECK-LABEL: name: test_phi_loop
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[CST2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-
-; CHECK: [[PN1:%[0-9]+]]:_(s32) = G_PHI [[ARG1]](s32), %bb.1, [[SUB:%[0-9]+]](s32), %bb.2
-; CHECK: [[PN2:%[0-9]+]]:_(s64) = G_PHI [[CST3]](s64), %bb.1, [[PN3:%[0-9]+]](s64), %bb.2
-; CHECK: [[PN3]]:_(s64) = G_PHI [[CST4]](s64), %bb.1, [[ADD:%[0-9]+]](s64), %bb.2
-; CHECK: [[ADD]]:_(s64) = G_ADD [[PN2]], [[PN3]]
-; CHECK: [[SUB]]:_(s32) = G_SUB [[PN1]], [[CST1]]
-; CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[PN1]](s32), [[CST2]]
-; CHECK: G_BRCOND [[CMP]](s1), %bb.3
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[CST1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[CST2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[CST4:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+
+; CHECK: [[PN1:%[0-9]+]]:_(i32) = G_PHI [[ARG1]](i32), %bb.1, [[SUB:%[0-9]+]](i32), %bb.2
+; CHECK: [[PN2:%[0-9]+]]:_(i64) = G_PHI [[CST3]](i64), %bb.1, [[PN3:%[0-9]+]](i64), %bb.2
+; CHECK: [[PN3]]:_(i64) = G_PHI [[CST4]](i64), %bb.1, [[ADD:%[0-9]+]](i64), %bb.2
+; CHECK: [[ADD]]:_(i64) = G_ADD [[PN2]], [[PN3]]
+; CHECK: [[SUB]]:_(i32) = G_SUB [[PN1]], [[CST1]]
+; CHECK: [[CMP:%[0-9]+]]:_(i1) = G_ICMP intpred(sle), [[PN1]](i32), [[CST2]]
+; CHECK: G_BRCOND [[CMP]](i1), %bb.3
; CHECK: G_BR %bb.2
-; CHECK: $x0 = COPY [[PN2]](s64)
+; CHECK: $x0 = COPY [[PN2]](i64)
; CHECK: RET_ReallyLR implicit $x0
entry:
br label %loop
@@ -1902,41 +1904,41 @@ define void @test_phi_diamond(ptr %a.ptr, ptr %b.ptr, i1 %selector, ptr %dst) {
; CHECK-LABEL: name: test_phi_diamond
; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ARG2:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY $w2
-; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[ARG3]]
+; CHECK: [[ARG3:%[0-9]+]]:_(i32) = COPY $w2
+; CHECK: [[TRUNC8:%[0-9]+]]:_(i8) = G_TRUNC [[ARG3]]
; CHECK: [[ARG4:%[0-9]+]]:_(p0) = COPY $x3
-; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC8]], 1
-; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNCASSERT]]
-; CHECK: G_BRCOND [[TRUNC]](s1), %bb.2
+; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC8]], 1
+; CHECK: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[TRUNCASSERT]]
+; CHECK: G_BRCOND [[TRUNC]](i1), %bb.2
; CHECK: G_BR %bb.3
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD [[ARG1]](p0) :: (load (s8) from %ir.a.ptr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s16) = G_LOAD [[GEP1]](p0) :: (load (s16) from %ir.a.ptr + 2)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.a.ptr + 4)
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD [[ARG1]](p0) :: (load (i8) from %ir.a.ptr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i16) = G_LOAD [[GEP1]](p0) :: (load (i16) from %ir.a.ptr + 2)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.a.ptr + 4)
; CHECK: G_BR %bb.4
-; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[ARG2]](p0) :: (load (s8) from %ir.b.ptr, align 4)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST3]](s64)
-; CHECK: [[LD5:%[0-9]+]]:_(s16) = G_LOAD [[GEP3]](p0) :: (load (s16) from %ir.b.ptr + 2)
-; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST4]](s64)
-; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load (s32) from %ir.b.ptr + 4)
-
-; CHECK: [[PN1:%[0-9]+]]:_(s8) = G_PHI [[LD1]](s8), %bb.2, [[LD4]](s8), %bb.3
-; CHECK: [[PN2:%[0-9]+]]:_(s16) = G_PHI [[LD2]](s16), %bb.2, [[LD5]](s16), %bb.3
-; CHECK: [[PN3:%[0-9]+]]:_(s32) = G_PHI [[LD3]](s32), %bb.2, [[LD6]](s32), %bb.3
-; CHECK: G_STORE [[PN1]](s8), [[ARG4]](p0) :: (store (s8) into %ir.dst, align 4)
-; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
-; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST5]](s64)
-; CHECK: G_STORE [[PN2]](s16), [[GEP5]](p0) :: (store (s16) into %ir.dst + 2)
-; CHECK: [[CST6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST6]](s64)
-; CHECK: G_STORE [[PN3]](s32), [[GEP6]](p0) :: (store (s32) into %ir.dst + 4)
+; CHECK: [[LD4:%[0-9]+]]:_(i8) = G_LOAD [[ARG2]](p0) :: (load (i8) from %ir.b.ptr, align 4)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST3]](i64)
+; CHECK: [[LD5:%[0-9]+]]:_(i16) = G_LOAD [[GEP3]](p0) :: (load (i16) from %ir.b.ptr + 2)
+; CHECK: [[CST4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST4]](i64)
+; CHECK: [[LD6:%[0-9]+]]:_(i32) = G_LOAD [[GEP4]](p0) :: (load (i32) from %ir.b.ptr + 4)
+
+; CHECK: [[PN1:%[0-9]+]]:_(i8) = G_PHI [[LD1]](i8), %bb.2, [[LD4]](i8), %bb.3
+; CHECK: [[PN2:%[0-9]+]]:_(i16) = G_PHI [[LD2]](i16), %bb.2, [[LD5]](i16), %bb.3
+; CHECK: [[PN3:%[0-9]+]]:_(i32) = G_PHI [[LD3]](i32), %bb.2, [[LD6]](i32), %bb.3
+; CHECK: G_STORE [[PN1]](i8), [[ARG4]](p0) :: (store (i8) into %ir.dst, align 4)
+; CHECK: [[CST5:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST5]](i64)
+; CHECK: G_STORE [[PN2]](i16), [[GEP5]](p0) :: (store (i16) into %ir.dst + 2)
+; CHECK: [[CST6:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST6]](i64)
+; CHECK: G_STORE [[PN3]](i32), [[GEP6]](p0) :: (store (i32) into %ir.dst + 4)
; CHECK: RET_ReallyLR
entry:
@@ -1963,31 +1965,31 @@ join:
define void @test_nested_aggregate_const(ptr %ptr) {
; CHECK-LABEL: name: test_nested_aggregate_const
; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[CST2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
-; CHECK: [[CST3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
-; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
-; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[CST6:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
-; CHECK: G_STORE [[CST1]](s32), [[BASE]](p0) :: (store (s32) into %ir.ptr, align 8)
-; CHECK: [[CST7:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST7]](s64)
-; CHECK: G_STORE [[CST1]](s32), [[GEP1]](p0) :: (store (s32) into %ir.ptr + 4)
-; CHECK: [[CST8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST8]](s64)
-; CHECK: G_STORE [[CST2]](s16), [[GEP2]](p0) :: (store (s16) into %ir.ptr + 8, align 8)
-; CHECK: [[CST9:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST9]](s64)
-; CHECK: G_STORE [[CST3]](s8), [[GEP3]](p0) :: (store (s8) into %ir.ptr + 10, align 2)
-; CHECK: [[CST10:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST10]](s64)
-; CHECK: G_STORE [[CST4]](s64), [[GEP4]](p0) :: (store (s64) into %ir.ptr + 16)
-; CHECK: [[CST11:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
-; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST11]](s64)
-; CHECK: G_STORE [[CST5]](s64), [[GEP5]](p0) :: (store (s64) into %ir.ptr + 24)
-; CHECK: [[CST12:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
-; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST12]](s64)
-; CHECK: G_STORE [[CST6]](s32), [[GEP6]](p0) :: (store (s32) into %ir.ptr + 32, align 8)
+; CHECK: [[CST1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[CST2:%[0-9]+]]:_(i16) = G_CONSTANT i16 2
+; CHECK: [[CST3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+; CHECK: [[CST4:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+; CHECK: [[CST5:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[CST6:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+; CHECK: G_STORE [[CST1]](i32), [[BASE]](p0) :: (store (i32) into %ir.ptr, align 8)
+; CHECK: [[CST7:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST7]](i64)
+; CHECK: G_STORE [[CST1]](i32), [[GEP1]](p0) :: (store (i32) into %ir.ptr + 4)
+; CHECK: [[CST8:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST8]](i64)
+; CHECK: G_STORE [[CST2]](i16), [[GEP2]](p0) :: (store (i16) into %ir.ptr + 8, align 8)
+; CHECK: [[CST9:%[0-9]+]]:_(i64) = G_CONSTANT i64 10
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST9]](i64)
+; CHECK: G_STORE [[CST3]](i8), [[GEP3]](p0) :: (store (i8) into %ir.ptr + 10, align 2)
+; CHECK: [[CST10:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST10]](i64)
+; CHECK: G_STORE [[CST4]](i64), [[GEP4]](p0) :: (store (i64) into %ir.ptr + 16)
+; CHECK: [[CST11:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST11]](i64)
+; CHECK: G_STORE [[CST5]](i64), [[GEP5]](p0) :: (store (i64) into %ir.ptr + 24)
+; CHECK: [[CST12:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST12]](i64)
+; CHECK: G_STORE [[CST6]](i32), [[GEP6]](p0) :: (store (i32) into %ir.ptr + 32, align 8)
store %agg.nested { i32 1, i32 1, %agg.inner { i16 2, i8 3, %agg.inner.inner {i64 5, i64 8} }, i32 13}, ptr %ptr
ret void
}
@@ -1995,10 +1997,10 @@ define void @test_nested_aggregate_const(ptr %ptr) {
define i1 @return_i1_zext() {
; AAPCS ABI says that booleans can only be 1 or 0, so we need to zero-extend.
; CHECK-LABEL: name: return_i1_zext
-; CHECK: [[CST:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
-; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[CST]](s1)
-; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
-; CHECK: $w0 = COPY [[ANYEXT]](s32)
+; CHECK: [[CST:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+; CHECK: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[CST]](i1)
+; CHECK: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+; CHECK: $w0 = COPY [[ANYEXT]](i32)
; CHECK: RET_ReallyLR implicit $w0
ret i1 true
}
@@ -2010,12 +2012,12 @@ define i32 @test_atomic_cmpxchg_1(ptr %addr) {
; CHECK-NEXT: successors: %bb.{{[^)]+}}
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK: bb.2.repeat:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVALRES:%[0-9]+]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (s32) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVALRES:%[0-9]+]]:_(i32), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (i32) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.done:
entry:
@@ -2036,12 +2038,12 @@ define i32 @test_weak_atomic_cmpxchg_1(ptr %addr) {
; CHECK-NEXT: successors: %bb.{{[^)]+}}
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK: bb.2.repeat:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVALRES:%[0-9]+]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (s32) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVALRES:%[0-9]+]]:_(i32), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (i32) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.done:
entry:
@@ -2062,12 +2064,12 @@ define i16 @test_atomic_cmpxchg_2(ptr %addr) {
; CHECK-NEXT: successors: %bb.2({{[^)]+}})
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(i16) = G_CONSTANT i16 0
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
; CHECK: bb.2.repeat:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVALRES:%[0-9]+]]:_(s16), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (s16) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVALRES:%[0-9]+]]:_(i16), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (i16) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.done:
entry:
@@ -2088,12 +2090,12 @@ define i64 @test_atomic_cmpxchg_3(ptr %addr) {
; CHECK-NEXT: successors: %bb.2({{[^)]+}})
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK: bb.2.repeat:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVALRES:%[0-9]+]]:_(s64), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst acquire (s64) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVALRES:%[0-9]+]]:_(i64), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst acquire (i64) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.done:
entry:
@@ -2113,8 +2115,8 @@ define i32 @test_atomicrmw_xchg(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_XCHG [[ADDR]](p0), [[VAL]] :: (load store monotonic (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_XCHG [[ADDR]](p0), [[VAL]] :: (load store monotonic (i32) on %ir.addr)
%oldval = atomicrmw xchg ptr %addr, i32 1 monotonic
ret i32 %oldval
}
@@ -2125,8 +2127,8 @@ define i32 @test_atomicrmw_add(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[ADDR]](p0), [[VAL]] :: (load store acquire (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_ADD [[ADDR]](p0), [[VAL]] :: (load store acquire (i32) on %ir.addr)
%oldval = atomicrmw add ptr %addr, i32 1 acquire
ret i32 %oldval
}
@@ -2137,8 +2139,8 @@ define i32 @test_atomicrmw_sub(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_SUB [[ADDR]](p0), [[VAL]] :: (load store release (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_SUB [[ADDR]](p0), [[VAL]] :: (load store release (i32) on %ir.addr)
%oldval = atomicrmw sub ptr %addr, i32 1 release
ret i32 %oldval
}
@@ -2149,8 +2151,8 @@ define i32 @test_atomicrmw_and(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[ADDR]](p0), [[VAL]] :: (load store acq_rel (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_AND [[ADDR]](p0), [[VAL]] :: (load store acq_rel (i32) on %ir.addr)
%oldval = atomicrmw and ptr %addr, i32 1 acq_rel
ret i32 %oldval
}
@@ -2163,16 +2165,16 @@ define i32 @test_atomicrmw_nand(ptr %addr) {
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[NEG1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
-; CHECK-NEXT: [[OLDVALSTART:%[0-9]+]]:_(s32) = G_LOAD [[ADDR]](p0) :: (load (s32) from %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[NEG1:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1
+; CHECK-NEXT: [[OLDVALSTART:%[0-9]+]]:_(i32) = G_LOAD [[ADDR]](p0) :: (load (i32) from %ir.addr)
; CHECK: bb.2.atomicrmw.start:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVAL:%[0-9]+]]:_(s32) = G_PHI [[OLDVALSTART]](s32), %bb.1, [[OLDVALRES:%[0-9]+]](s32), %bb.2
-; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[OLDVAL]], [[VAL]]
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_XOR [[AND]], [[NEG1]]
-; CHECK: [[OLDVALRES]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (s32) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVAL:%[0-9]+]]:_(i32) = G_PHI [[OLDVALSTART]](i32), %bb.1, [[OLDVALRES:%[0-9]+]](i32), %bb.2
+; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[OLDVAL]], [[VAL]]
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i32) = G_XOR [[AND]], [[NEG1]]
+; CHECK: [[OLDVALRES]]:_(i32), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (i32) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.atomicrmw.end:
%oldval = atomicrmw nand ptr %addr, i32 1 seq_cst
@@ -2185,8 +2187,8 @@ define i32 @test_atomicrmw_or(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_OR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_OR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw or ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2197,8 +2199,8 @@ define i32 @test_atomicrmw_xor(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_XOR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_XOR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw xor ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2209,8 +2211,8 @@ define i32 @test_atomicrmw_min(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_MIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_MIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw min ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2221,8 +2223,8 @@ define i32 @test_atomicrmw_max(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_MAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_MAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw max ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2233,8 +2235,8 @@ define i32 @test_atomicrmw_umin(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_UMIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_UMIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw umin ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2245,8 +2247,8 @@ define i32 @test_atomicrmw_umax(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_UMAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_UMAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw umax ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2279,7 +2281,7 @@ define void @test_invariant_intrin() {
declare float @llvm.ceil.f32(float)
define float @test_ceil_f32(float %x) {
; CHECK-LABEL: name: test_ceil_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FCEIL %{{[0-9]+}}
%y = call float @llvm.ceil.f32(float %x)
ret float %y
}
@@ -2287,7 +2289,7 @@ define float @test_ceil_f32(float %x) {
declare double @llvm.ceil.f64(double)
define double @test_ceil_f64(double %x) {
; CHECK-LABEL: name: test_ceil_f64
- ; CHECK: %{{[0-9]+}}:_(s64) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f64) = G_FCEIL %{{[0-9]+}}
%y = call double @llvm.ceil.f64(double %x)
ret double %y
}
@@ -2295,7 +2297,7 @@ define double @test_ceil_f64(double %x) {
declare <2 x float> @llvm.ceil.v2f32(<2 x float>)
define <2 x float> @test_ceil_v2f32(<2 x float> %x) {
; CHECK-LABEL: name: test_ceil_v2f32
- ; CHECK: %{{[0-9]+}}:_(<2 x s32>) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(<2 x f32>) = G_FCEIL %{{[0-9]+}}
%y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x)
ret <2 x float> %y
}
@@ -2303,7 +2305,7 @@ define <2 x float> @test_ceil_v2f32(<2 x float> %x) {
declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
define <4 x float> @test_ceil_v4f32(<4 x float> %x) {
; CHECK-LABEL: name: test_ceil_v4f32
- ; CHECK: %{{[0-9]+}}:_(<4 x s32>) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(<4 x f32>) = G_FCEIL %{{[0-9]+}}
; SELECT: %{{[0-9]+}}:fpr128 = FRINTPv4f32 %{{[0-9]+}}
%y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x)
ret <4 x float> %y
@@ -2312,7 +2314,7 @@ define <4 x float> @test_ceil_v4f32(<4 x float> %x) {
declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
define <2 x double> @test_ceil_v2f64(<2 x double> %x) {
; CHECK-LABEL: name: test_ceil_v2f64
- ; CHECK: %{{[0-9]+}}:_(<2 x s64>) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(<2 x f64>) = G_FCEIL %{{[0-9]+}}
%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x)
ret <2 x double> %y
}
@@ -2320,7 +2322,7 @@ define <2 x double> @test_ceil_v2f64(<2 x double> %x) {
declare float @llvm.cos.f32(float)
define float @test_cos_f32(float %x) {
; CHECK-LABEL: name: test_cos_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FCOS %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FCOS %{{[0-9]+}}
%y = call float @llvm.cos.f32(float %x)
ret float %y
}
@@ -2328,7 +2330,7 @@ define float @test_cos_f32(float %x) {
declare float @llvm.sin.f32(float)
define float @test_sin_f32(float %x) {
; CHECK-LABEL: name: test_sin_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSIN %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FSIN %{{[0-9]+}}
%y = call float @llvm.sin.f32(float %x)
ret float %y
}
@@ -2336,7 +2338,7 @@ define float @test_sin_f32(float %x) {
declare float @llvm.tan.f32(float)
define float @test_tan_f32(float %x) {
; CHECK-LABEL: name: test_tan_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FTAN %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FTAN %{{[0-9]+}}
%y = call float @llvm.tan.f32(float %x)
ret float %y
}
@@ -2344,7 +2346,7 @@ define float @test_tan_f32(float %x) {
declare float @llvm.acos.f32(float)
define float @test_acos_f32(float %x) {
; CHECK-LABEL: name: test_acos_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FACOS %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FACOS %{{[0-9]+}}
%y = call float @llvm.acos.f32(float %x)
ret float %y
}
@@ -2352,7 +2354,7 @@ define float @test_acos_f32(float %x) {
declare float @llvm.asin.f32(float)
define float @test_asin_f32(float %x) {
; CHECK-LABEL: name: test_asin_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FASIN %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FASIN %{{[0-9]+}}
%y = call float @llvm.asin.f32(float %x)
ret float %y
}
@@ -2360,7 +2362,7 @@ define float @test_asin_f32(float %x) {
declare float @llvm.atan.f32(float)
define float @test_atan_f32(float %x) {
; CHECK-LABEL: name: test_atan_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FATAN %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FATAN %{{[0-9]+}}
%y = call float @llvm.atan.f32(float %x)
ret float %y
}
@@ -2368,7 +2370,7 @@ define float @test_atan_f32(float %x) {
declare float @llvm.atan2.f32(float, float)
define float @test_atan2_f32(float %x, float %y) {
; CHECK-LABEL: name: test_atan2_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FATAN2 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FATAN2 %{{[0-9]+}}
%z = call float @llvm.atan2.f32(float %x, float %y)
ret float %z
}
@@ -2376,7 +2378,7 @@ define float @test_atan2_f32(float %x, float %y) {
declare float @llvm.cosh.f32(float)
define float @test_cosh_f32(float %x) {
; CHECK-LABEL: name: test_cosh_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FCOSH %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FCOSH %{{[0-9]+}}
%y = call float @llvm.cosh.f32(float %x)
ret float %y
}
@@ -2384,7 +2386,7 @@ define float @test_cosh_f32(float %x) {
declare float @llvm.sinh.f32(float)
define float @test_sinh_f32(float %x) {
; CHECK-LABEL: name: test_sinh_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSINH %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FSINH %{{[0-9]+}}
%y = call float @llvm.sinh.f32(float %x)
ret float %y
}
@@ -2392,7 +2394,7 @@ define float @test_sinh_f32(float %x) {
declare float @llvm.tanh.f32(float)
define float @test_tanh_f32(float %x) {
; CHECK-LABEL: name: test_tanh_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FTANH %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FTANH %{{[0-9]+}}
%y = call float @llvm.tanh.f32(float %x)
ret float %y
}
@@ -2400,7 +2402,7 @@ define float @test_tanh_f32(float %x) {
declare float @llvm.sqrt.f32(float)
define float @test_sqrt_f32(float %x) {
; CHECK-LABEL: name: test_sqrt_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FSQRT %{{[0-9]+}}
%y = call float @llvm.sqrt.f32(float %x)
ret float %y
}
@@ -2408,7 +2410,7 @@ define float @test_sqrt_f32(float %x) {
declare float @llvm.floor.f32(float)
define float @test_floor_f32(float %x) {
; CHECK-LABEL: name: test_floor_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FFLOOR %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FFLOOR %{{[0-9]+}}
%y = call float @llvm.floor.f32(float %x)
ret float %y
}
@@ -2416,13 +2418,13 @@ define float @test_floor_f32(float %x) {
declare float @llvm.nearbyint.f32(float)
define float @test_nearbyint_f32(float %x) {
; CHECK-LABEL: name: test_nearbyint_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FNEARBYINT %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FNEARBYINT %{{[0-9]+}}
%y = call float @llvm.nearbyint.f32(float %x)
ret float %y
}
; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i32
-; CHECK: %1:_(<4 x s32>), %2:_(<4 x s32>), %3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load (s384) from %ir.ptr, align 64)
+; CHECK: %1:_(<4 x i32>), %2:_(<4 x i32>), %3:_(<4 x i32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load (s384) from %ir.ptr, align 64)
define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(ptr %ptr) {
%arst = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %ptr)
ret void
@@ -2432,10 +2434,10 @@ declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr)
define void @test_i1_arg_zext(ptr %f) {
; CHECK-LABEL: name: test_i1_arg_zext
-; CHECK: [[I1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
-; CHECK: [[ZEXT0:%[0-9]+]]:_(s8) = G_ZEXT [[I1]](s1)
-; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT0]](s8)
-; CHECK: $w0 = COPY [[ZEXT1]](s32)
+; CHECK: [[I1:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+; CHECK: [[ZEXT0:%[0-9]+]]:_(i8) = G_ZEXT [[I1]](i1)
+; CHECK: [[ZEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT0]](i8)
+; CHECK: $w0 = COPY [[ZEXT1]](i32)
call void %f(i1 true)
ret void
}
@@ -2455,7 +2457,7 @@ define void @test_stacksaverestore() {
declare float @llvm.rint.f32(float)
define float @test_rint_f32(float %x) {
; CHECK-LABEL: name: test_rint_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FRINT %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FRINT %{{[0-9]+}}
%y = call float @llvm.rint.f32(float %x)
ret float %y
}
@@ -2504,7 +2506,7 @@ define void @test_var_annotation(ptr, ptr, ptr, i32) {
declare i64 @llvm.readcyclecounter()
define i64 @test_readcyclecounter() {
; CHECK-LABEL: name: test_readcyclecounter
- ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_READCYCLECOUNTER{{$}}
+ ; CHECK: [[RES:%[0-9]+]]:_(i64) = G_READCYCLECOUNTER{{$}}
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = call i64 @llvm.readcyclecounter()
@@ -2513,8 +2515,8 @@ define i64 @test_readcyclecounter() {
define i64 @test_freeze(i64 %a) {
; CHECK-LABEL: name: test_freeze
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
+ ; CHECK: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_FREEZE [[COPY]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = freeze i64 %a
@@ -2524,13 +2526,13 @@ define i64 @test_freeze(i64 %a) {
define {i8, i32} @test_freeze_struct(ptr %addr) {
; CHECK-LABEL: name: test_freeze_struct
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]]
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[LOAD]]
- ; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s32) = G_FREEZE [[LOAD1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE]]
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(i8) = G_FREEZE [[LOAD]]
+ ; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(i32) = G_FREEZE [[LOAD1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FREEZE]]
; CHECK-NEXT: $w0 = COPY [[ANYEXT]]
; CHECK-NEXT: $w1 = COPY [[FREEZE1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
@@ -2546,9 +2548,9 @@ define i64 @lround(float %x) {
; CHECK-LABEL: name: lround
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $s0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[LROUND:%[0-9]+]]:_(s64) = G_LROUND [[COPY]](s32)
- ; CHECK: $x0 = COPY [[LROUND]](s64)
+ ; CHECK: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK: [[LROUND:%[0-9]+]]:_(i64) = G_LROUND [[COPY]](f32)
+ ; CHECK: $x0 = COPY [[LROUND]](i64)
; CHECK: RET_ReallyLR implicit $x0
%lround = tail call i64 @llvm.lround.i64.f32(float %x)
ret i64 %lround
@@ -2559,9 +2561,9 @@ define i64 @llround(float %x) {
; CHECK-LABEL: name: llround
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $s0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[LLROUND:%[0-9]+]]:_(s64) = G_LLROUND [[COPY]](s32)
- ; CHECK: $x0 = COPY [[LLROUND]](s64)
+ ; CHECK: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK: [[LLROUND:%[0-9]+]]:_(i64) = G_LLROUND [[COPY]](f32)
+ ; CHECK: $x0 = COPY [[LLROUND]](i64)
; CHECK: RET_ReallyLR implicit $x0
%lround = tail call i64 @llvm.llround.i64.f32(float %x)
ret i64 %lround
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
index 57481724936a3..78c2b12198b17 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
@@ -12,7 +12,7 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -20,7 +20,7 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRW renamable $w2, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STXRW renamable $w2, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -46,13 +46,13 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) {
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $w1, $x0, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w9 = LDRWui killed renamable $x2, 0, implicit-def $x9, pcsections !0 :: (load (s32) from %ir.pnew)
+ ; CHECK-NEXT: renamable $w9 = LDRWui killed renamable $x2, 0, implicit-def $x9, pcsections !0 :: (load (i32) from %ir.pnew)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.cmpxchg.start:
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $x0, $x9
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -60,7 +60,7 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) {
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $x0, $x8, $x9
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRW renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRW renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -91,7 +91,7 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -99,7 +99,7 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STLXRW renamable $w2, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STLXRW renamable $w2, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -129,7 +129,7 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -137,7 +137,7 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) {
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -167,7 +167,7 @@ define i64 @val_compare_and_swap_64_monotonic_seqcst(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -175,7 +175,7 @@ define i64 @val_compare_and_swap_64_monotonic_seqcst(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STLXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STLXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -205,7 +205,7 @@ define i64 @val_compare_and_swap_64_release_acquire(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -213,7 +213,7 @@ define i64 @val_compare_and_swap_64_release_acquire(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STLXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STLXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -240,13 +240,13 @@ define i32 @fetch_and_nand(ptr %p) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w8, 2, pcsections !0
; CHECK-NEXT: $w9 = ORNWrs $wzr, killed renamable $w9, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRW killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRW killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -265,13 +265,13 @@ define i64 @fetch_and_nand_64(ptr %p) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: renamable $x9 = ANDXri renamable $x8, 4098, pcsections !0
; CHECK-NEXT: $x9 = ORNXrs $xzr, killed renamable $x9, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRX killed renamable $x9, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRX killed renamable $x9, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -292,12 +292,12 @@ define i32 @fetch_and_or(ptr %p) {
; CHECK-NEXT: renamable $w9 = MOVZWi 5, 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $w10 = ORRWrs renamable $w8, renamable $w9, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STLXRW killed renamable $w10, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STLXRW killed renamable $w10, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -316,12 +316,12 @@ define i64 @fetch_and_or_64(ptr %p) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: renamable $x9 = ORRXri renamable $x8, 4098, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRX killed renamable $x9, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRX killed renamable $x9, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -365,7 +365,7 @@ define i32 @atomic_load(ptr %p) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (i32) from %ir.p)
; CHECK-NEXT: RET undef $lr, implicit $w0
%r = load atomic i32, ptr %p seq_cst, align 4, !pcsections !0
ret i32 %r
@@ -376,13 +376,13 @@ define i8 @atomic_load_relaxed_8(ptr %p, i32 %off32) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDRBBui renamable $x0, 4095, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unsigned)
- ; CHECK-NEXT: renamable $w9 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0 :: (load unordered (s8) from %ir.ptr_regoff)
- ; CHECK-NEXT: renamable $w10 = LDURBBi renamable $x0, -256 :: (load monotonic (s8) from %ir.ptr_unscaled)
+ ; CHECK-NEXT: renamable $w8 = LDRBBui renamable $x0, 4095, pcsections !0 :: (load monotonic (i8) from %ir.ptr_unsigned)
+ ; CHECK-NEXT: renamable $w9 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0 :: (load unordered (i8) from %ir.ptr_regoff)
+ ; CHECK-NEXT: renamable $w10 = LDURBBi renamable $x0, -256 :: (load monotonic (i8) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-NEXT: renamable $x9 = ADDXri killed renamable $x0, 291, 12
; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w8, killed renamable $w10, 0, pcsections !0
- ; CHECK-NEXT: renamable $w9 = LDRBBui killed renamable $x9, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_random)
+ ; CHECK-NEXT: renamable $w9 = LDRBBui killed renamable $x9, 0, pcsections !0 :: (load unordered (i8) from %ir.ptr_random)
; CHECK-NEXT: renamable $w0 = ADDWrx killed renamable $w8, killed renamable $w9, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
%ptr_unsigned = getelementptr i8, ptr %p, i32 4095
@@ -408,13 +408,13 @@ define i16 @atomic_load_relaxed_16(ptr %p, i32 %off32) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDRHHui renamable $x0, 4095, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unsigned)
- ; CHECK-NEXT: renamable $w9 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1 :: (load unordered (s16) from %ir.ptr_regoff)
- ; CHECK-NEXT: renamable $w10 = LDURHHi renamable $x0, -256 :: (load monotonic (s16) from %ir.ptr_unscaled)
+ ; CHECK-NEXT: renamable $w8 = LDRHHui renamable $x0, 4095, pcsections !0 :: (load monotonic (i16) from %ir.ptr_unsigned)
+ ; CHECK-NEXT: renamable $w9 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1 :: (load unordered (i16) from %ir.ptr_regoff)
+ ; CHECK-NEXT: renamable $w10 = LDURHHi renamable $x0, -256 :: (load monotonic (i16) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w9, killed renamable $w8, 8, pcsections !0
; CHECK-NEXT: renamable $x9 = ADDXri killed renamable $x0, 291, 12
; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w8, killed renamable $w10, 8, pcsections !0
- ; CHECK-NEXT: renamable $w9 = LDRHHui killed renamable $x9, 0, pcsections !0 :: (load unordered (s16) from %ir.ptr_random)
+ ; CHECK-NEXT: renamable $w9 = LDRHHui killed renamable $x9, 0, pcsections !0 :: (load unordered (i16) from %ir.ptr_random)
; CHECK-NEXT: renamable $w0 = ADDWrx killed renamable $w8, killed renamable $w9, 8, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
%ptr_unsigned = getelementptr i16, ptr %p, i32 4095
@@ -440,12 +440,12 @@ define i32 @atomic_load_relaxed_32(ptr %p, i32 %off32) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDRWui renamable $x0, 4095, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unsigned)
- ; CHECK-NEXT: renamable $w9 = LDRWroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s32) from %ir.ptr_regoff)
- ; CHECK-NEXT: renamable $w10 = LDURWi renamable $x0, -256, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unscaled)
+ ; CHECK-NEXT: renamable $w8 = LDRWui renamable $x0, 4095, pcsections !0 :: (load monotonic (i32) from %ir.ptr_unsigned)
+ ; CHECK-NEXT: renamable $w9 = LDRWroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (i32) from %ir.ptr_regoff)
+ ; CHECK-NEXT: renamable $w10 = LDURWi renamable $x0, -256, pcsections !0 :: (load monotonic (i32) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x11 = ADDXri killed renamable $x0, 291, 12
; CHECK-NEXT: $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0, pcsections !0
- ; CHECK-NEXT: renamable $w9 = LDRWui killed renamable $x11, 0, pcsections !0 :: (load unordered (s32) from %ir.ptr_random)
+ ; CHECK-NEXT: renamable $w9 = LDRWui killed renamable $x11, 0, pcsections !0 :: (load unordered (i32) from %ir.ptr_random)
; CHECK-NEXT: $w8 = ADDWrs killed renamable $w8, killed renamable $w10, 0, pcsections !0
; CHECK-NEXT: $w0 = ADDWrs killed renamable $w8, killed renamable $w9, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
@@ -472,12 +472,12 @@ define i64 @atomic_load_relaxed_64(ptr %p, i32 %off32) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDRXui renamable $x0, 4095, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unsigned)
- ; CHECK-NEXT: renamable $x9 = LDRXroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s64) from %ir.ptr_regoff)
- ; CHECK-NEXT: renamable $x10 = LDURXi renamable $x0, -256, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unscaled)
+ ; CHECK-NEXT: renamable $x8 = LDRXui renamable $x0, 4095, pcsections !0 :: (load monotonic (i64) from %ir.ptr_unsigned)
+ ; CHECK-NEXT: renamable $x9 = LDRXroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (i64) from %ir.ptr_regoff)
+ ; CHECK-NEXT: renamable $x10 = LDURXi renamable $x0, -256, pcsections !0 :: (load monotonic (i64) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x11 = ADDXri killed renamable $x0, 291, 12
; CHECK-NEXT: $x8 = ADDXrs killed renamable $x8, killed renamable $x9, 0, pcsections !0
- ; CHECK-NEXT: renamable $x9 = LDRXui killed renamable $x11, 0, pcsections !0 :: (load unordered (s64) from %ir.ptr_random)
+ ; CHECK-NEXT: renamable $x9 = LDRXui killed renamable $x11, 0, pcsections !0 :: (load unordered (i64) from %ir.ptr_random)
; CHECK-NEXT: $x8 = ADDXrs killed renamable $x8, killed renamable $x10, 0, pcsections !0
; CHECK-NEXT: $x0 = ADDXrs killed renamable $x8, killed renamable $x9, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $x0
@@ -506,7 +506,7 @@ define void @atomc_store(ptr %p) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = MOVZWi 4, 0
- ; CHECK-NEXT: STLRW killed renamable $w8, killed renamable $x0, pcsections !0 :: (store seq_cst (s32) into %ir.p)
+ ; CHECK-NEXT: STLRW killed renamable $w8, killed renamable $x0, pcsections !0 :: (store seq_cst (i32) into %ir.p)
; CHECK-NEXT: RET undef $lr
store atomic i32 4, ptr %p seq_cst, align 4, !pcsections !0
ret void
@@ -517,11 +517,11 @@ define void @atomic_store_relaxed_8(ptr %p, i32 %off32, i8 %val) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRBBui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (s8) into %ir.ptr_unsigned)
- ; CHECK-NEXT: STRBBroW renamable $w2, renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (store unordered (s8) into %ir.ptr_regoff)
- ; CHECK-NEXT: STURBBi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (s8) into %ir.ptr_unscaled)
+ ; CHECK-NEXT: STRBBui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (i8) into %ir.ptr_unsigned)
+ ; CHECK-NEXT: STRBBroW renamable $w2, renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (store unordered (i8) into %ir.ptr_regoff)
+ ; CHECK-NEXT: STURBBi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (i8) into %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = ADDXri killed renamable $x0, 291, 12
- ; CHECK-NEXT: STRBBui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (s8) into %ir.ptr_random)
+ ; CHECK-NEXT: STRBBui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (i8) into %ir.ptr_random)
; CHECK-NEXT: RET undef $lr
%ptr_unsigned = getelementptr i8, ptr %p, i32 4095
store atomic i8 %val, ptr %ptr_unsigned monotonic, align 1, !pcsections !0
@@ -543,11 +543,11 @@ define void @atomic_store_relaxed_16(ptr %p, i32 %off32, i16 %val) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRHHui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (s16) into %ir.ptr_unsigned)
- ; CHECK-NEXT: STRHHroW renamable $w2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (s16) into %ir.ptr_regoff)
- ; CHECK-NEXT: STURHHi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (s16) into %ir.ptr_unscaled)
+ ; CHECK-NEXT: STRHHui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (i16) into %ir.ptr_unsigned)
+ ; CHECK-NEXT: STRHHroW renamable $w2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (i16) into %ir.ptr_regoff)
+ ; CHECK-NEXT: STURHHi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (i16) into %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = ADDXri killed renamable $x0, 291, 12
- ; CHECK-NEXT: STRHHui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (s16) into %ir.ptr_random)
+ ; CHECK-NEXT: STRHHui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (i16) into %ir.ptr_random)
; CHECK-NEXT: RET undef $lr
%ptr_unsigned = getelementptr i16, ptr %p, i32 4095
store atomic i16 %val, ptr %ptr_unsigned monotonic, align 2, !pcsections !0
@@ -569,11 +569,11 @@ define void @atomic_store_relaxed_32(ptr %p, i32 %off32, i32 %val) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRWui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (s32) into %ir.ptr_unsigned)
- ; CHECK-NEXT: STRWroW renamable $w2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (s32) into %ir.ptr_regoff)
- ; CHECK-NEXT: STURWi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (s32) into %ir.ptr_unscaled)
+ ; CHECK-NEXT: STRWui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (i32) into %ir.ptr_unsigned)
+ ; CHECK-NEXT: STRWroW renamable $w2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (i32) into %ir.ptr_regoff)
+ ; CHECK-NEXT: STURWi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (i32) into %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = ADDXri killed renamable $x0, 291, 12
- ; CHECK-NEXT: STRWui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (s32) into %ir.ptr_random)
+ ; CHECK-NEXT: STRWui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (i32) into %ir.ptr_random)
; CHECK-NEXT: RET undef $lr
%ptr_unsigned = getelementptr i32, ptr %p, i32 4095
store atomic i32 %val, ptr %ptr_unsigned monotonic, align 4, !pcsections !0
@@ -595,11 +595,11 @@ define void @atomic_store_relaxed_64(ptr %p, i32 %off32, i64 %val) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui renamable $x2, renamable $x0, 4095, pcsections !0 :: (store monotonic (s64) into %ir.ptr_unsigned)
- ; CHECK-NEXT: STRXroW renamable $x2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (s64) into %ir.ptr_regoff)
- ; CHECK-NEXT: STURXi renamable $x2, renamable $x0, -256, pcsections !0 :: (store monotonic (s64) into %ir.ptr_unscaled)
+ ; CHECK-NEXT: STRXui renamable $x2, renamable $x0, 4095, pcsections !0 :: (store monotonic (i64) into %ir.ptr_unsigned)
+ ; CHECK-NEXT: STRXroW renamable $x2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (i64) into %ir.ptr_regoff)
+ ; CHECK-NEXT: STURXi renamable $x2, renamable $x0, -256, pcsections !0 :: (store monotonic (i64) into %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = ADDXri killed renamable $x0, 291, 12
- ; CHECK-NEXT: STRXui killed renamable $x2, killed renamable $x8, 0, pcsections !0 :: (store unordered (s64) into %ir.ptr_random)
+ ; CHECK-NEXT: STRXui killed renamable $x2, killed renamable $x8, 0, pcsections !0 :: (store unordered (i64) into %ir.ptr_random)
; CHECK-NEXT: RET undef $lr
%ptr_unsigned = getelementptr i64, ptr %p, i32 4095
store atomic i64 %val, ptr %ptr_unsigned monotonic, align 8, !pcsections !0
@@ -621,8 +621,8 @@ define i32 @load_zext(ptr %p8, ptr %p16) {
; CHECK-NOLSE: bb.0 (%ir-block.0):
; CHECK-NOLSE-NEXT: liveins: $x0, $x1
; CHECK-NOLSE-NEXT: {{ $}}
- ; CHECK-NOLSE-NEXT: renamable $w8 = LDARB killed renamable $x0, pcsections !0 :: (load acquire (s8) from %ir.p8)
- ; CHECK-NOLSE-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (s16) from %ir.p16)
+ ; CHECK-NOLSE-NEXT: renamable $w8 = LDARB killed renamable $x0, pcsections !0 :: (load acquire (i8) from %ir.p8)
+ ; CHECK-NOLSE-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (i16) from %ir.p16)
; CHECK-NOLSE-NEXT: renamable $w0 = ADDWrx killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-NOLSE-NEXT: RET undef $lr, implicit $w0
;
@@ -630,8 +630,8 @@ define i32 @load_zext(ptr %p8, ptr %p16) {
; CHECK-LDAPR: bb.0 (%ir-block.0):
; CHECK-LDAPR-NEXT: liveins: $x0, $x1
; CHECK-LDAPR-NEXT: {{ $}}
- ; CHECK-LDAPR-NEXT: renamable $w8 = LDAPRB killed renamable $x0, pcsections !0 :: (load acquire (s8) from %ir.p8)
- ; CHECK-LDAPR-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (s16) from %ir.p16)
+ ; CHECK-LDAPR-NEXT: renamable $w8 = LDAPRB killed renamable $x0, pcsections !0 :: (load acquire (i8) from %ir.p8)
+ ; CHECK-LDAPR-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (i16) from %ir.p16)
; CHECK-LDAPR-NEXT: renamable $w0 = ADDWrx killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-LDAPR-NEXT: RET undef $lr, implicit $w0
%val1.8 = load atomic i8, ptr %p8 acquire, align 1, !pcsections !0
@@ -649,16 +649,16 @@ define { i32, i64 } @load_acq(ptr %p32, ptr %p64) {
; CHECK-NOLSE: bb.0 (%ir-block.0):
; CHECK-NOLSE-NEXT: liveins: $x0, $x1
; CHECK-NOLSE-NEXT: {{ $}}
- ; CHECK-NOLSE-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (s32) from %ir.p32)
- ; CHECK-NOLSE-NEXT: renamable $x1 = LDARX killed renamable $x1, pcsections !0 :: (load acquire (s64) from %ir.p64)
+ ; CHECK-NOLSE-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (i32) from %ir.p32)
+ ; CHECK-NOLSE-NEXT: renamable $x1 = LDARX killed renamable $x1, pcsections !0 :: (load acquire (i64) from %ir.p64)
; CHECK-NOLSE-NEXT: RET undef $lr, implicit $w0, implicit $x1
;
; CHECK-LDAPR-LABEL: name: load_acq
; CHECK-LDAPR: bb.0 (%ir-block.0):
; CHECK-LDAPR-NEXT: liveins: $x0, $x1
; CHECK-LDAPR-NEXT: {{ $}}
- ; CHECK-LDAPR-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (s32) from %ir.p32)
- ; CHECK-LDAPR-NEXT: renamable $x1 = LDAPRX killed renamable $x1, pcsections !0 :: (load acquire (s64) from %ir.p64)
+ ; CHECK-LDAPR-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (i32) from %ir.p32)
+ ; CHECK-LDAPR-NEXT: renamable $x1 = LDAPRX killed renamable $x1, pcsections !0 :: (load acquire (i64) from %ir.p64)
; CHECK-LDAPR-NEXT: RET undef $lr, implicit $w0, implicit $x1
%val32 = load atomic i32, ptr %p32 seq_cst, align 4, !pcsections !0
%tmp = insertvalue { i32, i64 } undef, i32 %val32, 0
@@ -674,8 +674,8 @@ define i32 @load_sext(ptr %p8, ptr %p16) {
; CHECK-NOLSE: bb.0 (%ir-block.0):
; CHECK-NOLSE-NEXT: liveins: $x0, $x1
; CHECK-NOLSE-NEXT: {{ $}}
- ; CHECK-NOLSE-NEXT: renamable $w8 = LDARB killed renamable $x0, pcsections !0 :: (load acquire (s8) from %ir.p8)
- ; CHECK-NOLSE-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (s16) from %ir.p16)
+ ; CHECK-NOLSE-NEXT: renamable $w8 = LDARB killed renamable $x0, pcsections !0 :: (load acquire (i8) from %ir.p8)
+ ; CHECK-NOLSE-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (i16) from %ir.p16)
; CHECK-NOLSE-NEXT: renamable $w9 = SBFMWri killed renamable $w9, 0, 15
; CHECK-NOLSE-NEXT: renamable $w0 = ADDWrx killed renamable $w9, killed renamable $w8, 32, pcsections !0
; CHECK-NOLSE-NEXT: RET undef $lr, implicit $w0
@@ -684,8 +684,8 @@ define i32 @load_sext(ptr %p8, ptr %p16) {
; CHECK-LDAPR: bb.0 (%ir-block.0):
; CHECK-LDAPR-NEXT: liveins: $x0, $x1
; CHECK-LDAPR-NEXT: {{ $}}
- ; CHECK-LDAPR-NEXT: renamable $w8 = LDAPRB killed renamable $x0, pcsections !0 :: (load acquire (s8) from %ir.p8)
- ; CHECK-LDAPR-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (s16) from %ir.p16)
+ ; CHECK-LDAPR-NEXT: renamable $w8 = LDAPRB killed renamable $x0, pcsections !0 :: (load acquire (i8) from %ir.p8)
+ ; CHECK-LDAPR-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (i16) from %ir.p16)
; CHECK-LDAPR-NEXT: renamable $w9 = SBFMWri killed renamable $w9, 0, 15
; CHECK-LDAPR-NEXT: renamable $w0 = ADDWrx killed renamable $w9, killed renamable $w8, 32, pcsections !0
; CHECK-LDAPR-NEXT: RET undef $lr, implicit $w0
@@ -704,8 +704,8 @@ define void @store_trunc(i32 %val, ptr %p8, ptr %p16) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STLRB renamable $w0, killed renamable $x1, pcsections !0 :: (store seq_cst (s8) into %ir.p8)
- ; CHECK-NEXT: STRHHui killed renamable $w0, killed renamable $x2, 0, pcsections !0 :: (store monotonic (s16) into %ir.p16)
+ ; CHECK-NEXT: STLRB renamable $w0, killed renamable $x1, pcsections !0 :: (store seq_cst (i8) into %ir.p8)
+ ; CHECK-NEXT: STRHHui killed renamable $w0, killed renamable $x2, 0, pcsections !0 :: (store monotonic (i16) into %ir.p16)
; CHECK-NEXT: RET undef $lr
%val8 = trunc i32 %val to i8
store atomic i8 %val8, ptr %p8 seq_cst, align 1, !pcsections !0
@@ -723,12 +723,12 @@ define i8 @atomicrmw_add_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = ADDWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -747,11 +747,11 @@ define i8 @atomicrmw_xchg_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w1, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w1, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -770,12 +770,12 @@ define i8 @atomicrmw_sub_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = SUBWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -794,12 +794,12 @@ define i8 @atomicrmw_and_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = ANDWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -818,12 +818,12 @@ define i8 @atomicrmw_or_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = ORRWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -842,12 +842,12 @@ define i8 @atomicrmw_xor_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = EORWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -866,14 +866,14 @@ define i8 @atomicrmw_min_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 32, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit killed $nzcv, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -892,14 +892,14 @@ define i8 @atomicrmw_max_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 32, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 12, implicit killed $nzcv, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -920,14 +920,14 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: renamable $w9 = ANDWri killed renamable $w1, 7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STLXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STLXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -948,14 +948,14 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: renamable $w9 = ANDWri killed renamable $w1, 7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -974,12 +974,12 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = ADDWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -998,11 +998,11 @@ define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w1, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w1, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1021,12 +1021,12 @@ define i16 @atomicrmw_sub_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = SUBWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1045,12 +1045,12 @@ define i16 @atomicrmw_and_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = ANDWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1069,12 +1069,12 @@ define i16 @atomicrmw_or_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = ORRWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1093,12 +1093,12 @@ define i16 @atomicrmw_xor_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = EORWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1117,14 +1117,14 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 40, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit killed $nzcv, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1143,14 +1143,14 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 40, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 12, implicit killed $nzcv, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1171,14 +1171,14 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: renamable $w9 = ANDWri killed renamable $w1, 15
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STLXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STLXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1199,14 +1199,14 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: renamable $w9 = ANDWri killed renamable $w1, 15
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.atomicrmw.start:
- ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1230,21 +1230,21 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
- ; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
+ ; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
- ; CHECK-NEXT: renamable $w9 = MOVZWi 1, 0
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (i8) into %ir.ptr)
+ ; CHECK-NEXT: renamable $w9 = MOVZWi 1, 0
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
- ; CHECK-NEXT: B %bb.4
+ ; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.cmpxchg.nostore:
+ ; CHECK-NEXT: bb.3.cmpxchg.nostore:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
@@ -1273,16 +1273,16 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 8, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
- ; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
+ ; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: renamable $w9 = MOVZWi 1, 0
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: B %bb.4
@@ -1299,7 +1299,7 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
; CHECK-NEXT: $w1 = ORRWrs $wzr, killed $w9, 0
- ; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
+ ; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
%res = cmpxchg ptr %ptr, i16 %desired, i16 %new monotonic monotonic, !pcsections !0
ret { i16, i1 } %res
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index a29a46bd43e49..dfc23cc4ee3ed 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -405,8 +405,8 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
-# CHECK: %0:gpr(s32) = COPY $w0
-# FAST-NEXT: %1:fpr(<4 x s8>) = G_BITCAST %0
+# CHECK: %0:gpr(s32) = COPY $w0
+# FAST: %1:fpr(<4 x s8>) = G_BITCAST %2(s32)
# GREEDY-NEXT: %1:gpr(<4 x s8>) = G_BITCAST %0
# The greedy check is incorrect and should produce fpr.
body: |
@@ -424,7 +424,7 @@ legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '', flags: [ ] }
-# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }
# GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
@@ -432,7 +432,7 @@ registers:
# CHECK: body:
# CHECK: %0:fpr(<2 x s16>) = COPY $s0
-# FAST: %1:gpr(s32) = G_BITCAST %0
+# FAST: %1:fpr(s32) = G_BITCAST %0(<2 x s16>)
# GREEDY: %1:fpr(s32) = G_BITCAST %0
body: |
bb.0:
@@ -457,7 +457,7 @@ registers:
# CHECK: body:
# CHECK: %0:gpr(s32) = COPY $w0
-# FAST: %1:fpr(<2 x s16>) = G_BITCAST %0
+# FAST: %1:fpr(<2 x s16>) = G_BITCAST %2(s32)
# GREEDY: %1:gpr(<2 x s16>) = G_BITCAST %0
body: |
bb.0:
@@ -476,7 +476,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s16>) = COPY $s0
-# FAST: %1:gpr(s32) = G_BITCAST %0
+# FAST: %1:fpr(s32) = G_BITCAST %0(<2 x s16>)
# GREEDY: %1:fpr(s32) = G_BITCAST %0
body: |
bb.0:
@@ -495,7 +495,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s64) = COPY $x0
-# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
+# FAST: %1:fpr(<2 x s32>) = G_BITCAST %2(s64)
# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
body: |
bb.0:
@@ -514,7 +514,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s32>) = COPY $d0
-# FAST: %1:gpr(s64) = G_BITCAST %0
+# FAST: %1:fpr(s64) = G_BITCAST %0(<2 x s32>)
# GREEDY: %1:fpr(s64) = G_BITCAST %0
body: |
bb.0:
@@ -533,7 +533,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s64) = COPY $x0
-# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
+# FAST: %1:fpr(<2 x s32>) = G_BITCAST %2(s64)
# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
body: |
bb.0:
@@ -552,7 +552,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s32>) = COPY $d0
-# FAST: %1:gpr(s64) = G_BITCAST %0
+# FAST: %1:fpr(s64) = G_BITCAST %0(<2 x s32>)
# GREEDY: %1:fpr(s64) = G_BITCAST %0
body: |
bb.0:
@@ -691,13 +691,14 @@ registers:
# No repairing should be necessary for both modes.
# CHECK: %0:gpr(s64) = COPY $x0
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
-# FAST-NEXT: %2:fpr(<2 x s32>) = G_BITCAST %0(s64)
+# FAST: %2:fpr(<2 x s32>) = G_BITCAST %6(s64)
# FAST-NEXT: %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>) from %ir.addr)
# FAST-NEXT: %4:fpr(<2 x s32>) = G_OR %2, %3
+# FAST-NEXT: %5:fpr(s64) = G_BITCAST %4(<2 x s32>)
# GREEDY-NEXT: %2:gpr(<2 x s32>) = G_BITCAST %0(s64)
# GREEDY-NEXT: %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>) from %ir.addr)
# GREEDY-NEXT: %4:gpr(<2 x s32>) = G_OR %2, %3
-# CHECK-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
+# GREEDY-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
# CHECK-NEXT: $x0 = COPY %5(s64)
# CHECK-NEXT: RET_ReallyLR implicit $x0
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
new file mode 100644
index 0000000000000..2fd07dc2fa729
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
@@ -0,0 +1,127 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O3 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-SD
+; RUN: llc < %s -O3 -global-isel -global-isel-abort=1 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-GIS
+
+define bfloat @scalar_fptrunc_float(float %a) {
+; SCALAR-LABEL: scalar_fptrunc_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: bfcvt h0, s0
+; SCALAR-NEXT: ret
+entry:
+ %res = fptrunc float %a to bfloat
+ ret bfloat %res
+}
+
+define float @scalar_fpext(bfloat %a) {
+; SCALAR-LABEL: scalar_fpext:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-NEXT: // kill: def $s0 killed $s0 killed $q0
+; SCALAR-NEXT: ret
+entry:
+ %res = fpext bfloat %a to float
+ ret float %res
+}
+
+define double @scalar_fpext_double(bfloat %a) {
+; SCALAR-LABEL: scalar_fpext_double:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-NEXT: fcvt d0, s0
+; SCALAR-NEXT: ret
+entry:
+ %res = fpext bfloat %a to double
+ ret double %res
+}
+
+define <2 x bfloat> @v2bf16_fptrunc_float(<2 x float> %a) {
+; SCALAR-LABEL: v2bf16_fptrunc_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: // kill: def $d0 killed $d0 def $q0
+; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-NEXT: ret
+entry:
+ %res = fptrunc <2 x float> %a to <2 x bfloat>
+ ret <2 x bfloat> %res
+}
+
+define <3 x bfloat> @v3bf16_fptrunc_float(<3 x float> %a) {
+; SCALAR-LABEL: v3bf16_fptrunc_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-NEXT: ret
+entry:
+ %res = fptrunc <3 x float> %a to <3 x bfloat>
+ ret <3 x bfloat> %res
+}
+
+define <4 x bfloat> @v4bf16_fptrunc_float(<4 x float> %a) {
+; SCALAR-LABEL: v4bf16_fptrunc_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-NEXT: ret
+entry:
+ %res = fptrunc <4 x float> %a to <4 x bfloat>
+ ret <4 x bfloat> %res
+}
+
+define <4 x bfloat> @v4bf16_fptrunc_double(<4 x double> %a) {
+; SCALAR-SD-LABEL: v4bf16_fptrunc_double:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: fcvtxn v0.2s, v0.2d
+; SCALAR-SD-NEXT: fcvtxn2 v0.4s, v1.2d
+; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: v4bf16_fptrunc_double:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: fcvtxn v0.2s, v0.2d
+; SCALAR-GIS-NEXT: fcvtxn2 v0.4s, v1.2d
+; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fptrunc <4 x double> %a to <4 x bfloat>
+ ret <4 x bfloat> %res
+}
+
+define <2 x float> @v2bf16_fpext_float(<2 x bfloat> %a) {
+; SCALAR-LABEL: v2bf16_fpext_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-NEXT: // kill: def $d0 killed $d0 killed $q0
+; SCALAR-NEXT: ret
+entry:
+ %res = fpext <2 x bfloat> %a to <2 x float>
+ ret <2 x float> %res
+}
+
+define <4 x float> @v4bf16_fpext_float(<4 x bfloat> %a) {
+; SCALAR-LABEL: v4bf16_fpext_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-NEXT: ret
+entry:
+ %res = fpext <4 x bfloat> %a to <4 x float>
+ ret <4 x float> %res
+}
+
+define <4 x double> @v4bf16_fpext_double(<4 x bfloat> %a) {
+; SCALAR-SD-LABEL: v4bf16_fpext_double:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fcvtl2 v1.2d, v0.4s
+; SCALAR-SD-NEXT: fcvtl v0.2d, v0.2s
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: v4bf16_fpext_double:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: shll v1.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: fcvtl v0.2d, v1.2s
+; SCALAR-GIS-NEXT: fcvtl2 v1.2d, v1.4s
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fpext <4 x bfloat> %a to <4 x double>
+ ret <4 x double> %res
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
new file mode 100644
index 0000000000000..75f5f68aa1904
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
@@ -0,0 +1,200 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O3 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-SD
+; RUN: llc < %s -O3 -global-isel -global-isel-abort=1 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-GIS
+
+define bfloat @scalar_fadd(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fadd:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fadd s0, s0, s1
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fadd:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fadd s0, s0, s1
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fadd bfloat %a, %b
+ ret bfloat %res
+}
+
+define <2 x bfloat> @v2bf16_fadd(<2 x bfloat> %a, <2 x bfloat> %b) {
+; SCALAR-SD-LABEL: v2bf16_fadd:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fadd v0.4s, v0.4s, v1.4s
+; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: v2bf16_fadd:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fadd v0.2s, v0.2s, v1.2s
+; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fadd <2 x bfloat> %a, %b
+ ret <2 x bfloat> %res
+}
+
+
+define <4 x bfloat> @v4bf16_fadd(<4 x bfloat> %a, <4 x bfloat> %b) {
+; SCALAR-SD-LABEL: v4bf16_fadd:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fadd v0.4s, v0.4s, v1.4s
+; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: v4bf16_fadd:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fadd v0.4s, v0.4s, v1.4s
+; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fadd <4 x bfloat> %a, %b
+ ret <4 x bfloat> %res
+}
+
+define bfloat @scalar_fsub(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fsub:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fsub s0, s0, s1
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fsub:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fsub s0, s0, s1
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fsub bfloat %a, %b
+ ret bfloat %res
+}
+
+define bfloat @scalar_fmul(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fmul:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fmul s0, s0, s1
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fmul:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fmul s0, s0, s1
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fmul bfloat %a, %b
+ ret bfloat %res
+}
+
+define bfloat @scalar_fdiv(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fdiv:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fdiv s0, s0, s1
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fdiv:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fdiv s0, s0, s1
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fdiv bfloat %a, %b
+ ret bfloat %res
+}
+
+define i1 @scalar_fcmp(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fcmp:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fcmp s0, s1
+; SCALAR-SD-NEXT: cset w0, gt
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fcmp:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fcmp s0, s1
+; SCALAR-GIS-NEXT: cset w0, gt
+; SCALAR-GIS-NEXT: ret
+entry:
+ %cmp = fcmp ogt bfloat %a, %b
+ ret i1 %cmp
+}
+
+define bfloat @scalar_sitofp(i32 %a) {
+; SCALAR-SD-LABEL: scalar_sitofp:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: scvtf d0, w0
+; SCALAR-SD-NEXT: fcvtxn s0, d0
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_sitofp:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: scvtf s0, w0
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = sitofp i32 %a to bfloat
+ ret bfloat %res
+}
+
+define <4 x bfloat> @v4i32_sitofp(<4 x i32> %a) {
+; SCALAR-LABEL: v4i32_sitofp:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: scvtf v0.4s, v0.4s
+; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-NEXT: ret
+entry:
+ %res = sitofp <4 x i32> %a to <4 x bfloat>
+ ret <4 x bfloat> %res
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
index 2305c2694131c..51d7e2bcd218d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
@@ -19,7 +19,7 @@ define void @caller() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @foo_alias, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: RET_ReallyLR
entry:
%0 = call i32 @foo_alias()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
index 982f096fdba55..d5d3b12291b52 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
@@ -20,7 +20,7 @@ define void @caller() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @foo_ifunc, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: RET_ReallyLR
entry:
%0 = call i32 @foo_ifunc()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
index 4224c1cad1b6f..dedbd82e49dc7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
@@ -8,11 +8,11 @@ define i8 @signext_param_i8(i8 signext %x) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY]], 8
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i8 %x
}
@@ -22,10 +22,10 @@ define i8 @no_signext_param(i8 %x) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i8 %x
}
@@ -36,8 +36,8 @@ define i32 @signext_param_i32(i32 signext %x) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i32 %x
}
@@ -48,22 +48,22 @@ define i32 @signext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[SEXTLOAD]], 1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(i32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[SEXTLOAD]], 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %g, i64 %h, i64 %i, i1 signext %j) {
%v = zext i1 %j to i32
@@ -76,19 +76,19 @@ define i32 @dont_need_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.0, align 8)
- ; CHECK-NEXT: $w0 = COPY [[LOAD1]](s32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i32) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i,
i32 signext %j) {
@@ -101,22 +101,22 @@ define i8 @s8_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[SEXTLOAD]], 8
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(i32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[SEXTLOAD]], 8
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i,
i8 signext %j) {
@@ -128,11 +128,11 @@ define i32 @callee_signext_i1(i1 signext %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s1)
- ; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY]], 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = sext i1 %0 to i32
ret i32 %r
@@ -141,15 +141,15 @@ define i32 @callee_signext_i1(i1 signext %0) {
define i32 @caller_signext_i1() {
; CHECK-LABEL: name: caller_signext_i1
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s8) = G_SEXT [[C]](s1)
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[SEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[SEXT1]](s32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i8) = G_SEXT [[C]](i1)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i32) = G_SEXT [[SEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT1]](i32)
; CHECK-NEXT: BL @callee_signext_i1, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = call i32 @callee_signext_i1(i1 signext true)
ret i32 %r
@@ -158,9 +158,9 @@ define i32 @caller_signext_i1() {
define signext i1 @ret_signext_i1() {
; CHECK-LABEL: name: ret_signext_i1
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
- ; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[C]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i1 true
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
index 08021ccedb71b..6a2be75c34efd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
@@ -8,32 +8,32 @@ define [9 x i64] @callee_sret_demotion() {
; CHECK-NEXT: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD1]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD2]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD3]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD4]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD5]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD6]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C8]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD7]](p0) :: (store (s64))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD1]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD2]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD3]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD4]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD5]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD6]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C8]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD7]](p0) :: (store (i64))
; CHECK-NEXT: RET_ReallyLR
ret [9 x i64] zeroinitializer
}
@@ -46,32 +46,32 @@ define i64 @caller() {
; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @callee_sret_demotion, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD3]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD4]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C5]](s64)
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD5]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C6]](s64)
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C7]](s64)
- ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD7]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: $x0 = COPY [[LOAD4]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](i64)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD2]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C3]](i64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD3]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C4]](i64)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD4]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C5]](i64)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD5]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C6]](i64)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C7]](i64)
+ ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD7]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: $x0 = COPY [[LOAD4]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = call [9 x i64] @callee_sret_demotion()
%val = extractvalue [9 x i64] %res, 4
@@ -86,32 +86,32 @@ define i64 @caller_tail() {
; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @callee_sret_demotion, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD3]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD4]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C5]](s64)
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD5]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C6]](s64)
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C7]](s64)
- ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD7]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: $x0 = COPY [[LOAD4]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](i64)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD2]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C3]](i64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD3]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C4]](i64)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD4]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C5]](i64)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD5]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C6]](i64)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C7]](i64)
+ ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD7]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: $x0 = COPY [[LOAD4]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = tail call [9 x i64] @callee_sret_demotion()
%val = extractvalue [9 x i64] %res, 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
index e5db9c2baa88f..4149fb8e17058 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
@@ -6,10 +6,10 @@ define i8 @v1s8_add(<1 x i8> %a0) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8), [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[COPY]](<8 x i8>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = bitcast <1 x i8> %a0 to i8
ret i8 %res
@@ -20,14 +20,14 @@ define i24 @test_v3i8(<3 x i8> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[BUILD_VECTOR]](<3 x s32>)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s24) = G_BITCAST [[TRUNC]](<3 x s8>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](s24)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x i8>) = G_TRUNC [[BUILD_VECTOR]](<3 x i32>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i24) = G_BITCAST [[TRUNC]](<3 x i8>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](i24)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = bitcast <3 x i8> %a to i24
ret i24 %res
@@ -39,10 +39,11 @@ define <1 x half> @test_v1s16(<1 x float> %x) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[UV]](s32)
- ; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](s16)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[UV]](f32)
+ ; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](f16)
; CHECK-NEXT: RET_ReallyLR implicit $h0
%tmp = fptrunc <1 x float> %x to <1 x half>
ret <1 x half> %tmp
@@ -52,15 +53,15 @@ declare <3 x float> @bar(float)
define void @test_return_v3f32() {
; CHECK-LABEL: name: test_return_v3f32
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f32) = G_IMPLICIT_DEF
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $s0 = COPY [[DEF]](s32)
+ ; CHECK-NEXT: $s0 = COPY [[DEF]](f32)
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $q0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[UV]](f32), [[UV1]](f32), [[UV2]](f32)
; CHECK-NEXT: RET_ReallyLR
%call = call <3 x float> @bar(float undef)
ret void
@@ -70,13 +71,13 @@ declare void @foo(<3 x i32>)
define void @test_v3i32_arg() {
; CHECK-LABEL: name: test_v3i32_arg
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32), [[C]](i32)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR1]](<4 x s32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x i32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[UV]](i32), [[UV1]](i32), [[UV2]](i32), [[DEF]](i32)
+ ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR1]](<4 x i32>)
; CHECK-NEXT: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
index 02ab7a0772d89..3e6b8c1a1acd1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
@@ -6,25 +6,27 @@
define i8 @zeroext_param_i8(i8 zeroext %x) {
; CHECK-LABEL: name: zeroext_param_i8
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY]], 8
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i8 %x
}
define i8 @no_zeroext_param(i8 %x) {
; CHECK-LABEL: name: no_zeroext_param
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i8 %x
}
@@ -32,10 +34,11 @@ define i8 @no_zeroext_param(i8 %x) {
define i32 @zeroext_param_i32(i32 zeroext %x) {
; CHECK-LABEL: name: zeroext_param_i32
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: $w0 = COPY [[COPY]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i32 %x
}
@@ -43,24 +46,25 @@ define i32 @zeroext_param_i32(i32 zeroext %x) {
define i32 @zeroext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
; CHECK-LABEL: name: zeroext_param_stack
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
- ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
- ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 1
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
- ; CHECK: $w0 = COPY [[ZEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %g, i64 %h, i64 %i, i1 zeroext %j) {
%v = zext i1 %j to i32
ret i32 %v
@@ -70,21 +74,22 @@ define i32 @zeroext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
define i32 @dont_need_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK-LABEL: name: dont_need_assert_zext_stack
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
- ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.0, align 8)
- ; CHECK: $w0 = COPY [[LOAD1]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i32) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD1]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i,
i32 zeroext %j) {
ret i32 %j
@@ -94,24 +99,25 @@ define i32 @dont_need_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
define i8 @s8_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK-LABEL: name: s8_assert_zext_stack
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
- ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
- ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 8
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 8
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i,
i8 zeroext %j) {
ret i8 %j
@@ -122,11 +128,11 @@ define i32 @callee_zeroext_i1(i1 zeroext %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY]], 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = zext i1 %0 to i32
ret i32 %r
@@ -135,15 +141,15 @@ define i32 @callee_zeroext_i1(i1 zeroext %0) {
define i32 @caller_zeroext_i1() {
; CHECK-LABEL: name: caller_zeroext_i1
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[C]](s1)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT1]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[C]](i1)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT1]](i32)
; CHECK-NEXT: BL @callee_zeroext_i1, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = call i32 @callee_zeroext_i1(i1 zeroext true)
ret i32 %r
@@ -152,9 +158,9 @@ define i32 @caller_zeroext_i1() {
define zeroext i1 @ret_zeroext_i1() {
; CHECK-LABEL: name: ret_zeroext_i1
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s1)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[C]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i1 true
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
index 39860a73bcda4..4ac1adc0ee2f9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
@@ -1,18 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=irtranslator -enable-cse-in-irtranslator=1 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; CHECK-LABEL: name: test_split_struct
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load (s64) from %ir.ptr + 8)
+; CHECK: [[LO:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (i64) from %ir.ptr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: [[HI:%[0-9]+]]:_(i64) = G_LOAD [[GEP]](p0) :: (load (i64) from %ir.ptr + 8)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST2]](s64)
-; CHECK: G_STORE [[LO]](s64), [[GEP2]](p0) :: (store (s64) into stack, align 1)
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]](s64)
-; CHECK: G_STORE [[HI]](s64), [[GEP3]](p0) :: (store (s64) into stack + 8, align 1)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST2]](i64)
+; CHECK: G_STORE [[LO]](i64), [[GEP2]](p0) :: (store (i64) into stack, align 1)
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]](i64)
+; CHECK: G_STORE [[HI]](i64), [[GEP3]](p0) :: (store (i64) into stack + 8, align 1)
define void @test_split_struct(ptr %ptr) {
%struct = load [2 x i64], ptr %ptr
call void @take_split_struct(ptr null, i64 1, i64 2, i64 3,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
index b3e436bdfec4a..d5ffcb2b9b556 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
@@ -6,16 +7,16 @@
; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
-; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX]](p0) :: (invariant load (s8) from %fixed-stack.1, align 16)
-; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD]], 8
-; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
+; CHECK: [[LOAD:%[0-9]+]]:_(i32) = G_SEXTLOAD [[FRAME_INDEX]](p0) :: (invariant load (i8) from %fixed-stack.1, align 16)
+; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[LOAD]], 8
+; CHECK: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
-; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0)
-; CHECK: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 8
-; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT1]](s32)
-; CHECK: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
-; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ADD]](s8)
-; CHECK: $w0 = COPY [[SEXT]](s32)
+; CHECK: [[LOAD1:%[0-9]+]]:_(i32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0)
+; CHECK: [[ASSERT_SEXT1:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[LOAD1]], 8
+; CHECK: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT1]](i32)
+; CHECK: [[ADD:%[0-9]+]]:_(i8) = G_ADD [[TRUNC]], [[TRUNC1]]
+; CHECK: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[ADD]](i8)
+; CHECK: $w0 = COPY [[SEXT]](i32)
; CHECK: RET_ReallyLR implicit $w0
define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
%sum = add i8 %lhs, %rhs
@@ -23,15 +24,15 @@ define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs)
}
; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C42:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
-; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
+; CHECK: [[C42:%[0-9]+]]:_(i8) = G_CONSTANT i8 42
+; CHECK: [[C12:%[0-9]+]]:_(i8) = G_CONSTANT i8 12
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](s64)
-; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store (s8) into stack)
-; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](s64)
-; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store (s8) into stack + 1)
+; CHECK: [[C42_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](i64)
+; CHECK: G_STORE [[C42]](i8), [[C42_LOC]](p0) :: (store (i8) into stack)
+; CHECK: [[C12_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](i64)
+; CHECK: G_STORE [[C12]](i8), [[C12_LOC]](p0) :: (store (i8) into stack + 1)
; CHECK: BL @test_stack_slots
define void @test_call_stack() {
call signext i8 @test_stack_slots([8 x i64] undef, i8 signext 42, i8 signext 12)
@@ -51,26 +52,26 @@ define void @test_128bit_struct(ptr %ptr) {
; CHECK-LABEL: name: take_128bit_struct
; CHECK: {{%.*}}:_(p0) = COPY $x0
-; CHECK: {{%.*}}:_(s64) = COPY $x1
-; CHECK: {{%.*}}:_(s64) = COPY $x2
+; CHECK: {{%.*}}:_(i64) = COPY $x1
+; CHECK: {{%.*}}:_(i64) = COPY $x2
define void @take_128bit_struct(ptr %ptr, [2 x i64] %in) {
store [2 x i64] %in, ptr %ptr
ret void
}
; CHECK-LABEL: name: test_split_struct
-; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD %3(p0) :: (load (s64) from %ir.ptr + 8)
+; CHECK: [[LD1:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (i64) from %ir.ptr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i64) = G_LOAD %3(p0) :: (load (i64) from %ir.ptr + 8)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF]](s64)
-; CHECK: G_STORE [[LD1]](s64), [[ADDR]](p0) :: (store (s64) into stack, align 1)
+; CHECK: [[OFF:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF]](i64)
+; CHECK: G_STORE [[LD1]](i64), [[ADDR]](p0) :: (store (i64) into stack, align 1)
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]]
-; CHECK: G_STORE [[LD2]](s64), [[ADDR]](p0) :: (store (s64) into stack + 8, align 1)
+; CHECK: G_STORE [[LD2]](i64), [[ADDR]](p0) :: (store (i64) into stack + 8, align 1)
define void @test_split_struct(ptr %ptr) {
%struct = load [2 x i64], ptr %ptr
call void @take_split_struct(ptr null, i64 1, i64 2, i64 3,
@@ -85,10 +86,10 @@ define void @test_split_struct(ptr %ptr) {
; CHECK-DAG: - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
-; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load (s64) from %fixed-stack.[[LO_FRAME]], align 16)
+; CHECK: [[LO:%[0-9]+]]:_(i64) = G_LOAD [[LOPTR]](p0) :: (invariant load (i64) from %fixed-stack.[[LO_FRAME]], align 16)
; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
-; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load (s64) from %fixed-stack.[[HI_FRAME]])
+; CHECK: [[HI:%[0-9]+]]:_(i64) = G_LOAD [[HIPTR]](p0) :: (invariant load (i64) from %fixed-stack.[[HI_FRAME]])
define void @take_split_struct(ptr %ptr, i64, i64, i64,
i64, i64, i64,
[2 x i64] %in) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
index 0ff6ae28279f8..545d854f047ec 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
@@ -54,8 +54,8 @@ define void @dont_tail_call_explicit_sret_alloca_dummyusers(ptr %ptr) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.l
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.ptr)
- ; CHECK-NEXT: G_STORE [[LOAD]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %ir.l)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[COPY]](p0) :: (load (i64) from %ir.ptr)
+ ; CHECK-NEXT: G_STORE [[LOAD]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %ir.l)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
@@ -74,8 +74,8 @@ define void @dont_tail_call_tailcall_explicit_sret_gep(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x8 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
@@ -94,8 +94,8 @@ define i64 @dont_tail_call_sret_alloca_returned() {
; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.l)
- ; CHECK-NEXT: $x0 = COPY [[LOAD]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (i64) from %ir.l)
+ ; CHECK-NEXT: $x0 = COPY [[LOAD]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%l = alloca i64, align 8
tail call void @test_explicit_sret(ptr %l)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
index 9828cc8572cca..4328ccb94efe2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
@@ -7,6 +7,7 @@ define void @tail_call() {
; DARWIN-LABEL: name: tail_call
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: TCRETURNdi @simple_fn, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: tail_call
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: TCRETURNdi @simple_fn, 0, csr_aarch64_aapcs, implicit $sp
@@ -23,6 +24,7 @@ define void @indirect_tail_call(ptr %func) {
; DARWIN-NEXT: {{ $}}
; DARWIN-NEXT: [[COPY:%[0-9]+]]:tcgpr64(p0) = COPY $x0
; DARWIN-NEXT: TCRETURNri [[COPY]](p0), 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: indirect_tail_call
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $x0
@@ -39,15 +41,16 @@ define void @test_outgoing_args(i32 %a) {
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: liveins: $w0
; DARWIN-NEXT: {{ $}}
- ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; DARWIN-NEXT: $w0 = COPY [[COPY]](s32)
+ ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; DARWIN-NEXT: $w0 = COPY [[COPY]](i32)
; DARWIN-NEXT: TCRETURNdi @outgoing_args_fn, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $w0
+ ;
; WINDOWS-LABEL: name: test_outgoing_args
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $w0
; WINDOWS-NEXT: {{ $}}
- ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; WINDOWS-NEXT: $w0 = COPY [[COPY]](s32)
+ ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; WINDOWS-NEXT: $w0 = COPY [[COPY]](i32)
; WINDOWS-NEXT: TCRETURNdi @outgoing_args_fn, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0
tail call void @outgoing_args_fn(i32 %a)
ret void
@@ -62,33 +65,50 @@ define void @test_outgoing_stack_args([8 x <2 x double>], <4 x half> %arg) {
; DARWIN: bb.1 (%ir-block.1):
; DARWIN-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
; DARWIN-NEXT: {{ $}}
- ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; DARWIN-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; DARWIN-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; DARWIN-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $q4
- ; DARWIN-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $q5
- ; DARWIN-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $q6
- ; DARWIN-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $q7
+ ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; DARWIN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; DARWIN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; DARWIN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; DARWIN-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY4:%[0-9]+]]:_(<2 x i64>) = COPY $q4
+ ; DARWIN-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY4]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY5:%[0-9]+]]:_(<2 x i64>) = COPY $q5
+ ; DARWIN-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY5]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY6:%[0-9]+]]:_(<2 x i64>) = COPY $q6
+ ; DARWIN-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY6]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY7:%[0-9]+]]:_(<2 x i64>) = COPY $q7
+ ; DARWIN-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY7]](<2 x i64>)
; DARWIN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; DARWIN-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x s16>) from %fixed-stack.0, align 16)
- ; DARWIN-NEXT: $d0 = COPY [[LOAD]](<4 x s16>)
+ ; DARWIN-NEXT: [[LOAD:%[0-9]+]]:_(<4 x f16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x f16>) from %fixed-stack.0, align 16)
+ ; DARWIN-NEXT: $d0 = COPY [[LOAD]](<4 x f16>)
; DARWIN-NEXT: TCRETURNdi @outgoing_stack_args_fn, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $d0
+ ;
; WINDOWS-LABEL: name: test_outgoing_stack_args
; WINDOWS: bb.1 (%ir-block.1):
; WINDOWS-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
; WINDOWS-NEXT: {{ $}}
- ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; WINDOWS-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; WINDOWS-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; WINDOWS-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $q4
- ; WINDOWS-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $q5
- ; WINDOWS-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $q6
- ; WINDOWS-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $q7
+ ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; WINDOWS-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; WINDOWS-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; WINDOWS-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; WINDOWS-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY4:%[0-9]+]]:_(<2 x i64>) = COPY $q4
+ ; WINDOWS-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY4]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY5:%[0-9]+]]:_(<2 x i64>) = COPY $q5
+ ; WINDOWS-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY5]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY6:%[0-9]+]]:_(<2 x i64>) = COPY $q6
+ ; WINDOWS-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY6]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY7:%[0-9]+]]:_(<2 x i64>) = COPY $q7
+ ; WINDOWS-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY7]](<2 x i64>)
; WINDOWS-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; WINDOWS-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x s16>) from %fixed-stack.0, align 16)
- ; WINDOWS-NEXT: $d0 = COPY [[LOAD]](<4 x s16>)
+ ; WINDOWS-NEXT: [[LOAD:%[0-9]+]]:_(<4 x f16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x f16>) from %fixed-stack.0, align 16)
+ ; WINDOWS-NEXT: $d0 = COPY [[LOAD]](<4 x f16>)
; WINDOWS-NEXT: TCRETURNdi @outgoing_stack_args_fn, 0, csr_aarch64_aapcs, implicit $sp, implicit $d0
tail call void @outgoing_stack_args_fn(<4 x half> %arg)
ret void
@@ -100,55 +120,56 @@ declare i32 @too_big_stack(i64 %x0, i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5,
define i32 @test_too_big_stack() {
; DARWIN-LABEL: name: test_too_big_stack
; DARWIN: bb.1.entry:
- ; DARWIN-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; DARWIN-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 8
- ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
+ ; DARWIN-NEXT: [[DEF:%[0-9]+]]:_(i64) = G_IMPLICIT_DEF
+ ; DARWIN-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 8
+ ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 9
; DARWIN-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; DARWIN-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; DARWIN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; DARWIN-NEXT: G_STORE [[C1]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 2, align 1)
- ; DARWIN-NEXT: $x0 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x1 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x2 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x3 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x4 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x5 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x6 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x7 = COPY [[DEF]](s64)
+ ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](i64)
+ ; DARWIN-NEXT: G_STORE [[C]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; DARWIN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; DARWIN-NEXT: G_STORE [[C1]](i16), [[PTR_ADD1]](p0) :: (store (i16) into stack + 2, align 1)
+ ; DARWIN-NEXT: $x0 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x1 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x2 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x3 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x4 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x5 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x6 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x7 = COPY [[DEF]](i64)
; DARWIN-NEXT: BL @too_big_stack, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit-def $w0
; DARWIN-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit $sp
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
- ; DARWIN-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
+ ; DARWIN-NEXT: $w0 = COPY [[COPY1]](i32)
; DARWIN-NEXT: RET_ReallyLR implicit $w0
+ ;
; WINDOWS-LABEL: name: test_too_big_stack
; WINDOWS: bb.1.entry:
- ; WINDOWS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 8
- ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
+ ; WINDOWS-NEXT: [[DEF:%[0-9]+]]:_(i64) = G_IMPLICIT_DEF
+ ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 8
+ ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 9
; WINDOWS-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; WINDOWS-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; WINDOWS-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; WINDOWS-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; WINDOWS-NEXT: G_STORE [[C1]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 8, align 1)
- ; WINDOWS-NEXT: $x0 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x1 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x2 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x3 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x4 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x5 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x6 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x7 = COPY [[DEF]](s64)
+ ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; WINDOWS-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](i64)
+ ; WINDOWS-NEXT: G_STORE [[C]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; WINDOWS-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; WINDOWS-NEXT: G_STORE [[C1]](i16), [[PTR_ADD1]](p0) :: (store (i16) into stack + 8, align 1)
+ ; WINDOWS-NEXT: $x0 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x1 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x2 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x3 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x4 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x5 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x6 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x7 = COPY [[DEF]](i64)
; WINDOWS-NEXT: BL @too_big_stack, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit-def $w0
; WINDOWS-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
- ; WINDOWS-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
+ ; WINDOWS-NEXT: $w0 = COPY [[COPY1]](i32)
; WINDOWS-NEXT: RET_ReallyLR implicit $w0
entry:
%call = tail call i32 @too_big_stack(i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i8 8, i16 9)
@@ -163,6 +184,7 @@ define i32 @test_nonvoid_ret() {
; DARWIN-LABEL: name: test_nonvoid_ret
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: test_nonvoid_ret
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_aarch64_aapcs, implicit $sp
@@ -174,21 +196,22 @@ declare void @varargs(i32, double, i64, ...)
define void @test_varargs() {
; DARWIN-LABEL: name: test_varargs
; DARWIN: bb.1 (%ir-block.0):
- ; DARWIN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; DARWIN-NEXT: $w0 = COPY [[C]](s32)
- ; DARWIN-NEXT: $d0 = COPY [[C1]](s64)
- ; DARWIN-NEXT: $x1 = COPY [[C2]](s64)
+ ; DARWIN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; DARWIN-NEXT: $w0 = COPY [[C]](i32)
+ ; DARWIN-NEXT: $d0 = COPY [[C1]](f64)
+ ; DARWIN-NEXT: $x1 = COPY [[C2]](i64)
; DARWIN-NEXT: TCRETURNdi @varargs, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $w0, implicit $d0, implicit $x1
+ ;
; WINDOWS-LABEL: name: test_varargs
; WINDOWS: bb.1 (%ir-block.0):
- ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; WINDOWS-NEXT: $w0 = COPY [[C]](s32)
- ; WINDOWS-NEXT: $x1 = COPY [[C1]](s64)
- ; WINDOWS-NEXT: $x2 = COPY [[C2]](s64)
+ ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; WINDOWS-NEXT: $w0 = COPY [[C]](i32)
+ ; WINDOWS-NEXT: $x1 = COPY [[C1]](f64)
+ ; WINDOWS-NEXT: $x2 = COPY [[C2]](i64)
; WINDOWS-NEXT: TCRETURNdi @varargs, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0, implicit $x1, implicit $x2
tail call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12)
ret void
@@ -201,31 +224,32 @@ define void @test_varargs_2() {
; DARWIN-LABEL: name: test_varargs_2
; DARWIN: bb.1 (%ir-block.0):
- ; DARWIN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 314
+ ; DARWIN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 314
; DARWIN-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; DARWIN-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; DARWIN-NEXT: G_STORE [[C3]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 1)
- ; DARWIN-NEXT: $w0 = COPY [[C]](s32)
- ; DARWIN-NEXT: $d0 = COPY [[C1]](s64)
- ; DARWIN-NEXT: $x1 = COPY [[C2]](s64)
+ ; DARWIN-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](i64)
+ ; DARWIN-NEXT: G_STORE [[C3]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack, align 1)
+ ; DARWIN-NEXT: $w0 = COPY [[C]](i32)
+ ; DARWIN-NEXT: $d0 = COPY [[C1]](f64)
+ ; DARWIN-NEXT: $x1 = COPY [[C2]](i64)
; DARWIN-NEXT: BL @varargs, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1
; DARWIN-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_varargs_2
; WINDOWS: bb.1 (%ir-block.0):
- ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 314
- ; WINDOWS-NEXT: $w0 = COPY [[C]](s32)
- ; WINDOWS-NEXT: $x1 = COPY [[C1]](s64)
- ; WINDOWS-NEXT: $x2 = COPY [[C2]](s64)
- ; WINDOWS-NEXT: $x3 = COPY [[C3]](s64)
+ ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 314
+ ; WINDOWS-NEXT: $w0 = COPY [[C]](i32)
+ ; WINDOWS-NEXT: $x1 = COPY [[C1]](f64)
+ ; WINDOWS-NEXT: $x2 = COPY [[C2]](i64)
+ ; WINDOWS-NEXT: $x3 = COPY [[C3]](i64)
; WINDOWS-NEXT: TCRETURNdi @varargs, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0, implicit $x1, implicit $x2, implicit $x3
tail call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i64 314)
ret void
@@ -240,53 +264,70 @@ define void @test_varargs_3([8 x <2 x double>], <4 x half> %arg) {
; DARWIN: bb.1 (%ir-block.1):
; DARWIN-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
; DARWIN-NEXT: {{ $}}
- ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; DARWIN-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; DARWIN-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; DARWIN-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $q4
- ; DARWIN-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $q5
- ; DARWIN-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $q6
- ; DARWIN-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $q7
+ ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; DARWIN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; DARWIN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; DARWIN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; DARWIN-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY4:%[0-9]+]]:_(<2 x i64>) = COPY $q4
+ ; DARWIN-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY4]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY5:%[0-9]+]]:_(<2 x i64>) = COPY $q5
+ ; DARWIN-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY5]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY6:%[0-9]+]]:_(<2 x i64>) = COPY $q6
+ ; DARWIN-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY6]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY7:%[0-9]+]]:_(<2 x i64>) = COPY $q7
+ ; DARWIN-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY7]](<2 x i64>)
; DARWIN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; DARWIN-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x s16>) from %fixed-stack.0, align 16)
- ; DARWIN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 314
+ ; DARWIN-NEXT: [[LOAD:%[0-9]+]]:_(<4 x f16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x f16>) from %fixed-stack.0, align 16)
+ ; DARWIN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 314
; DARWIN-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: [[COPY8:%[0-9]+]]:_(p0) = COPY $sp
- ; DARWIN-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY8]], [[C4]](s64)
- ; DARWIN-NEXT: G_STORE [[C3]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 1)
- ; DARWIN-NEXT: $w0 = COPY [[C]](s32)
- ; DARWIN-NEXT: $d0 = COPY [[C1]](s64)
- ; DARWIN-NEXT: $x1 = COPY [[C2]](s64)
+ ; DARWIN-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY8]], [[C4]](i64)
+ ; DARWIN-NEXT: G_STORE [[C3]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack, align 1)
+ ; DARWIN-NEXT: $w0 = COPY [[C]](i32)
+ ; DARWIN-NEXT: $d0 = COPY [[C1]](f64)
+ ; DARWIN-NEXT: $x1 = COPY [[C2]](i64)
; DARWIN-NEXT: BL @varargs, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1
; DARWIN-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_varargs_3
; WINDOWS: bb.1 (%ir-block.1):
; WINDOWS-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
; WINDOWS-NEXT: {{ $}}
- ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; WINDOWS-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; WINDOWS-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; WINDOWS-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $q4
- ; WINDOWS-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $q5
- ; WINDOWS-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $q6
- ; WINDOWS-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $q7
+ ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; WINDOWS-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; WINDOWS-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; WINDOWS-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; WINDOWS-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY4:%[0-9]+]]:_(<2 x i64>) = COPY $q4
+ ; WINDOWS-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY4]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY5:%[0-9]+]]:_(<2 x i64>) = COPY $q5
+ ; WINDOWS-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY5]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY6:%[0-9]+]]:_(<2 x i64>) = COPY $q6
+ ; WINDOWS-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY6]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY7:%[0-9]+]]:_(<2 x i64>) = COPY $q7
+ ; WINDOWS-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY7]](<2 x i64>)
; WINDOWS-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; WINDOWS-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x s16>) from %fixed-stack.0, align 16)
- ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 314
- ; WINDOWS-NEXT: $w0 = COPY [[C]](s32)
- ; WINDOWS-NEXT: $x1 = COPY [[C1]](s64)
- ; WINDOWS-NEXT: $x2 = COPY [[C2]](s64)
- ; WINDOWS-NEXT: $x3 = COPY [[C3]](s64)
+ ; WINDOWS-NEXT: [[LOAD:%[0-9]+]]:_(<4 x f16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x f16>) from %fixed-stack.0, align 16)
+ ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 314
+ ; WINDOWS-NEXT: $w0 = COPY [[C]](i32)
+ ; WINDOWS-NEXT: $x1 = COPY [[C1]](f64)
+ ; WINDOWS-NEXT: $x2 = COPY [[C2]](i64)
+ ; WINDOWS-NEXT: $x3 = COPY [[C3]](i64)
; WINDOWS-NEXT: TCRETURNdi @varargs, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0, implicit $x1, implicit $x2, implicit $x3
tail call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i64 314)
ret void
@@ -302,6 +343,7 @@ define void @test_bad_call_conv() {
; DARWIN-NEXT: BL @bad_call_conv_fn, csr_aarch64_noregs, implicit-def $lr, implicit $sp
; DARWIN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_bad_call_conv
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
@@ -322,6 +364,7 @@ define void @test_byval(ptr byval(i8) %ptr) {
; DARWIN-NEXT: BL @simple_fn, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; DARWIN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_byval
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -345,6 +388,7 @@ define void @test_inreg(ptr inreg %ptr) {
; DARWIN-NEXT: BL @simple_fn, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; DARWIN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_inreg
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $x0
@@ -363,6 +407,7 @@ define void @test_mismatched_caller() {
; DARWIN-LABEL: name: test_mismatched_caller
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: TCRETURNdi @fast_fn, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: test_mismatched_caller
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: TCRETURNdi @fast_fn, 0, csr_aarch64_aapcs, implicit $sp
@@ -376,6 +421,7 @@ define void @test_assume() local_unnamed_addr {
; DARWIN-LABEL: name: test_assume
; DARWIN: bb.1.entry:
; DARWIN-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: test_assume
; WINDOWS: bb.1.entry:
; WINDOWS-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_aarch64_aapcs, implicit $sp
@@ -394,6 +440,7 @@ define void @test_lifetime() local_unnamed_addr {
; DARWIN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.t
; DARWIN-NEXT: LIFETIME_START %stack.0.t
; DARWIN-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: test_lifetime
; WINDOWS: bb.1.entry:
; WINDOWS-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.t
@@ -424,6 +471,7 @@ define hidden swiftcc i64 @swiftself_indirect_tail(ptr swiftself %arg) {
; DARWIN-NEXT: [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
; DARWIN-NEXT: $x20 = COPY [[COPY]](p0)
; DARWIN-NEXT: TCRETURNri [[COPY1]](p0), 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $x20
+ ;
; WINDOWS-LABEL: name: swiftself_indirect_tail
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $x20
@@ -451,6 +499,7 @@ define void @foo(ptr) {
; DARWIN-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; DARWIN-NEXT: $x0 = COPY [[C]](p0)
; DARWIN-NEXT: TCRETURNdi @must_callee, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $x0
+ ;
; WINDOWS-LABEL: name: foo
; WINDOWS: bb.1 (%ir-block.1):
; WINDOWS-NEXT: liveins: $x0
@@ -471,23 +520,24 @@ define void @test_tail_call_outgoing_v16f16(<16 x half> %arg) {
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: liveins: $q0, $q1
; DARWIN-NEXT: {{ $}}
- ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
- ; DARWIN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[COPY]](<8 x s16>), [[COPY1]](<8 x s16>)
- ; DARWIN-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>)
- ; DARWIN-NEXT: $q0 = COPY [[UV]](<8 x s16>)
- ; DARWIN-NEXT: $q1 = COPY [[UV1]](<8 x s16>)
+ ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<8 x f16>) = COPY $q1
+ ; DARWIN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x f16>) = G_CONCAT_VECTORS [[COPY]](<8 x f16>), [[COPY1]](<8 x f16>)
+ ; DARWIN-NEXT: [[UV:%[0-9]+]]:_(<8 x f16>), [[UV1:%[0-9]+]]:_(<8 x f16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f16>)
+ ; DARWIN-NEXT: $q0 = COPY [[UV]](<8 x f16>)
+ ; DARWIN-NEXT: $q1 = COPY [[UV1]](<8 x f16>)
; DARWIN-NEXT: TCRETURNdi @outgoing_v16f16, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1
+ ;
; WINDOWS-LABEL: name: test_tail_call_outgoing_v16f16
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $q0, $q1
; WINDOWS-NEXT: {{ $}}
- ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
- ; WINDOWS-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[COPY]](<8 x s16>), [[COPY1]](<8 x s16>)
- ; WINDOWS-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>)
- ; WINDOWS-NEXT: $q0 = COPY [[UV]](<8 x s16>)
- ; WINDOWS-NEXT: $q1 = COPY [[UV1]](<8 x s16>)
+ ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<8 x f16>) = COPY $q1
+ ; WINDOWS-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x f16>) = G_CONCAT_VECTORS [[COPY]](<8 x f16>), [[COPY1]](<8 x f16>)
+ ; WINDOWS-NEXT: [[UV:%[0-9]+]]:_(<8 x f16>), [[UV1:%[0-9]+]]:_(<8 x f16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f16>)
+ ; WINDOWS-NEXT: $q0 = COPY [[UV]](<8 x f16>)
+ ; WINDOWS-NEXT: $q1 = COPY [[UV1]](<8 x f16>)
; WINDOWS-NEXT: TCRETURNdi @outgoing_v16f16, 0, csr_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1
tail call void @outgoing_v16f16(<16 x half> %arg)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
index 36529be38253e..25baf6a295b14 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
@@ -12,7 +12,7 @@ define void @test_trivial_call() {
; CHECK-LABEL: name: test_simple_return
; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY $x0
+; CHECK: [[RES:%[0-9]+]]:_(i64) = COPY $x0
; CHECK: $x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit $x0
declare i64 @simple_return_callee()
@@ -22,7 +22,7 @@ define i64 @test_simple_return() {
}
; CHECK-LABEL: name: test_simple_arg
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
; CHECK: $w0 = COPY [[IN]]
; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: RET_ReallyLR
@@ -45,8 +45,8 @@ define void @test_indirect_call(ptr %func) {
}
; CHECK-LABEL: name: test_multiple_args
-; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[IN:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[ANSWER:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK: $w0 = COPY [[ANSWER]]
; CHECK: $x1 = COPY [[IN]]
; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $x1
@@ -59,19 +59,19 @@ define void @test_multiple_args(i64 %in) {
; CHECK-LABEL: name: test_struct_formal
-; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[I8:%[0-9]+]]:_(s8) = G_TRUNC [[I8_C]]
+; CHECK: [[DBL:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[I64:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[I8_C:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[I8:%[0-9]+]]:_(i8) = G_TRUNC [[I8_C]]
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: G_STORE [[DBL]](s64), [[ADDR]](p0) :: (store (s64) into %ir.addr)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)
-; CHECK: G_STORE [[I64]](s64), [[GEP1]](p0) :: (store (s64) into %ir.addr + 8)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST2]](s64)
-; CHECK: G_STORE [[I8]](s8), [[GEP2]](p0) :: (store (s8) into %ir.addr + 16, align 8)
+; CHECK: G_STORE [[DBL]](f64), [[ADDR]](p0) :: (store (f64) into %ir.addr)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](i64)
+; CHECK: G_STORE [[I64]](i64), [[GEP1]](p0) :: (store (i64) into %ir.addr + 8)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST2]](i64)
+; CHECK: G_STORE [[I8]](i8), [[GEP2]](p0) :: (store (i8) into %ir.addr + 16, align 8)
; CHECK: RET_ReallyLR
define void @test_struct_formal({double, i64, i8} %in, ptr %addr) {
store {double, i64, i8} %in, ptr %addr
@@ -82,17 +82,17 @@ define void @test_struct_formal({double, i64, i8} %in, ptr %addr) {
; CHECK-LABEL: name: test_struct_return
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load (s64) from %ir.addr + 8)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 16, align 8)
-
-; CHECK: $d0 = COPY [[LD1]](s64)
-; CHECK: $x0 = COPY [[LD2]](s64)
-; CHECK: $w1 = COPY [[LD3]](s32)
+; CHECK: [[LD1:%[0-9]+]]:_(f64) = G_LOAD [[ADDR]](p0) :: (load (f64) from %ir.addr)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i64) = G_LOAD [[GEP1]](p0) :: (load (i64) from %ir.addr + 8)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.addr + 16, align 8)
+
+; CHECK: $d0 = COPY [[LD1]](f64)
+; CHECK: $x0 = COPY [[LD2]](i64)
+; CHECK: $w1 = COPY [[LD3]](i32)
; CHECK: RET_ReallyLR implicit $d0, implicit $x0, implicit $w1
define {double, i64, i32} @test_struct_return(ptr %addr) {
%val = load {double, i64, i32}, ptr %addr
@@ -101,26 +101,26 @@ define {double, i64, i32} @test_struct_return(ptr %addr) {
; CHECK-LABEL: name: test_arr_call
; CHECK: %0:_(p0) = COPY $x0
-; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.addr)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load (s64) from %ir.addr + 8)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s64) = G_LOAD [[GEP2]](p0) :: (load (s64) from %ir.addr + 16)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s64) = G_LOAD [[GEP3]](p0) :: (load (s64) from %ir.addr + 24)
-
-; CHECK: $x0 = COPY [[LD1]](s64)
-; CHECK: $x1 = COPY [[LD2]](s64)
-; CHECK: $x2 = COPY [[LD3]](s64)
-; CHECK: $x3 = COPY [[LD4]](s64)
+; CHECK: [[LD1:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (i64) from %ir.addr)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i64) = G_LOAD [[GEP1]](p0) :: (load (i64) from %ir.addr + 8)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i64) = G_LOAD [[GEP2]](p0) :: (load (i64) from %ir.addr + 16)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i64) = G_LOAD [[GEP3]](p0) :: (load (i64) from %ir.addr + 24)
+
+; CHECK: $x0 = COPY [[LD1]](i64)
+; CHECK: $x1 = COPY [[LD2]](i64)
+; CHECK: $x2 = COPY [[LD3]](i64)
+; CHECK: $x3 = COPY [[LD4]](i64)
; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1, implicit-def $x2, implicit-def $x3
-; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY $x3
+; CHECK: [[E0:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[E1:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK: [[E2:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: [[E3:%[0-9]+]]:_(i64) = COPY $x3
; CHECK: $x0 = COPY [[E1]]
declare [4 x i64] @arr_callee([4 x i64])
define i64 @test_arr_call(ptr %addr) {
@@ -132,15 +132,15 @@ define i64 @test_arr_call(ptr %addr) {
; CHECK-LABEL: name: test_abi_exts_call
-; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
-; CHECK: [[VAL_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[VAL]]
+; CHECK: [[VAL:%[0-9]+]]:_(i8) = G_LOAD
+; CHECK: [[VAL_TMP:%[0-9]+]]:_(i32) = G_ANYEXT [[VAL]]
; CHECK: $w0 = COPY [[VAL_TMP]]
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
-; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
-; CHECK: $w0 = COPY [[SVAL]](s32)
+; CHECK: [[SVAL:%[0-9]+]]:_(i32) = G_SEXT [[VAL]](i8)
+; CHECK: $w0 = COPY [[SVAL]](i32)
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
-; CHECK: [[ZVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
-; CHECK: $w0 = COPY [[ZVAL]](s32)
+; CHECK: [[ZVAL:%[0-9]+]]:_(i32) = G_ZEXT [[VAL]](i8)
+; CHECK: $w0 = COPY [[ZVAL]](i32)
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
declare void @take_char(i8)
define void @test_abi_exts_call(ptr %addr) {
@@ -155,10 +155,10 @@ define void @test_abi_exts_call(ptr %addr) {
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.addr)
+; CHECK: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (load (i8) from %ir.addr)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
-; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s8)
-; CHECK: $w0 = COPY [[ZEXT]](s32)
+; CHECK: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD]](i8)
+; CHECK: $w0 = COPY [[ZEXT]](i32)
; CHECK: BL @has_zext_param, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: RET_ReallyLR
@@ -173,10 +173,10 @@ define void @test_zext_in_callee(ptr %addr) {
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.addr)
+; CHECK: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (load (i8) from %ir.addr)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
-; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s8)
-; CHECK: $w0 = COPY [[SEXT]](s32)
+; CHECK: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD]](i8)
+; CHECK: $w0 = COPY [[SEXT]](i32)
; CHECK: BL @has_sext_param, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: RET_ReallyLR
@@ -188,9 +188,9 @@ define void @test_sext_in_callee(ptr %addr) {
}
; CHECK-LABEL: name: test_abi_sext_ret
-; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
-; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
-; CHECK: $w0 = COPY [[SVAL]](s32)
+; CHECK: [[VAL:%[0-9]+]]:_(i8) = G_LOAD
+; CHECK: [[SVAL:%[0-9]+]]:_(i32) = G_SEXT [[VAL]](i8)
+; CHECK: $w0 = COPY [[SVAL]](i32)
; CHECK: RET_ReallyLR implicit $w0
define signext i8 @test_abi_sext_ret(ptr %addr) {
%val = load i8, ptr %addr
@@ -198,9 +198,9 @@ define signext i8 @test_abi_sext_ret(ptr %addr) {
}
; CHECK-LABEL: name: test_abi_zext_ret
-; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
-; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
-; CHECK: $w0 = COPY [[SVAL]](s32)
+; CHECK: [[VAL:%[0-9]+]]:_(i8) = G_LOAD
+; CHECK: [[SVAL:%[0-9]+]]:_(i32) = G_ZEXT [[VAL]](i8)
+; CHECK: $w0 = COPY [[SVAL]](i32)
; CHECK: RET_ReallyLR implicit $w0
define zeroext i8 @test_abi_zext_ret(ptr %addr) {
%val = load i8, ptr %addr
@@ -213,13 +213,13 @@ define zeroext i8 @test_abi_zext_ret(ptr %addr) {
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8,
; CHECK-DAG: - { id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 8,
; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; CHECK: [[LHS:%[0-9]+]]:_(s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load (s64) from %fixed-stack.[[STACK0]], align 16)
+; CHECK: [[LHS:%[0-9]+]]:_(i64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load (i64) from %fixed-stack.[[STACK0]], align 16)
; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; CHECK: [[RHS:%[0-9]+]]:_(s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load (s64) from %fixed-stack.[[STACK8]])
+; CHECK: [[RHS:%[0-9]+]]:_(i64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load (i64) from %fixed-stack.[[STACK8]])
; CHECK: [[ADDR_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load (p0) from %fixed-stack.[[STACK16]], align 16)
-; CHECK: [[SUM:%[0-9]+]]:_(s64) = G_ADD [[LHS]], [[RHS]]
-; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0)
+; CHECK: [[SUM:%[0-9]+]]:_(i64) = G_ADD [[LHS]], [[RHS]]
+; CHECK: G_STORE [[SUM]](i64), [[ADDR]](p0)
define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, ptr %addr) {
%sum = add i64 %lhs, %rhs
store i64 %sum, ptr %addr
@@ -227,19 +227,19 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, ptr %addr) {
}
; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C42:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
-; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+; CHECK: [[C42:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+; CHECK: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](s64)
-; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store (s64) into stack, align 1)
-; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](s64)
-; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store (s64) into stack + 8, align 1)
-; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[PTR_OFFS]](s64)
+; CHECK: [[C42_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](i64)
+; CHECK: G_STORE [[C42]](i64), [[C42_LOC]](p0) :: (store (i64) into stack, align 1)
+; CHECK: [[C12_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](i64)
+; CHECK: G_STORE [[C12]](i64), [[C12_LOC]](p0) :: (store (i64) into stack + 8, align 1)
+; CHECK: [[PTR_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[PTR_OFFS]](i64)
; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store (p0) into stack + 16, align 1)
; CHECK: BL @test_stack_slots
; CHECK: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
@@ -253,10 +253,10 @@ define void @test_call_stack() {
; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, stack-id: default,
; CHECK-NEXT: isImmutable: true,
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
-; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[ADDR]](p0) :: (invariant load (s8) from %fixed-stack.[[SLOT]], align 16)
-; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[LOAD]]
-; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC8]], 1
-; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[TRUNCASSERT]]
+; CHECK: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[ADDR]](p0) :: (invariant load (i8) from %fixed-stack.[[SLOT]], align 16)
+; CHECK: [[TRUNC8:%[0-9]+]]:_(i8) = G_TRUNC [[LOAD]]
+; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC8]], 1
+; CHECK: {{%[0-9]+}}:_(i1) = G_TRUNC [[TRUNCASSERT]]
define void @test_mem_i1([8 x i64], i1 %in) {
ret void
@@ -275,8 +275,8 @@ define void @test_128bit_struct(ptr %ptr) {
; CHECK-LABEL: name: take_128bit_struct
; CHECK: {{%.*}}:_(p0) = COPY $x0
-; CHECK: {{%.*}}:_(s64) = COPY $x1
-; CHECK: {{%.*}}:_(s64) = COPY $x2
+; CHECK: {{%.*}}:_(i64) = COPY $x1
+; CHECK: {{%.*}}:_(i64) = COPY $x2
define void @take_128bit_struct(ptr %ptr, [2 x i64] %in) {
store [2 x i64] %in, ptr %ptr
ret void
@@ -284,17 +284,17 @@ define void @take_128bit_struct(ptr %ptr, [2 x i64] %in) {
; CHECK-LABEL: name: test_split_struct
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load (s64) from %ir.ptr + 8)
+; CHECK: [[LO:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (i64) from %ir.ptr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: [[HI:%[0-9]+]]:_(i64) = G_LOAD [[GEP]](p0) :: (load (i64) from %ir.ptr + 8)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST2]](s64)
-; CHECK: G_STORE [[LO]](s64), [[GEP2]](p0) :: (store (s64) into stack, align 1)
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]](s64)
-; CHECK: G_STORE [[HI]](s64), [[GEP3]](p0) :: (store (s64) into stack + 8, align 1)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST2]](i64)
+; CHECK: G_STORE [[LO]](i64), [[GEP2]](p0) :: (store (i64) into stack, align 1)
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]](i64)
+; CHECK: G_STORE [[HI]](i64), [[GEP3]](p0) :: (store (i64) into stack + 8, align 1)
define void @test_split_struct(ptr %ptr) {
%struct = load [2 x i64], ptr %ptr
call void @take_split_struct(ptr null, i64 1, i64 2, i64 3,
@@ -309,10 +309,10 @@ define void @test_split_struct(ptr %ptr) {
; CHECK-DAG: - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
-; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load (s64) from %fixed-stack.[[LO_FRAME]], align 16)
+; CHECK: [[LO:%[0-9]+]]:_(i64) = G_LOAD [[LOPTR]](p0) :: (invariant load (i64) from %fixed-stack.[[LO_FRAME]], align 16)
; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
-; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load (s64) from %fixed-stack.[[HI_FRAME]])
+; CHECK: [[HI:%[0-9]+]]:_(i64) = G_LOAD [[HIPTR]](p0) :: (invariant load (i64) from %fixed-stack.[[HI_FRAME]])
define void @take_split_struct(ptr %ptr, i64, i64, i64,
i64, i64, i64,
[2 x i64] %in) {
@@ -373,11 +373,11 @@ define i32 @test_zext_return_from_callee() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_zext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY]], 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%val = call i16 @has_zext_return()
%ext = zext i16 %val to i32
@@ -392,11 +392,11 @@ define i32 @test_zext_return_from_callee2() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_zext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY]], 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%val = call zeroext i16 @has_zext_return()
%ext = zext i16 %val to i32
@@ -412,11 +412,11 @@ define i32 @test_sext_return_from_callee() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_sext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY]], 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%val = call i16 @has_sext_return()
%ext = sext i16 %val to i32
@@ -431,11 +431,11 @@ define i32 @test_sext_return_from_callee2() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_sext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY]], 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%val = call signext i16 @has_sext_return()
%ext = sext i16 %val to i32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
index f427f8648a301..e5e6517f6391f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
@@ -266,10 +266,10 @@ name: test_combine_unmerge_fpcst
body: |
bb.1:
; CHECK-LABEL: name: test_combine_unmerge_fpcst
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4400
; CHECK-NEXT: $h0 = COPY [[C]](s16)
; CHECK-NEXT: $h1 = COPY [[C1]](s16)
; CHECK-NEXT: $h2 = COPY [[C2]](s16)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
index cae1b3949dca7..07cf87fe4bcc8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
@@ -9,8 +9,8 @@ define ptr @test_simple_load_pre(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(s8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](s64), 1 :: (volatile load (s8) from %ir.next)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](i64), 1 :: (volatile load (i8) from %ir.next)
; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%next = getelementptr i8, ptr %ptr, i32 42
@@ -25,9 +25,9 @@ define ptr @test_unused_load_pre(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (s8) from %ir.next)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (i8) from %ir.next)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY [[C1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -43,9 +43,9 @@ define ptr @test_simple_store_pre(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
- ; CHECK-NEXT: [[INDEXED_STORE:%[0-9]+]]:_(p0) = G_INDEXED_STORE [[C1]](s8), [[COPY]], [[C]](s64), 1 :: (volatile store (s8) into %ir.next)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i8) = G_CONSTANT i8 0
+ ; CHECK-NEXT: [[INDEXED_STORE:%[0-9]+]]:_(p0) = G_INDEXED_STORE [[C1]](i8), [[COPY]], [[C]](i64), 1 :: (volatile store (i8) into %ir.next)
; CHECK-NEXT: $x0 = COPY [[INDEXED_STORE]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%next = getelementptr i8, ptr %ptr, i32 42
@@ -62,8 +62,8 @@ define ptr @test_store_pre_val_loop(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 336
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 336
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[PTR_ADD]](p0) :: (volatile store (p0) into %ir.next)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -81,12 +81,12 @@ define ptr @test_load_pre_before(ptr %ptr) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: BL @bar, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (s8) from %ir.next)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (i8) from %ir.next)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%next = getelementptr i8, ptr %ptr, i32 42
@@ -101,10 +101,10 @@ define ptr @test_alloca_load_pre() {
; CHECK-LABEL: name: test_alloca_load_pre
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (s8) from %ir.next)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (i8) from %ir.next)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%ptr = alloca i8, i32 128
@@ -120,8 +120,8 @@ define ptr @test_simple_load_post(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(s8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](s64), 0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](i64), 0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%next = getelementptr i8, ptr %ptr, i32 42
@@ -139,8 +139,8 @@ define ptr @test_simple_load_post_gep_after(ptr %ptr) {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(s8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](s64), 0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](i64), 0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%offset = call i64 @get_offset()
@@ -159,13 +159,13 @@ define ptr @test_load_post_keep_looking(ptr %ptr) {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(s8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](s64), 0 :: (volatile load (s8) from %ir.ptr)
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](i64), 0 :: (volatile load (i8) from %ir.ptr)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[PTRTOINT]](i64)
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var
; CHECK-NEXT: [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var
- ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[ADD_LOW]](p0) :: (store (s8) into @var)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i8), [[ADD_LOW]](p0) :: (store (i8) into @var)
; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%offset = call i64 @get_offset()
@@ -183,9 +183,9 @@ define ptr @test_load_post_alloca() {
; CHECK-LABEL: name: test_load_post_alloca
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (volatile load (s8) from %ir.ptr)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[FRAME_INDEX]](p0) :: (volatile load (i8) from %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%ptr = alloca i8, i32 128
@@ -202,12 +202,12 @@ define ptr @test_load_post_gep_offset_after(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[COPY1]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
load volatile i8, ptr %ptr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
index 5e667eba741aa..32394c4c6f0a7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
@@ -12,26 +12,26 @@ define i32 @main() #0 !dbg !14 {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.retval)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0), debug-location !17 :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C1]], debug-location !19
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2, debug-location !20
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %ir.retval)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV]](p0), debug-location !17 :: (dereferenceable load (i32) from @var1)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C1]], debug-location !19
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2, debug-location !20
; CHECK-NEXT: G_BR %bb.3, debug-location !20
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: G_STORE [[C2]](s32), [[GV1]](p0), debug-location !21 :: (store (s32) into @var2)
+ ; CHECK-NEXT: G_STORE [[C2]](i32), [[GV1]](p0), debug-location !21 :: (store (i32) into @var2)
; CHECK-NEXT: G_BR %bb.3, debug-location !23
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
- ; CHECK-NEXT: $w0 = COPY [[C]](s32), debug-location !24
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32), debug-location !24
; CHECK-NEXT: RET_ReallyLR implicit $w0, debug-location !24
entry:
%retval = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll b/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
index 64fde65bf8b5e..d24d1f822e4ac 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
@@ -31,11 +31,11 @@ entry:
; CHECK-LABEL: name: debug_value
; CHECK: stack:
; CHECK: - { id: {{.*}}, name: addr
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
define void @debug_value(i32 %in) #0 !dbg !16 {
; CHECK: G_FRAME_INDEX %[[stack_slot:.*]]
%addr = alloca i32
-; CHECK: DBG_VALUE [[IN]](s32), $noreg, !17, !DIExpression(), debug-location !18
+; CHECK: DBG_VALUE [[IN]](i32), $noreg, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
store i32 %in, ptr %addr
; CHECK: DBG_VALUE %[[stack_slot]], 0, !17, !DIExpression(), debug-location !18
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll b/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
index 88eaa1382d1d6..f46cc65b5c60f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
@@ -4,18 +4,19 @@
define ptr @test_simple_alloca(i32 %numelts) {
; CHECK-LABEL: name: test_simple_alloca
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
- ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
- ; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
- ; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY]](i32)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = nuw G_ADD [[MUL]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -16
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ADD]], [[C2]]
+ ; CHECK-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](i64), 1
+ ; CHECK-NEXT: $x0 = COPY [[DYN_STACKALLOC]](p0)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%addr = alloca i8, i32 %numelts
ret ptr %addr
}
@@ -23,18 +24,19 @@ define ptr @test_simple_alloca(i32 %numelts) {
define ptr @test_aligned_alloca(i32 %numelts) {
; CHECK-LABEL: name: test_aligned_alloca
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
- ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
- ; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 32
- ; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY]](i32)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = nuw G_ADD [[MUL]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -16
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ADD]], [[C2]]
+ ; CHECK-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](i64), 32
+ ; CHECK-NEXT: $x0 = COPY [[DYN_STACKALLOC]](p0)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%addr = alloca i8, i32 %numelts, align 32
ret ptr %addr
}
@@ -42,18 +44,19 @@ define ptr @test_aligned_alloca(i32 %numelts) {
define ptr @test_natural_alloca(i32 %numelts) {
; CHECK-LABEL: name: test_natural_alloca
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
- ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
- ; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
- ; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY]](i32)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = nuw G_ADD [[MUL]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -16
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ADD]], [[C2]]
+ ; CHECK-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](i64), 1
+ ; CHECK-NEXT: $x0 = COPY [[DYN_STACKALLOC]](p0)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%addr = alloca i128, i32 %numelts
ret ptr %addr
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
index c1c918ff64a6c..6281c2f5c0a78 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
@@ -5,7 +5,7 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios5.0.0"
define float @main() #0 !dbg !14 {
-; CHECK: %0:_(s32) = G_FCONSTANT float 0.000000e+00
+; CHECK: %0:_(f32) = G_FCONSTANT float 0.000000e+00
ret float 0.000000e+00, !dbg !24
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
index cb01154a872bb..c499984775e89 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
@@ -35,13 +35,13 @@ body: |
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %2, %1
- $w1 = COPY %5(s32)
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(oeq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %2, %1
+ $w1 = COPY %5(f32)
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -68,14 +68,14 @@ body: |
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: $s1 = COPY [[FCSELSrrr1]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %2, %1
- %7:fpr(s32) = G_SELECT %5, %1, %2
- $s0 = COPY %4(s32)
- $s1 = COPY %7(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(oeq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %2, %1
+ %7:fpr(f32) = G_SELECT %5, %1, %2
+ $s0 = COPY %4(f32)
+ $s1 = COPY %7(f32)
RET_ReallyLR implicit $s0
...
@@ -99,13 +99,13 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:gpr(s32) = COPY $w0
- %1:fpr(s32) = COPY $s0
- %2:gpr(s32) = G_CONSTANT i32 0
- %5:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %6:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %6, %1, %5
- $s0 = COPY %4(s32)
+ %0:gpr(f32) = COPY $w0
+ %1:fpr(f32) = COPY $s0
+ %2:gpr(f32) = G_CONSTANT i32 0
+ %5:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %6:gpr(f32) = G_ICMP intpred(eq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %6, %1, %5
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -129,12 +129,12 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %2, %1
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(oeq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %2, %1
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -162,12 +162,12 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %2, %1
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(ueq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %2, %1
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -195,12 +195,12 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(one), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %1, %2
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(one), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %1, %2
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -224,12 +224,12 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(une), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %1, %2
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(une), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %1, %2
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -253,12 +253,12 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
- %4:fpr(s64) = G_SELECT %5, %2, %1
- $d0 = COPY %4(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(oeq), %0(f64), %2
+ %4:fpr(f64) = G_SELECT %5, %2, %1
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -286,12 +286,12 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s64), %2
- %4:fpr(s64) = G_SELECT %5, %2, %1
- $d0 = COPY %4(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(ueq), %0(f64), %2
+ %4:fpr(f64) = G_SELECT %5, %2, %1
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -319,12 +319,12 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(one), %0(s64), %2
- %4:fpr(s64) = G_SELECT %5, %1, %2
- $d0 = COPY %4(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(one), %0(f64), %2
+ %4:fpr(f64) = G_SELECT %5, %1, %2
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -348,12 +348,12 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(une), %0(s64), %2
- %4:fpr(s64) = G_SELECT %5, %1, %2
- $d0 = COPY %4(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(une), %0(f64), %2
+ %4:fpr(f64) = G_SELECT %5, %1, %2
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -379,13 +379,13 @@ body: |
; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:gpr(s32) = COPY $w0
- %1:fpr(s32) = COPY $s0
- %5:fpr(s32) = G_FCONSTANT float 0.000000e+00
+ %0:gpr(f32) = COPY $w0
+ %1:fpr(f32) = COPY $s0
+ %5:fpr(f32) = G_FCONSTANT float 0.000000e+00
BL @copy_from_physreg, implicit-def $w0
- %4:fpr(s32) = G_SELECT %5, %1, %5
+ %4:fpr(f32) = G_SELECT %5, %1, %5
BL @copy_from_physreg, implicit-def $w0
- $s0 = COPY %4(s32)
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
index 1c0fc3fb36a0d..1e3855cf534a4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
@@ -35,48 +35,48 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD5]](s128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 96
; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](s64)
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD6]](s128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD6]](f128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 112
; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](s64)
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD7]](s128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD7]](f128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 127
; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](s64)
- ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
+ ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD8]](s128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
+ ; CHECK-NEXT: G_STORE [[LOAD8]](f128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
index b040ff2932ce8..c33e5641b1acb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
@@ -108,23 +108,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
@@ -156,23 +156,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
@@ -232,48 +232,48 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD5]](s128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 96
; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](s64)
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD6]](s128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD6]](f128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 112
; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](s64)
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD7]](s128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD7]](f128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 127
; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](s64)
- ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
+ ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD8]](s128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
+ ; CHECK-NEXT: G_STORE [[LOAD8]](f128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
@@ -300,23 +300,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p2) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p2) :: (load (s128) from %ir.1 + 48, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p2) :: (load (s128) from %ir.1 + 48, align 4, addrspace 2)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p1) :: (store (s128) into %ir.0 + 48, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p1) :: (store (s128) into %ir.0 + 48, align 4, addrspace 1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p2) :: (load (s64) from %ir.1 + 64, align 4, addrspace 2)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
index f24aeaed1d8bc..b06b064b361de 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
@@ -87,20 +87,20 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD2]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD2]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
@@ -122,38 +122,38 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD3]](p0) :: (load (s128) from %ir.1 + 64, align 4)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD3]](p0) :: (load (s128) from %ir.1 + 64, align 4)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 80, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 80, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD6]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD6]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C8]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s128), [[PTR_ADD8]](p0) :: (store (s128) into %ir.0 + 64, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD8]](p0) :: (store (s128) into %ir.0 + 64, align 4)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C9]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD5]](s128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
@@ -175,23 +175,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.1 + 48)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD4]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD4]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
; CHECK-NEXT: G_STORE [[LOAD3]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %ir.0 + 48)
@@ -216,20 +216,20 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p2) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD2]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD2]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p1) = COPY $x0
%1:_(p2) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
index e4d2ca32468f6..e5f444154f5fd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
@@ -95,13 +95,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK-NEXT: G_STORE [[MUL]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: G_STORE [[MUL]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[MUL]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)
+ ; CHECK-NEXT: G_STORE [[MUL]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
@@ -123,18 +123,18 @@ body: |
; CHECK: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %ir.dst + 16, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD]](p0) :: (store (<2 x i64>) into %ir.dst + 16, align 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into %ir.dst + 32, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD1]](p0) :: (store (<2 x i64>) into %ir.dst + 32, align 1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into %ir.dst + 48, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into %ir.dst + 48, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 0
@@ -157,11 +157,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4629771061636907072
- ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 64
@@ -184,20 +184,20 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %ir.dst + 16, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD]](p0) :: (store (<2 x i64>) into %ir.dst + 16, align 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into %ir.dst + 32, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD1]](p0) :: (store (<2 x i64>) into %ir.dst + 32, align 1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into %ir.dst + 44, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into %ir.dst + 44, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
@@ -219,11 +219,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4629771061636907072
- ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 16448
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
@@ -249,13 +249,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK-NEXT: G_STORE [[MUL]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: G_STORE [[MUL]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[MUL]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)
+ ; CHECK-NEXT: G_STORE [[MUL]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
index 73930911e304f..bd73e6870a14e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
@@ -43,13 +43,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll b/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
index 38b9558f426f2..21402fade53dd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
@@ -4,9 +4,9 @@
define dso_local void @fn() {
; CHECK-LABEL: fn:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, #4132
-; CHECK-NEXT: mov w9, #1
-; CHECK-NEXT: movk x8, #65489, lsl #16
+; CHECK-NEXT: mov w8, #4132 // =0x1024
+; CHECK-NEXT: mov w9, #1 // =0x1
+; CHECK-NEXT: movk w8, #65489, lsl #16
; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
index 39ad002a0763f..ecf5aeee05896 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
@@ -13,10 +13,10 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
@@ -29,19 +29,19 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C1]](i32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV1]](p0) :: (store (s32) into @global_var)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV1]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[C2]](s16), %bb.1, [[C3]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(i16) = G_PHI [[C2]](i16), %bb.1, [[C3]](i16), %bb.2
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[PHI1]](i16)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
store i32 42, ptr @global_var
invoke void @may_throw()
@@ -68,12 +68,12 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.ptr)
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ASSERT_ZEXT]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (load (i8) from %ir.ptr)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[LOAD]], 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[ASSERT_ZEXT]](i8)
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
@@ -86,19 +86,19 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C1]](i32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV1]](p0) :: (store (s32) into @global_var)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV1]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[ANYEXT]](s16), %bb.1, [[C2]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(i16) = G_PHI [[ANYEXT]](i16), %bb.1, [[C2]](i16), %bb.2
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[PHI1]](i16)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
store i32 42, ptr @global_var
%v = load i1, ptr %ptr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll
index 0173f92c98220..5dbd18a148222 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll
@@ -7,11 +7,11 @@ define <2 x i1> @call_icmp_samesign_vector(<2 x i32> %a, <2 x i32> %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: %2:_(<2 x s1>) = samesign G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i1>) = samesign G_ICMP intpred(ult), [[COPY]](<2 x i32>), [[COPY1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i32>) = G_ANYEXT [[ICMP]](<2 x i1>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
entry:
%result = icmp samesign ult <2 x i32> %a, %b
@@ -23,11 +23,11 @@ define <2 x i1> @call_icmp_vector(<2 x i32> %a, <2 x i32> %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[ICMP]](<2 x s1>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(ult), [[COPY]](<2 x i32>), [[COPY1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i32>) = G_ANYEXT [[ICMP]](<2 x i1>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
entry:
%result = icmp ult <2 x i32> %a, %b
@@ -39,12 +39,12 @@ define i1 @call_icmp(i32 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[ICMP]](s1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ult), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[ICMP]](i1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = icmp ult i32 %a, 3
@@ -56,12 +56,12 @@ define i1 @call_icmp_samesign(i32 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: %2:_(s1) = samesign G_ICMP intpred(ult), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT %2(s1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = samesign G_ICMP intpred(ult), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[ICMP]](i1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = icmp samesign ult i32 %a, 3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
index d2989a852a032..b741093e5a7ef 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
@@ -9,31 +9,31 @@ define i32 @call_use_s128(i32 %p1, i128 %p2, i32 %p3, i32 %p4, i32 %p5, i128 %p6
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w4, $w5, $w6, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY1]](s64), [[COPY2]](s64)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w6
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY1]](i64), [[COPY2]](i64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w6
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.2, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.2, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s64) from %fixed-stack.1)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](s64), [[LOAD1]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i64) from %fixed-stack.1)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[LOAD]](i64), [[LOAD1]](i64)
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (s32) from %fixed-stack.0, align 16)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (i32) from %fixed-stack.0, align 16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV1]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[MV]](i128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[MV1]](i128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: BL @use_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
call void @use_s128(i128 %p2, i128 %p6)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
index c471ba0cabaad..1b36f217dbc9e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
@@ -4,12 +4,13 @@
define i32 @atomicrmw_volatile(ptr %ptr) {
; CHECK-LABEL: name: atomicrmw_volatile
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile load store monotonic (s32) on %ir.ptr)
- ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(i32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile load store monotonic (i32) on %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMICRMW_ADD]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%oldval = atomicrmw volatile add ptr %ptr, i32 1 monotonic
ret i32 %oldval
}
@@ -17,12 +18,13 @@ define i32 @atomicrmw_volatile(ptr %ptr) {
define i32 @atomicrmw_falkor(ptr %ptr) {
; CHECK-LABEL: name: atomicrmw_falkor
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: ("aarch64-strided-access" load store monotonic (s32) on %ir.ptr)
- ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(i32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: ("aarch64-strided-access" load store monotonic (i32) on %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMICRMW_ADD]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%oldval = atomicrmw add ptr %ptr, i32 1 monotonic, !falkor.strided.access !0
ret i32 %oldval
}
@@ -30,12 +32,13 @@ define i32 @atomicrmw_falkor(ptr %ptr) {
define i32 @atomicrmw_volatile_falkor(ptr %ptr) {
; CHECK-LABEL: name: atomicrmw_volatile_falkor
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile "aarch64-strided-access" load store monotonic (s32) on %ir.ptr)
- ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(i32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile "aarch64-strided-access" load store monotonic (i32) on %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMICRMW_ADD]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%oldval = atomicrmw volatile add ptr %ptr, i32 1 monotonic, !falkor.strided.access !0
ret i32 %oldval
}
@@ -43,13 +46,14 @@ define i32 @atomicrmw_volatile_falkor(ptr %ptr) {
define i32 @cmpxchg_volatile(ptr %addr) {
; CHECK-LABEL: name: cmpxchg_volatile
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile load store monotonic monotonic (s32) on %ir.addr)
- ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(i32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile load store monotonic monotonic (i32) on %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val_success = cmpxchg volatile ptr %addr, i32 0, i32 1 monotonic monotonic
%value_loaded = extractvalue { i32, i1 } %val_success, 0
ret i32 %value_loaded
@@ -58,13 +62,14 @@ define i32 @cmpxchg_volatile(ptr %addr) {
define i32 @cmpxchg_falkor(ptr %addr) {
; CHECK-LABEL: name: cmpxchg_falkor
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: ("aarch64-strided-access" load store monotonic monotonic (s32) on %ir.addr)
- ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(i32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: ("aarch64-strided-access" load store monotonic monotonic (i32) on %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val_success = cmpxchg ptr %addr, i32 0, i32 1 monotonic monotonic, !falkor.strided.access !0
%value_loaded = extractvalue { i32, i1 } %val_success, 0
ret i32 %value_loaded
@@ -73,13 +78,14 @@ define i32 @cmpxchg_falkor(ptr %addr) {
define i32 @cmpxchg_volatile_falkor(ptr %addr) {
; CHECK-LABEL: name: cmpxchg_volatile_falkor
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile "aarch64-strided-access" load store monotonic monotonic (s32) on %ir.addr)
- ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(i32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile "aarch64-strided-access" load store monotonic monotonic (i32) on %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val_success = cmpxchg volatile ptr %addr, i32 0, i32 1 monotonic monotonic, !falkor.strided.access !0
%value_loaded = extractvalue { i32, i1 } %val_success, 0
ret i32 %value_loaded
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
index f84f156d154a4..8f482dda4a491 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
@@ -23,8 +23,8 @@ define i32 @test_bitcast_invalid_vreg() {
%tmp15 = add i32 30, 30
; At this point we mapped 46 values. The 'i32 100' constant will grow the map.
-; CHECK: %46:_(s32) = G_CONSTANT i32 100
-; CHECK: $w0 = COPY %47(s32)
+; CHECK: %46:_(i32) = G_CONSTANT i32 100
+; CHECK: $w0 = COPY %47(i32)
%res = bitcast i32 100 to i32
ret i32 %res
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
index 30eca0d463eb2..8f5c41de13d3b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
@@ -5,28 +5,33 @@ declare i32 @bar(...)
define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x20000000), %bb.4(0x60000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.3
- ; CHECK: G_BR %bb.4
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x20000000), %bb.4(0x60000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
@@ -44,29 +49,34 @@ UnifiedReturnBlock:
define void @or_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_select
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x20000000), %bb.4(0x60000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[SELECT:%[0-9]+]]:_(s1) = G_SELECT [[ICMP1]](s1), [[C2]], [[ICMP]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.3
- ; CHECK: G_BR %bb.4
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x20000000), %bb.4(0x60000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i1) = G_SELECT [[ICMP1]](i1), [[C2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
@@ -84,28 +94,33 @@ UnifiedReturnBlock:
define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.4(0x60000000), %bb.2(0x20000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.4(0x60000000), %bb.2(0x20000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i1) = G_AND [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.4
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
@@ -123,29 +138,34 @@ UnifiedReturnBlock:
define void @and_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond_select
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.4(0x60000000), %bb.2(0x20000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[SELECT:%[0-9]+]]:_(s1) = G_SELECT [[ICMP1]](s1), [[ICMP]], [[C2]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.4(0x60000000), %bb.2(0x20000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i1) = G_SELECT [[ICMP1]](i1), [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.4
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
@@ -164,21 +184,24 @@ UnifiedReturnBlock:
define void @or_cond_same_values_cmp(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_same_values_cmp
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: G_BRCOND [[OR]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 5
%tmp3 = icmp slt i32 %X, 5
@@ -197,34 +220,41 @@ UnifiedReturnBlock:
define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_multiple_cases
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x10000000), %bb.5(0x70000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[OR]], [[ICMP2]]
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.5
- ; CHECK: bb.5.entry:
- ; CHECK: successors: %bb.3(0x12492492), %bb.4(0x6db6db6e)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP4]](s1), %bb.3
- ; CHECK: G_BR %bb.4
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
- ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP5]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x10000000), %bb.5(0x70000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY2]](i32), [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i1) = G_OR [[OR]], [[ICMP2]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x12492492), %bb.4(0x6db6db6e)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP4]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY2]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP5]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 5
%tmp3 = icmp slt i32 %X, 5
@@ -246,21 +276,24 @@ UnifiedReturnBlock:
define void @or_cond_ne_null(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_ne_null
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: G_BRCOND [[OR]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[COPY1]](i32), [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp ne i32 %X, 0
%tmp3 = icmp ne i32 %Y, 0
@@ -281,22 +314,25 @@ UnifiedReturnBlock:
define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: unpredictable
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: G_BRCOND [[OR]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
index 065a3d8e4dd25..c153d08a3ebdb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
@@ -4,12 +4,13 @@
define i16 @convert_to_fp16(float %src) {
; CHECK-LABEL: name: convert_to_fp16
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(i16) = G_FPTRUNC [[COPY]](f32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%cvt = call i16 @llvm.convert.to.fp16.f32(float %src)
ret i16 %cvt
}
@@ -17,12 +18,13 @@ define i16 @convert_to_fp16(float %src) {
define float @convert_from_fp16(i16 %src) {
; CHECK-LABEL: name: convert_from_fp16
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; CHECK: $s0 = COPY [[FPEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%cvt = call float @llvm.convert.from.fp16.f32(i16 %src)
ret float %cvt
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
index 4a3b85d9cec18..2edbb53991ac4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
@@ -16,15 +16,16 @@ define void @caller() sspreq {
; CHECK-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (s64) from %stack.0.StackGuardSlot)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (i64) from %stack.0.StackGuardSlot)
; CHECK-NEXT: [[LOAD_STACK_GUARD2:%[0-9]+]]:gpr64sp(s64) = LOAD_STACK_GUARD :: (dereferenceable invariant load (p0) from @__stack_chk_guard)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.entry:
; CHECK-NEXT: successors:
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL &__stack_chk_fail, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index 8d68f384db907..9235371a500bd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -12,16 +12,16 @@ define { ptr, i32 } @bar() personality ptr @__gxx_personality_v0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
@@ -32,15 +32,15 @@ define { ptr, i32 } @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
- ; CHECK-NEXT: $w1 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[PTRTOINT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: $x0 = COPY [[DEF]](p0)
- ; CHECK-NEXT: $w1 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
%res32 = invoke i32 @foo(i32 42) to label %continue unwind label %broken
@@ -77,7 +77,7 @@ define void @test_invoke_indirect(ptr %callee) personality ptr @__gxx_personalit
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
@@ -99,19 +99,19 @@ define void @test_invoke_varargs() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
- ; CHECK-NEXT: G_STORE [[ANYEXT]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 1)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[C2]](s32), [[PTR_ADD1]](p0) :: (store (s32) into stack + 8, align 1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[C1]](i32)
+ ; CHECK-NEXT: G_STORE [[ANYEXT]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack, align 1)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](i64)
+ ; CHECK-NEXT: G_STORE [[C2]](f32), [[PTR_ADD1]](p0) :: (store (f32) into stack + 8, align 1)
; CHECK-NEXT: $x0 = COPY [[C]](p0)
; CHECK-NEXT: BL @printf, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
@@ -125,7 +125,7 @@ define void @test_invoke_varargs() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
@@ -148,12 +148,12 @@ define i32 @test_lpad_phi() personality ptr @__gxx_personality_v0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 55
- ; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 55
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
@@ -166,18 +166,18 @@ define i32 @test_lpad_phi() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C1]](i32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV]](p0) :: (store (s32) into @global_var)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV]](p0) :: (store (i32) into @global_var)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C2]](s32), %bb.1, [[C3]](s32), %bb.2
- ; CHECK-NEXT: $w0 = COPY [[PHI1]](s32)
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(i32) = G_PHI [[C2]](i32), %bb.1, [[C3]](i32), %bb.2
+ ; CHECK-NEXT: $w0 = COPY [[PHI1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
store i32 42, ptr @global_var
invoke void @may_throw()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
index b5658155f468b..249bca91a3cb4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
@@ -5,11 +5,11 @@
define i32 @test_zext(i32 %a) {
; CHECK-LABEL: name: test_zext
- ; CHECK: %0:_(s32) = COPY $w0
- ; CHECK: %1:_(s8) = G_TRUNC %0(s32)
- ; CHECK: %2:_(s16) = G_ZEXT %1(s8)
- ; CHECK: %3:_(s32) = G_ZEXT %2(s16)
- ; CHECK: $w0 = COPY %3(s32)
+ ; CHECK: %0:_(i32) = COPY $w0
+ ; CHECK: %1:_(i8) = G_TRUNC %0(i32)
+ ; CHECK: %2:_(i16) = G_ZEXT %1(i8)
+ ; CHECK: %3:_(i32) = G_ZEXT %2(i16)
+ ; CHECK: $w0 = COPY %3(i32)
%tmp0 = trunc i32 %a to i8
%tmp1 = zext i8 %tmp0 to i16
%tmp2 = zext i16 %tmp1 to i32
@@ -18,11 +18,11 @@ define i32 @test_zext(i32 %a) {
define i32 @test_sext(i32 %a) {
; CHECK-LABEL: name: test_sext
- ; CHECK: %0:_(s32) = COPY $w0
- ; CHECK: %1:_(s8) = G_TRUNC %0(s32)
- ; CHECK: %2:_(s16) = G_SEXT %1(s8)
- ; CHECK: %3:_(s32) = G_SEXT %2(s16)
- ; CHECK: $w0 = COPY %3(s32)
+ ; CHECK: %0:_(i32) = COPY $w0
+ ; CHECK: %1:_(i8) = G_TRUNC %0(i32)
+ ; CHECK: %2:_(i16) = G_SEXT %1(i8)
+ ; CHECK: %3:_(i32) = G_SEXT %2(i16)
+ ; CHECK: $w0 = COPY %3(i32)
%tmp0 = trunc i32 %a to i8
%tmp1 = sext i8 %tmp0 to i16
%tmp2 = sext i16 %tmp1 to i32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
index c70b93e50ded8..a9301581e7694 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
@@ -4,15 +4,16 @@
define i16 @smul_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: smul_fix
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[SMULFIX:%[0-9]+]]:_(s16) = G_SMULFIX [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMULFIX]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SMULFIX:%[0-9]+]]:_(i16) = G_SMULFIX [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SMULFIX]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.smul.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -20,15 +21,16 @@ define i16 @smul_fix(i16 %arg0, i16 %arg1) {
define i16 @umul_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: umul_fix
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[UMULFIX:%[0-9]+]]:_(s16) = G_UMULFIX [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMULFIX]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[UMULFIX:%[0-9]+]]:_(i16) = G_UMULFIX [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UMULFIX]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.umul.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -36,15 +38,16 @@ define i16 @umul_fix(i16 %arg0, i16 %arg1) {
define i16 @smul_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: smul_fix_sat
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[SMULFIXSAT:%[0-9]+]]:_(s16) = G_SMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMULFIXSAT]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SMULFIXSAT:%[0-9]+]]:_(i16) = G_SMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SMULFIXSAT]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.smul.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -52,15 +55,16 @@ define i16 @smul_fix_sat(i16 %arg0, i16 %arg1) {
define i16 @umul_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: umul_fix_sat
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[UMULFIXSAT:%[0-9]+]]:_(s16) = G_UMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMULFIXSAT]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[UMULFIXSAT:%[0-9]+]]:_(i16) = G_UMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UMULFIXSAT]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.umul.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -68,15 +72,16 @@ define i16 @umul_fix_sat(i16 %arg0, i16 %arg1) {
define i16 @sdiv_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: sdiv_fix
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[SDIVFIX:%[0-9]+]]:_(s16) = G_SDIVFIX [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SDIVFIX]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SDIVFIX:%[0-9]+]]:_(i16) = G_SDIVFIX [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SDIVFIX]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.sdiv.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -84,15 +89,16 @@ define i16 @sdiv_fix(i16 %arg0, i16 %arg1) {
define i16 @udiv_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: udiv_fix
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[UDIVFIX:%[0-9]+]]:_(s16) = G_UDIVFIX [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UDIVFIX]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[UDIVFIX:%[0-9]+]]:_(i16) = G_UDIVFIX [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UDIVFIX]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.udiv.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -100,15 +106,16 @@ define i16 @udiv_fix(i16 %arg0, i16 %arg1) {
define i16 @sdiv_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: sdiv_fix_sat
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[SDIVFIXSAT:%[0-9]+]]:_(s16) = G_SDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SDIVFIXSAT]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SDIVFIXSAT:%[0-9]+]]:_(i16) = G_SDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SDIVFIXSAT]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.sdiv.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -116,15 +123,16 @@ define i16 @sdiv_fix_sat(i16 %arg0, i16 %arg1) {
define i16 @udiv_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: udiv_fix_sat
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[UDIVFIXSAT:%[0-9]+]]:_(s16) = G_UDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UDIVFIXSAT]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[UDIVFIXSAT:%[0-9]+]]:_(i16) = G_UDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UDIVFIXSAT]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.udiv.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
index 4e639974b66e0..d8e172d93513a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
@@ -4,12 +4,13 @@
define float @test_minnum(float %x, float %y) {
; CHECK-LABEL: name: test_minnum
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY [[FMINNUM]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(f32) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINNUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.minnum.f32(float %x, float %y)
ret float %val
}
@@ -17,12 +18,13 @@ define float @test_minnum(float %x, float %y) {
define float @test_minnum_nnan(float %x, float %y) {
; CHECK-LABEL: name: test_minnum_nnan
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: %2:_(s32) = nnan G_FMINNUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY %2(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(f32) = nnan G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINNUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call nnan float @llvm.minnum.f32(float %x, float %y)
ret float %val
}
@@ -30,12 +32,13 @@ define float @test_minnum_nnan(float %x, float %y) {
define float @test_maxnum(float %x, float %y) {
; CHECK-LABEL: name: test_maxnum
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY [[FMAXNUM]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(f32) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMAXNUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.maxnum.f32(float %x, float %y)
ret float %val
}
@@ -43,12 +46,13 @@ define float @test_maxnum(float %x, float %y) {
define float @test_minimum(float %x, float %y) {
; CHECK-LABEL: name: test_minimum
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: [[FMINIMUM:%[0-9]+]]:_(s32) = G_FMINIMUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY [[FMINIMUM]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINIMUM:%[0-9]+]]:_(f32) = G_FMINIMUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINIMUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.minimum.f32(float %x, float %y)
ret float %val
}
@@ -56,12 +60,13 @@ define float @test_minimum(float %x, float %y) {
define float @test_minimum_nnan(float %x, float %y) {
; CHECK-LABEL: name: test_minimum_nnan
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: %2:_(s32) = nnan G_FMINIMUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY %2(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINIMUM:%[0-9]+]]:_(f32) = nnan G_FMINIMUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINIMUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call nnan float @llvm.minimum.f32(float %x, float %y)
ret float %val
}
@@ -69,12 +74,13 @@ define float @test_minimum_nnan(float %x, float %y) {
define float @test_maximum(float %x, float %y) {
; CHECK-LABEL: name: test_maximum
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: [[FMAXIMUM:%[0-9]+]]:_(s32) = G_FMAXIMUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY [[FMAXIMUM]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(f32) = G_FMAXIMUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMAXIMUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.maximum.f32(float %x, float %y)
ret float %val
}
@@ -84,10 +90,10 @@ define float @test_minimumnum(float %x, float %y) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(s32) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FMINIMUMNUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(f32) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINIMUMNUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %val
@@ -98,10 +104,10 @@ define float @test_minimumnum_nnan(float %x, float %y) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(s32) = nnan G_FMINIMUMNUM [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FMINIMUMNUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(f32) = nnan G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINIMUMNUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call nnan float @llvm.minimumnum.f32(float %x, float %y)
ret float %val
@@ -112,10 +118,10 @@ define float @test_maximumnum(float %x, float %y) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(s32) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FMAXIMUMNUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(f32) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMAXIMUMNUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %val
@@ -126,10 +132,10 @@ define float @test_maximumnum_nnan(float %x, float %y) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(s32) = nnan G_FMAXIMUMNUM [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FMAXIMUMNUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(f32) = nnan G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMAXIMUMNUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call nnan float @llvm.maximumnum.f32(float %x, float %y)
ret float %val
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
index 9a8e5529f0a1e..56354d5ddfd33 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
@@ -11,8 +11,8 @@ declare void @llvm.reset.fpmode()
define i64 @func_get_fpenv() #0 {
; CHECK-LABEL: name: func_get_fpenv
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[GET_FPENV:%[0-9]+]]:_(s64) = G_GET_FPENV
- ; CHECK-NEXT: $x0 = COPY [[GET_FPENV]](s64)
+ ; CHECK-NEXT: [[GET_FPENV:%[0-9]+]]:_(i64) = G_GET_FPENV
+ ; CHECK-NEXT: $x0 = COPY [[GET_FPENV]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%fpenv = call i64 @llvm.get.fpenv.i64()
@@ -24,8 +24,8 @@ define void @func_set_fpenv(i64 %fpenv) #0 {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: G_SET_FPENV [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: G_SET_FPENV [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.set.fpenv.i64(i64 %fpenv)
@@ -45,8 +45,8 @@ entry:
define i32 @func_get_fpmode() #0 {
; CHECK-LABEL: name: func_get_fpmode
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[GET_FPMODE:%[0-9]+]]:_(s32) = G_GET_FPMODE
- ; CHECK-NEXT: $w0 = COPY [[GET_FPMODE]](s32)
+ ; CHECK-NEXT: [[GET_FPMODE:%[0-9]+]]:_(i32) = G_GET_FPMODE
+ ; CHECK-NEXT: $w0 = COPY [[GET_FPMODE]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%fpmode = call i32 @llvm.get.fpmode.i32()
@@ -58,8 +58,8 @@ define void @func_set_fpmode(i32 %fpmode) #0 {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: G_SET_FPMODE [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: G_SET_FPMODE [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.set.fpmode.i32(i32 %fpmode)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
index b7cf9b31e345a..24e85f566e0c5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
@@ -7,20 +7,20 @@ define i32 @gep_nusw_nuw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nuw nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nuw nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -37,20 +37,20 @@ define i32 @gep_nuw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nuw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nuw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -67,20 +67,20 @@ define i32 @gep_nusw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -97,20 +97,20 @@ define i32 @gep_none(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -127,20 +127,20 @@ define i32 @gep_nusw_negative(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -157,15 +157,15 @@ define ptr @gep_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -179,15 +179,15 @@ define ptr @gep_nuw_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nuw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nuw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -201,15 +201,15 @@ define ptr @gep_nusw_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -223,15 +223,15 @@ define ptr @gep_inbounds_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -245,15 +245,15 @@ define ptr @gep_nuw_nusw_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nuw nsw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nuw nsw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -267,15 +267,15 @@ define ptr @gep_nuw_inbounds_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nuw nsw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nuw nsw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
index 1602480ea3e0d..1be3988d2cfd4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
@@ -14,26 +14,26 @@ define i32 @test(i32 %a, i1 %c) {
; TRANSLATED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; TRANSLATED-NEXT: liveins: $w0, $w1
; TRANSLATED-NEXT: {{ $}}
- ; TRANSLATED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; TRANSLATED-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; TRANSLATED-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; TRANSLATED-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC]], 1
- ; TRANSLATED-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s8)
- ; TRANSLATED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 100000
- ; TRANSLATED-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; TRANSLATED-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[C]]
- ; TRANSLATED-NEXT: G_BRCOND [[TRUNC1]](s1), %bb.3
+ ; TRANSLATED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; TRANSLATED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; TRANSLATED-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
+ ; TRANSLATED-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC]], 1
+ ; TRANSLATED-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i8)
+ ; TRANSLATED-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 100000
+ ; TRANSLATED-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; TRANSLATED-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(i32) = G_CONSTANT_FOLD_BARRIER [[C]]
+ ; TRANSLATED-NEXT: G_BRCOND [[TRUNC1]](i1), %bb.3
; TRANSLATED-NEXT: G_BR %bb.2
; TRANSLATED-NEXT: {{ $}}
; TRANSLATED-NEXT: bb.2.common.ret:
- ; TRANSLATED-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.3, [[C1]](s32), %bb.1
- ; TRANSLATED-NEXT: $w0 = COPY [[PHI]](s32)
+ ; TRANSLATED-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI %7(i32), %bb.3, [[C1]](i32), %bb.1
+ ; TRANSLATED-NEXT: $w0 = COPY [[PHI]](i32)
; TRANSLATED-NEXT: RET_ReallyLR implicit $w0
; TRANSLATED-NEXT: {{ $}}
; TRANSLATED-NEXT: bb.3.cont:
; TRANSLATED-NEXT: successors: %bb.2(0x80000000)
; TRANSLATED-NEXT: {{ $}}
- ; TRANSLATED-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
+ ; TRANSLATED-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
; TRANSLATED-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; TRANSLATED-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; TRANSLATED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -44,25 +44,25 @@ define i32 @test(i32 %a, i1 %c) {
; PRESELECTION-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; PRESELECTION-NEXT: liveins: $w0, $w1
; PRESELECTION-NEXT: {{ $}}
- ; PRESELECTION-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; PRESELECTION-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
- ; PRESELECTION-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 100000
- ; PRESELECTION-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:gpr(s32) = G_CONSTANT_FOLD_BARRIER [[C]]
- ; PRESELECTION-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; PRESELECTION-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; PRESELECTION-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[COPY1]], [[C2]]
- ; PRESELECTION-NEXT: G_BRCOND [[AND]](s32), %bb.3
+ ; PRESELECTION-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY $w0
+ ; PRESELECTION-NEXT: [[COPY1:%[0-9]+]]:gpr(i32) = COPY $w1
+ ; PRESELECTION-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 100000
+ ; PRESELECTION-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:gpr(i32) = G_CONSTANT_FOLD_BARRIER [[C]]
+ ; PRESELECTION-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; PRESELECTION-NEXT: [[C2:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; PRESELECTION-NEXT: [[AND:%[0-9]+]]:gpr(i32) = G_AND [[COPY1]], [[C2]]
+ ; PRESELECTION-NEXT: G_BRCOND [[AND]](i32), %bb.3
; PRESELECTION-NEXT: G_BR %bb.2
; PRESELECTION-NEXT: {{ $}}
; PRESELECTION-NEXT: bb.2.common.ret:
- ; PRESELECTION-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI %7(s32), %bb.3, [[C1]](s32), %bb.1
- ; PRESELECTION-NEXT: $w0 = COPY [[PHI]](s32)
+ ; PRESELECTION-NEXT: [[PHI:%[0-9]+]]:gpr(i32) = G_PHI %7(i32), %bb.3, [[C1]](i32), %bb.1
+ ; PRESELECTION-NEXT: $w0 = COPY [[PHI]](i32)
; PRESELECTION-NEXT: RET_ReallyLR implicit $w0
; PRESELECTION-NEXT: {{ $}}
; PRESELECTION-NEXT: bb.3.cont:
; PRESELECTION-NEXT: successors: %bb.2(0x80000000)
; PRESELECTION-NEXT: {{ $}}
- ; PRESELECTION-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
+ ; PRESELECTION-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
; PRESELECTION-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; PRESELECTION-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; PRESELECTION-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
index 2a490bc7d3d1c..18574893ce133 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
@@ -26,11 +26,11 @@ define void @asm_simple_register_clobber() {
define i64 @asm_register_early_clobber() {
; CHECK-LABEL: name: asm_register_early_clobber
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %0, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %1, !0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY %0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $x0 = COPY [[ADD]](s64)
+ ; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 3866635 /* regdef-ec:GPR64common */, def early-clobber %0, 3866635 /* regdef-ec:GPR64common */, def early-clobber %1, !0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY %0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY %1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x0 = COPY [[ADD]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
call { i64, i64 } asm sideeffect "mov $0, 7; mov $1, 7", "=&r,=&r"(), !srcloc !0
%asmresult = extractvalue { i64, i64 } %1, 0
@@ -43,8 +43,8 @@ define i32 @test_specific_register_output() nounwind ssp {
; CHECK-LABEL: name: test_specific_register_output
; CHECK: bb.1.entry:
; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $w0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i32 asm "mov ${0:w}, 7", "={w0}"() nounwind
@@ -54,9 +54,9 @@ entry:
define i32 @test_single_register_output() nounwind ssp {
; CHECK-LABEL: name: test_single_register_output
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY %0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind
@@ -66,9 +66,9 @@ entry:
define i64 @test_single_register_output_s64() nounwind ssp {
; CHECK-LABEL: name: test_single_register_output_s64
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY %0
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, 3866634 /* regdef:GPR64common */, def %0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY %0
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = tail call i64 asm "mov $0, 7", "=r"() nounwind
@@ -79,11 +79,11 @@ entry:
define float @test_multiple_register_outputs_same() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_same
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:GPR32common */, def %1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
+ ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2818058 /* regdef:GPR32common */, def %1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY %0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY %1
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()
%asmresult = extractvalue { float, float } %1, 0
@@ -96,10 +96,10 @@ define float @test_multiple_register_outputs_same() #0 {
define double @test_multiple_register_outputs_mixed() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_mixed
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %1
- ; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0, 3670026 /* regdef:FPR64 */, def %1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY %0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY %1
+ ; CHECK-NEXT: $d0 = COPY [[COPY1]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1 = call { float, double } asm "mov $0, #0; mov $1, #0", "=r,=w"()
%asmresult = extractvalue { float, double } %1, 1
@@ -111,8 +111,8 @@ define i32 @test_specific_register_output_trunc() nounwind ssp {
; CHECK: bb.1.entry:
; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $x0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i32 asm "mov ${0:w}, 7", "={x0}"() nounwind
@@ -125,11 +125,11 @@ define zeroext i8 @test_register_output_trunc(ptr %src) nounwind {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1
+ ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i8 asm "mov ${0:w}, 32", "=r"() nounwind
@@ -139,11 +139,11 @@ entry:
define float @test_vector_output() nounwind {
; CHECK-LABEL: name: test_vector_output
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: INLINEASM &"fmov ${0}.2s, #1.0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $d14
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d14
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: $s0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d14
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f32>), [[C]](i64)
+ ; CHECK-NEXT: $s0 = COPY [[EVEC]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%1 = tail call <2 x float> asm sideeffect "fmov ${0}.2s, #1.0", "={v14}"() nounwind
%2 = extractelement <2 x float> %1, i32 0
@@ -153,9 +153,9 @@ define float @test_vector_output() nounwind {
define void @test_input_register_imm() {
; CHECK-LABEL: name: test_input_register_imm
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64)
- ; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](i64)
+ ; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 3866633 /* reguse:GPR64common */, [[COPY]]
; CHECK-NEXT: RET_ReallyLR
call void asm sideeffect "mov x0, $0", "r"(i64 42)
ret void
@@ -165,9 +165,9 @@ define void @test_input_register_imm() {
define i32 @test_boolean_imm_ext() {
; CHECK-LABEL: name: test_boolean_imm_ext
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: INLINEASM &"#TEST 42 + ${0:c} - .\0A\09", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 1
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i"(i1 true)
@@ -209,11 +209,11 @@ define zeroext i8 @test_input_register(ptr %src) nounwind {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
- ; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, {{[0-9]+}} /* reguse:GPR64common */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %1, 3866633 /* reguse:GPR64common */, [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY2]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(ptr %src) nounwind
@@ -226,9 +226,9 @@ define i32 @test_memory_constraint(ptr %a) nounwind {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
- ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 2818058 /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY %1
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1 = tail call i32 asm "ldr $0, $1", "=r,*m"(ptr elementtype(i32) %a)
ret i32 %1
@@ -237,14 +237,14 @@ define i32 @test_memory_constraint(ptr %a) nounwind {
define i16 @test_anyext_input() {
; CHECK-LABEL: name: test_anyext_input
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* reguse:GPR32common */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2818057 /* reguse:GPR32common */, [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1 = call i16 asm sideeffect "", "=r,r"(i16 1)
ret i16 %1
@@ -253,14 +253,14 @@ define i16 @test_anyext_input() {
define i16 @test_anyext_input_with_matching_constraint() {
; CHECK-LABEL: name: test_anyext_input_with_matching_constraint
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1 = call i16 asm sideeffect "", "=r,0"(i16 1)
ret i16 %1
@@ -269,10 +269,10 @@ define i16 @test_anyext_input_with_matching_constraint() {
define i64 @test_input_with_matching_constraint_to_physical_register() {
; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[C]](tied-def 3)(s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[C]](tied-def 3)(i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%1 = tail call i64 asm "", "={x2},0"(i64 0)
ret i64 %1
@@ -283,13 +283,13 @@ define void @test_indirectify_i32_value(i32 %x, i32 %y) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[COPY]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: G_STORE [[COPY]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %stack.0)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
- ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %stack.1)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
+ ; CHECK-NEXT: G_STORE [[COPY1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %stack.1)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 %x, i32 %y)
@@ -299,13 +299,13 @@ entry:
define void @test_indirectify_i32_constant() {
; CHECK-LABEL: name: test_indirectify_i32_constant
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %stack.0)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
- ; CHECK-NEXT: G_STORE [[C1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %stack.1)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
+ ; CHECK-NEXT: G_STORE [[C1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %stack.1)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 42, i32 0)
@@ -317,11 +317,11 @@ define void @test_indirectify_i16_value(i16 %val) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[FRAME_INDEX]](p0) :: (store (s16) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i16), [[FRAME_INDEX]](p0) :: (store (i16) into %stack.0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i16 %val)
@@ -331,10 +331,10 @@ entry:
define void @test_indirectify_i16_constant() {
; CHECK-LABEL: name: test_indirectify_i16_constant
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[C]](s16), [[FRAME_INDEX]](p0) :: (store (s16) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: G_STORE [[C]](i16), [[FRAME_INDEX]](p0) :: (store (i16) into %stack.0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i16 42)
@@ -346,10 +346,10 @@ define void @test_indirectify_i64_value(i64 %val) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[COPY]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: G_STORE [[COPY]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %stack.0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i64 %val)
@@ -359,10 +359,10 @@ entry:
define void @test_indirectify_i64_constant() {
; CHECK-LABEL: name: test_indirectify_i64_constant
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %stack.0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i64 42)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
index e955b52e1643b..52f6d90e2c72b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
@@ -7,8 +7,8 @@ define i32 @load_invariant(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (invariant load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
@@ -20,8 +20,8 @@ define i32 @load_volatile_invariant(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile invariant load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (volatile invariant load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load volatile i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
@@ -33,8 +33,8 @@ define i32 @load_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4
ret i32 %load
@@ -46,8 +46,8 @@ define i32 @load_dereferenceable_invariant(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (invariant load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
@@ -59,8 +59,8 @@ define i32 @load_nontemporal(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (non-temporal load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (non-temporal load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !nontemporal !0
ret i32 %load
@@ -72,8 +72,8 @@ define i32 @load_falkor_strided_access(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !falkor.strided.access !0
ret i32 %load
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
index 91f4a480ccef2..e58874a0b2730 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
@@ -6,12 +6,12 @@ define void @local_escape() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape$frame_escape_1>, %stack.1.b
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape$frame_escape_0>, %stack.0.a
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.b
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.a)
- ; CHECK-NEXT: G_STORE [[C1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.b)
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %ir.a)
+ ; CHECK-NEXT: G_STORE [[C1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %ir.b)
; CHECK-NEXT: RET_ReallyLR
%a = alloca i32
%b = alloca i32, i32 2
@@ -27,12 +27,12 @@ define void @local_escape_insert_point() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape_insert_point$frame_escape_2>, %stack.1.b
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape_insert_point$frame_escape_0>, %stack.0.a
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.b
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.a)
- ; CHECK-NEXT: G_STORE [[C1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.b)
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %ir.a)
+ ; CHECK-NEXT: G_STORE [[C1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %ir.b)
; CHECK-NEXT: RET_ReallyLR
%a = alloca i32
%b = alloca i32, i32 2
@@ -49,9 +49,9 @@ define void @local_escape_strip_ptr_cast() {
; CHECK-LABEL: name: local_escape_strip_ptr_cast
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape_strip_ptr_cast$frame_escape_0>, %stack.0.a
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.a)
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %ir.a)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
index 8ff8349d15916..2e4d020cc495c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
@@ -1,8 +1,9 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
; CHECK-LABEL: name: store_max_address_space
; CHECK: %0:_(p16777215) = COPY $x0
-; CHECK: G_STORE %1(s32), %0(p16777215) :: (store (s32) into %ir.ptr, addrspace 16777215)
+; CHECK: G_STORE %1(i32), %0(p16777215) :: (store (i32) into %ir.ptr, addrspace 16777215)
define void @store_max_address_space(ptr addrspace(16777215) %ptr) {
store i32 0, ptr addrspace(16777215) %ptr
ret void
@@ -10,8 +11,8 @@ define void @store_max_address_space(ptr addrspace(16777215) %ptr) {
; CHECK-LABEL: name: store_max_address_space_vector
; CHECK: %0:_(<2 x p16777215>) = COPY $q0
-; CHECK: %1:_(p16777215) = G_EXTRACT_VECTOR_ELT %0(<2 x p16777215>), %2(s64)
-; CHECK: %1(p16777215) :: (store (s32) into %ir.elt0, addrspace 16777215)
+; CHECK: %1:_(p16777215) = G_EXTRACT_VECTOR_ELT %0(<2 x p16777215>), %2(i64)
+; CHECK: %1(p16777215) :: (store (i32) into %ir.elt0, addrspace 16777215)
define void @store_max_address_space_vector(<2 x ptr addrspace(16777215)> %vptr) {
%elt0 = extractelement <2 x ptr addrspace(16777215)> %vptr, i32 0
store i32 0, ptr addrspace(16777215) %elt0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
index fd12932cfd536..1d4f53d2ed4dd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
@@ -4,13 +4,14 @@
define void @copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: copy
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
@@ -19,13 +20,14 @@ entry:
define void @inline_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: inline_copy
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
@@ -34,13 +36,14 @@ entry:
define void @copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: copy_volatile
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 0 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
@@ -49,13 +52,14 @@ entry:
define void @inline_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: inline_copy_volatile
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
@@ -64,13 +68,14 @@ entry:
define void @tail_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_copy
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
@@ -79,13 +84,14 @@ entry:
define void @tail_inline_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_inline_copy
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
tail call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
@@ -94,13 +100,14 @@ entry:
define void @tail_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_copy_volatile
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 1 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
@@ -109,13 +116,14 @@ entry:
define void @tail_inline_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_inline_copy_volatile
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
tail call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
index 32c742316b872..af07caa67539d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
@@ -6,10 +6,10 @@ define i32 @call_nneg(i16 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: %2:_(s32) = nneg G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY %2(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = nneg G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = zext nneg i16 %a to i32
@@ -21,10 +21,10 @@ define i32 @call_not_nneg(i16 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = zext i16 %a to i32
@@ -36,10 +36,10 @@ define i32 @call_disjoint(i32 %a, i32 %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: %2:_(s32) = disjoint G_OR [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $w0 = COPY %2(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = or disjoint i32 %a, %b
@@ -51,10 +51,10 @@ define i32 @call_add(i32 %a, i32 %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = nsw G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = add nsw i32 %a, %b
@@ -66,10 +66,10 @@ define i32 @call_not_disjoint(i32 %a, i32 %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = or i32 %a, %b
@@ -81,10 +81,10 @@ define <2 x i64> @call_not_disjoint_vector(<2 x i64> %a, <2 x i64> %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%result = or <2 x i64> %a, %b
@@ -96,10 +96,10 @@ define <2 x i64> @call_disjoint_vector(<2 x i64> %a, <2 x i64> %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: %2:_(<2 x s64>) = disjoint G_OR [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY %2(<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = disjoint G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%result = or disjoint <2 x i64> %a, %b
@@ -111,9 +111,9 @@ define <2 x i64> @call_nneg_vector(<2 x i32> %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %1:_(<2 x s64>) = nneg G_ZEXT [[COPY]](<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY %1(<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = nneg G_ZEXT [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%result = zext nneg <2 x i32> %a to <2 x i64>
@@ -125,9 +125,9 @@ define <2 x i64> @call_not_nneg_vector(<2 x i32> %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%result = zext <2 x i32> %a to <2 x i64>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
index 4ab347c37f0d7..3ab10edc726ff 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
@@ -6,9 +6,9 @@ define i64 @expect_i64(i64 %arg0) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: $x0 = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[COPY]](i64)
+ ; CHECK-NEXT: $x0 = COPY [[COPY1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%expval = call i64 @llvm.expect.i64(i64 %arg0, i64 1)
ret i64 %expval
@@ -19,9 +19,9 @@ define i64 @expect_with_probability_i64(i64 %arg0) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: $x0 = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[COPY]](i64)
+ ; CHECK-NEXT: $x0 = COPY [[COPY1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%expval = call i64 @llvm.expect.with.probability.i64(i64 %arg0, i64 1, double 0.5)
ret i64 %expval
@@ -35,7 +35,7 @@ define ptr @ptr_annotate(ptr %arg0, ptr %arg1, ptr %arg2, i32 %arg3) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY4]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -51,9 +51,9 @@ define i32 @annotation(i32 %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%call = call i32 @llvm.annotation.i32(i32 %a, ptr @.str, ptr @.str1, i32 2)
ret i32 %call
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
index 78b0c720d51a3..07d406726e253 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
@@ -13,10 +13,10 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_idx(<1 x ptr> %vec) {
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[C]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $d0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -26,8 +26,8 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_idx(<1 x ptr> %vec) {
; CHECK-CI-NEXT: liveins: $d0
; CHECK-CI-NEXT: {{ $}}
; CHECK-CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $d0
- ; CHECK-CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-CI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-CI-NEXT: $d0 = COPY [[PTR_ADD]](p0)
; CHECK-CI-NEXT: RET_ReallyLR implicit $d0
%ptr_add = getelementptr i8, <1 x ptr> %vec, <1 x i32> <i32 1>
@@ -43,10 +43,10 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_ptr(ptr %vec) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[C]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $d0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -56,8 +56,8 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_ptr(ptr %vec) {
; CHECK-CI-NEXT: liveins: $x0
; CHECK-CI-NEXT: {{ $}}
; CHECK-CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-CI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-CI-NEXT: $d0 = COPY [[PTR_ADD]](p0)
; CHECK-CI-NEXT: RET_ReallyLR implicit $d0
%ptr_add = getelementptr i8, ptr %vec, <1 x i32> <i32 1>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
index c791e35946f72..d7d5bdf6d1c22 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
@@ -6,11 +6,11 @@ define float @fadd_seq(float %start, <4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q1, $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_SEQ_FADD:%[0-9]+]]:_(s32) = G_VECREDUCE_SEQ_FADD [[COPY]](s32), [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_SEQ_FADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_SEQ_FADD:%[0-9]+]]:_(f32) = G_VECREDUCE_SEQ_FADD [[COPY]](f32), [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_SEQ_FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %vec)
ret float %res
@@ -21,11 +21,12 @@ define float @fadd_seq_scalar(float %start, <1 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d1, $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[UV]]
- ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[UV]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fadd.v1f32(float %start, <1 x float> %vec)
ret float %res
@@ -36,12 +37,12 @@ define float @fadd_fast(float %start, <4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q1, $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = reassoc G_VECREDUCE_FADD [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = reassoc G_FADD [[COPY]], [[VECREDUCE_FADD]]
- ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FADD:%[0-9]+]]:_(f32) = reassoc G_VECREDUCE_FADD [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = reassoc G_FADD [[COPY]], [[VECREDUCE_FADD]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %vec)
ret float %res
@@ -52,12 +53,14 @@ define double @fmul_seq(double %start, <4 x double> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0, $q1, $q2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_SEQ_FMUL:%[0-9]+]]:_(s64) = G_VECREDUCE_SEQ_FMUL [[COPY]](s64), [[CONCAT_VECTORS]](<4 x s64>)
- ; CHECK-NEXT: $d0 = COPY [[VECREDUCE_SEQ_FMUL]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f64>) = G_CONCAT_VECTORS [[BITCAST]](<2 x f64>), [[BITCAST1]](<2 x f64>)
+ ; CHECK-NEXT: [[VECREDUCE_SEQ_FMUL:%[0-9]+]]:_(f64) = G_VECREDUCE_SEQ_FMUL [[COPY]](f64), [[CONCAT_VECTORS]](<4 x f64>)
+ ; CHECK-NEXT: $d0 = COPY [[VECREDUCE_SEQ_FMUL]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%res = call double @llvm.vector.reduce.fmul.v4f64(double %start, <4 x double> %vec)
ret double %res
@@ -68,10 +71,10 @@ define double @fmul_seq_scalar(double %start, <1 x double> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[FMUL]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $d1
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[FMUL]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%res = call double @llvm.vector.reduce.fmul.v1f64(double %start, <1 x double> %vec)
ret double %res
@@ -82,13 +85,15 @@ define double @fmul_fast(double %start, <4 x double> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0, $q1, $q2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMUL:%[0-9]+]]:_(s64) = reassoc G_VECREDUCE_FMUL [[CONCAT_VECTORS]](<4 x s64>)
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = reassoc G_FMUL [[COPY]], [[VECREDUCE_FMUL]]
- ; CHECK-NEXT: $d0 = COPY [[FMUL]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f64>) = G_CONCAT_VECTORS [[BITCAST]](<2 x f64>), [[BITCAST1]](<2 x f64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMUL:%[0-9]+]]:_(f64) = reassoc G_VECREDUCE_FMUL [[CONCAT_VECTORS]](<4 x f64>)
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = reassoc G_FMUL [[COPY]], [[VECREDUCE_FMUL]]
+ ; CHECK-NEXT: $d0 = COPY [[FMUL]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%res = call reassoc double @llvm.vector.reduce.fmul.v4f64(double %start, <4 x double> %vec)
ret double %res
@@ -99,10 +104,10 @@ define float @fmax(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAX]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(f32) = G_VECREDUCE_FMAX [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAX]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %vec)
ret float %res
@@ -113,10 +118,10 @@ define float @fmin(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMIN [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(f32) = G_VECREDUCE_FMIN [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %vec)
ret float %res
@@ -127,10 +132,10 @@ define float @fmin_nnan(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMIN [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(f32) = nnan G_VECREDUCE_FMIN [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %vec)
ret float %res
@@ -141,10 +146,10 @@ define float @fmaximum(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAXIMUM [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAXIMUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(f32) = G_VECREDUCE_FMAXIMUM [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAXIMUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %vec)
ret float %res
@@ -155,10 +160,10 @@ define float @fminimum(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(f32) = G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %vec)
ret float %res
@@ -169,10 +174,10 @@ define float @fminimum_nnan(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(f32) = nnan G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %vec)
ret float %res
@@ -183,9 +188,9 @@ define i32 @add(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(i32) = G_VECREDUCE_ADD [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -196,9 +201,9 @@ define i32 @mul(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_MUL:%[0-9]+]]:_(s32) = G_VECREDUCE_MUL [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_MUL]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_MUL:%[0-9]+]]:_(i32) = G_VECREDUCE_MUL [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_MUL]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -209,9 +214,9 @@ define i32 @and(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_AND:%[0-9]+]]:_(s32) = G_VECREDUCE_AND [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_AND]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_AND:%[0-9]+]]:_(i32) = G_VECREDUCE_AND [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_AND]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -222,9 +227,9 @@ define i32 @or(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_OR:%[0-9]+]]:_(s32) = G_VECREDUCE_OR [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_OR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_OR:%[0-9]+]]:_(i32) = G_VECREDUCE_OR [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -235,9 +240,9 @@ define i32 @xor(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_XOR:%[0-9]+]]:_(s32) = G_VECREDUCE_XOR [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_XOR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_XOR:%[0-9]+]]:_(i32) = G_VECREDUCE_XOR [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_XOR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -248,9 +253,9 @@ define i32 @smax(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_SMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_SMAX [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMAX]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_SMAX:%[0-9]+]]:_(i32) = G_VECREDUCE_SMAX [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMAX]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -261,9 +266,9 @@ define i32 @smin(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_SMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_SMIN [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMIN]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_SMIN:%[0-9]+]]:_(i32) = G_VECREDUCE_SMIN [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMIN]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -274,9 +279,9 @@ define i32 @umax(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_UMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_UMAX [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMAX]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_UMAX:%[0-9]+]]:_(i32) = G_VECREDUCE_UMAX [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMAX]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -287,9 +292,9 @@ define i32 @umin(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_UMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_UMIN [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMIN]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_UMIN:%[0-9]+]]:_(i32) = G_VECREDUCE_UMIN [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMIN]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)
ret i32 %res
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
index 69cd6ce87b5c6..471fb5ad0017f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
@@ -6,10 +6,10 @@ define { half, half } @test_sincos_f16(half %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $h0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s16), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $h0 = COPY [[FSINCOS]](s16)
- ; CHECK-NEXT: $h1 = COPY [[FSINCOS1]](s16)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f16) = COPY $h0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f16), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $h0 = COPY [[FSINCOS]](f16)
+ ; CHECK-NEXT: $h1 = COPY [[FSINCOS1]](f16)
; CHECK-NEXT: RET_ReallyLR implicit $h0, implicit $h1
%result = call { half, half } @llvm.sincos.f16(half %a)
ret { half, half } %result
@@ -20,16 +20,16 @@ define { <2 x half>, <2 x half> } @test_sincos_v2f16(<2 x half> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x s16>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[UV]]
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[FSINCOS]](<2 x s16>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV2]](s16), [[UV3]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[FSINCOS1]](<2 x s16>)
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV4]](s16), [[UV5]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
- ; CHECK-NEXT: $d1 = COPY [[BUILD_VECTOR1]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x f16>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[UV]]
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[FSINCOS]](<2 x f16>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV2]](f16), [[UV3]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(f16), [[UV5:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[FSINCOS1]](<2 x f16>)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV4]](f16), [[UV5]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x f16>)
+ ; CHECK-NEXT: $d1 = COPY [[BUILD_VECTOR1]](<4 x f16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%result = call { <2 x half>, <2 x half> } @llvm.sincos.v2f16(<2 x half> %a)
ret { <2 x half>, <2 x half> } %result
@@ -40,10 +40,10 @@ define { float, float } @test_sincos_f32(float %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s32), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $s0 = COPY [[FSINCOS]](s32)
- ; CHECK-NEXT: $s1 = COPY [[FSINCOS1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f32), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $s0 = COPY [[FSINCOS]](f32)
+ ; CHECK-NEXT: $s1 = COPY [[FSINCOS1]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1
%result = call { float, float } @llvm.sincos.f32(float %a)
ret { float, float } %result
@@ -54,10 +54,11 @@ define { <2 x float>, <2 x float> } @test_sincos_v2f32(<2 x float> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x s32>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $d0 = COPY [[FSINCOS]](<2 x s32>)
- ; CHECK-NEXT: $d1 = COPY [[FSINCOS1]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x f32>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[BITCAST]]
+ ; CHECK-NEXT: $d0 = COPY [[FSINCOS]](<2 x f32>)
+ ; CHECK-NEXT: $d1 = COPY [[FSINCOS1]](<2 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%result = call { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float> %a)
ret { <2 x float>, <2 x float> } %result
@@ -68,10 +69,10 @@ define { double, double } @test_sincos_f64(double %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s64), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $d0 = COPY [[FSINCOS]](s64)
- ; CHECK-NEXT: $d1 = COPY [[FSINCOS1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f64), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $d0 = COPY [[FSINCOS]](f64)
+ ; CHECK-NEXT: $d1 = COPY [[FSINCOS1]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%result = call { double, double } @llvm.sincos.f64(double %a)
ret { double, double } %result
@@ -82,10 +83,11 @@ define { <2 x double>, <2 x double> } @test_sincos_v2f64(<2 x double> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x s64>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $q0 = COPY [[FSINCOS]](<2 x s64>)
- ; CHECK-NEXT: $q1 = COPY [[FSINCOS1]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x f64>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[BITCAST]]
+ ; CHECK-NEXT: $q0 = COPY [[FSINCOS]](<2 x f64>)
+ ; CHECK-NEXT: $q1 = COPY [[FSINCOS1]](<2 x f64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%result = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> %a)
ret { <2 x double>, <2 x double> } %result
@@ -96,10 +98,10 @@ define { fp128, fp128 } @test_sincos_f128(fp128 %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s128), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $q0 = COPY [[FSINCOS]](s128)
- ; CHECK-NEXT: $q1 = COPY [[FSINCOS1]](s128)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f128) = COPY $q0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f128), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $q0 = COPY [[FSINCOS]](f128)
+ ; CHECK-NEXT: $q1 = COPY [[FSINCOS1]](f128)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%result = call { fp128, fp128 } @llvm.sincos.f16(fp128 %a)
ret { fp128, fp128 } %result
@@ -110,10 +112,10 @@ define { float, float } @test_sincos_f32_afn(float %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s32), [[FSINCOS1:%[0-9]+]]:_ = afn G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $s0 = COPY [[FSINCOS]](s32)
- ; CHECK-NEXT: $s1 = COPY [[FSINCOS1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f32), [[FSINCOS1:%[0-9]+]]:_ = afn G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $s0 = COPY [[FSINCOS]](f32)
+ ; CHECK-NEXT: $s1 = COPY [[FSINCOS1]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1
%result = call afn { float, float } @llvm.sincos.f32(float %a)
ret { float, float } %result
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
index ef74cdb4aada3..749c221651f81 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
@@ -7,13 +7,14 @@ target triple = "aarch64-apple-ios"
define hidden fastcc <4 x float> @foo(<4 x i64> %arg) unnamed_addr #0 {
; CHECK-LABEL: name: foo
; CHECK: bb.1.bb:
- ; CHECK: liveins: $q0, $q1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)
- ; CHECK: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[CONCAT_VECTORS]](<4 x s64>)
- ; CHECK: $q0 = COPY [[UITOFP]](<4 x s32>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x i64>) = G_CONCAT_VECTORS [[COPY]](<2 x i64>), [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<4 x f32>) = G_UITOFP [[CONCAT_VECTORS]](<4 x i64>)
+ ; CHECK-NEXT: $q0 = COPY [[UITOFP]](<4 x f32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
bb:
%tmp = uitofp <4 x i64> %arg to <4 x float>
ret <4 x float> %tmp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
index 92ef424a9283e..f6421dfc2c9e2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
@@ -7,21 +7,22 @@
define i3 @bug47619(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i3 %arg8) {
; CHECK-LABEL: name: bug47619
; CHECK: bb.1.bb:
- ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.0, align 16)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s3) = G_TRUNC [[LOAD]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s3)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i32) from %fixed-stack.0, align 16)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i3) = G_TRUNC [[LOAD]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i3)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb:
ret i3 %arg8
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
index d8fcf8161baf4..256ab9c2bd705 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
@@ -15,16 +15,16 @@ define void @stack_passed_i64(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %ar
i64 %arg7, i64 %arg8, ptr byval(i64) %arg9, ptr byval(i64) align(8) %arg10) {
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.2, align 16)
+ ; CHECK: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.2, align 16)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[COPY8:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX1]](p0)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[COPY9:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX2]](p0)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[COPY8]](p0) :: (load (s64) from %ir.arg9)
- ; CHECK: [[ADD0:%[0-9]+]]:_(s64) = G_ADD [[LOAD1]], [[LOAD]]
- ; CHECK: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[COPY9]](p0) :: (dereferenceable load (s64) from %ir.arg10)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD0]], [[LOAD2]]
- ; CHECK: G_STORE [[ADD1]](s64), [[COPY8]](p0) :: (volatile store (s64) into %ir.arg9)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[COPY8]](p0) :: (load (i64) from %ir.arg9)
+ ; CHECK: [[ADD0:%[0-9]+]]:_(i64) = G_ADD [[LOAD1]], [[LOAD]]
+ ; CHECK: [[LOAD2:%[0-9]+]]:_(i64) = G_LOAD [[COPY9]](p0) :: (dereferenceable load (i64) from %ir.arg10)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(i64) = G_ADD [[ADD0]], [[LOAD2]]
+ ; CHECK: G_STORE [[ADD1]](i64), [[COPY8]](p0) :: (volatile store (i64) into %ir.arg9)
; CHECK: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
index 00ad8fec95638..5be17b2b71d02 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
@@ -22,12 +22,12 @@ define void @test() nounwind ssp {
; NO_TRAP_UNREACHABLE-NEXT: $x0 = COPY [[FRAME_INDEX1]](p0)
; NO_TRAP_UNREACHABLE-NEXT: BL @callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $w0
; NO_TRAP_UNREACHABLE-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; NO_TRAP_UNREACHABLE-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; NO_TRAP_UNREACHABLE-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; NO_TRAP_UNREACHABLE-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
- ; NO_TRAP_UNREACHABLE-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (s64) from %stack.0.StackGuardSlot)
+ ; NO_TRAP_UNREACHABLE-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (i64) from %stack.0.StackGuardSlot)
; NO_TRAP_UNREACHABLE-NEXT: [[LOAD_STACK_GUARD2:%[0-9]+]]:gpr64sp(s64) = LOAD_STACK_GUARD :: (dereferenceable invariant load (p0) from @__stack_chk_guard)
- ; NO_TRAP_UNREACHABLE-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
- ; NO_TRAP_UNREACHABLE-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; NO_TRAP_UNREACHABLE-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
+ ; NO_TRAP_UNREACHABLE-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; NO_TRAP_UNREACHABLE-NEXT: G_BR %bb.2
; NO_TRAP_UNREACHABLE-NEXT: {{ $}}
; NO_TRAP_UNREACHABLE-NEXT: bb.3.entry:
@@ -53,12 +53,12 @@ define void @test() nounwind ssp {
; TRAP_UNREACHABLE-NEXT: $x0 = COPY [[FRAME_INDEX1]](p0)
; TRAP_UNREACHABLE-NEXT: BL @callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $w0
; TRAP_UNREACHABLE-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; TRAP_UNREACHABLE-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; TRAP_UNREACHABLE-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; TRAP_UNREACHABLE-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
- ; TRAP_UNREACHABLE-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (s64) from %stack.0.StackGuardSlot)
+ ; TRAP_UNREACHABLE-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (i64) from %stack.0.StackGuardSlot)
; TRAP_UNREACHABLE-NEXT: [[LOAD_STACK_GUARD2:%[0-9]+]]:gpr64sp(s64) = LOAD_STACK_GUARD :: (dereferenceable invariant load (p0) from @__stack_chk_guard)
- ; TRAP_UNREACHABLE-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
- ; TRAP_UNREACHABLE-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; TRAP_UNREACHABLE-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
+ ; TRAP_UNREACHABLE-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; TRAP_UNREACHABLE-NEXT: G_BR %bb.2
; TRAP_UNREACHABLE-NEXT: {{ $}}
; TRAP_UNREACHABLE-NEXT: bb.3.entry:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
index 08a1ac3135bd2..164435ee8f52d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
@@ -4,8 +4,8 @@
define <vscale x 2 x i64> @call_step_vector_i64() {
; CHECK-LABEL: name: call_step_vector_i64
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_STEP_VECTOR i64 1
- ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 2 x i64>) = G_STEP_VECTOR i64 1
+ ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $z0
entry:
%steps = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
@@ -15,8 +15,8 @@ entry:
define <vscale x 4 x i32> @call_step_vector_i32() {
; CHECK-LABEL: name: call_step_vector_i32
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_STEP_VECTOR i32 1
- ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 4 x i32>) = G_STEP_VECTOR i32 1
+ ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $z0
entry:
%steps = call <vscale x 4 x i32> @llvm.stepvector.nxv4i32()
@@ -26,8 +26,8 @@ entry:
define <vscale x 8 x i16> @call_step_vector_i16() {
; CHECK-LABEL: name: call_step_vector_i16
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_STEP_VECTOR i16 1
- ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 8 x i16>) = G_STEP_VECTOR i16 1
+ ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $z0
entry:
%steps = call <vscale x 8 x i16> @llvm.stepvector.nxv8i16()
@@ -37,8 +37,8 @@ entry:
define <vscale x 16 x i8> @call_step_vector_i8() {
; CHECK-LABEL: name: call_step_vector_i8
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_STEP_VECTOR i8 1
- ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 16 x i8>) = G_STEP_VECTOR i8 1
+ ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $z0
entry:
%steps = call <vscale x 16 x i8> @llvm.stepvector.nxv16i8()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
index baed1263008da..a9521bc852644 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
@@ -7,8 +7,8 @@ define void @store_nontemporal(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (non-temporal store (s32) into %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[COPY]](p0) :: (non-temporal store (i32) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store i32 0, ptr %ptr, align 4, !nontemporal !0
ret void
@@ -20,8 +20,8 @@ define void @store_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[COPY]](p0) :: (store (i32) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store i32 0, ptr %ptr, align 4
ret void
@@ -33,8 +33,8 @@ define void @store_volatile_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (volatile store (s32) into %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[COPY]](p0) :: (volatile store (i32) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store volatile i32 0, ptr %ptr, align 4
ret void
@@ -46,8 +46,8 @@ define void @store_falkor_strided_access(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store (s32) into %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[COPY]](p0) :: ("aarch64-strided-access" store (i32) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store i32 0, ptr %ptr, align 4, !falkor.strided.access !0
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
index 149bf72b053ef..546aa0f874e64 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
@@ -6,13 +6,13 @@ define i32 @extract_v4i32_vector_insert_const(<4 x i32> %a, <2 x i32> %b, i32 %c
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x s32>), 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x i32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x i32>), 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x i32>), [[C]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[EVEC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)
@@ -25,15 +25,18 @@ define double @extract_v4double_vector_insert_const(<4 x double> %a, <2 x double
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s64>) = G_INSERT_SUBVECTOR [[CONCAT_VECTORS]], [[COPY2]](<2 x s64>), 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s64>), [[C]](s64)
- ; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f64>) = G_CONCAT_VECTORS [[BITCAST]](<2 x f64>), [[BITCAST1]](<2 x f64>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x f64>) = G_INSERT_SUBVECTOR [[CONCAT_VECTORS]], [[BITCAST2]](<2 x f64>), 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f64) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x f64>), [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[EVEC]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
entry:
%vector = call <4 x double> @llvm.vector.insert.v4f64.v2f64(<4 x double> %a, <2 x double> %b, i64 0)
@@ -46,14 +49,15 @@ define float @extract_v4float_vector_insert_const(<4 x float> %a, <2 x float> %b
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[BITCAST]], [[COPY1]](<2 x s32>), 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: $s0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x f32>) = G_INSERT_SUBVECTOR [[BITCAST]], [[BITCAST1]](<2 x f32>), 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x f32>), [[C]](i64)
+ ; CHECK-NEXT: $s0 = COPY [[EVEC]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
entry:
%vector = call <4 x float> @llvm.vector.insert.v4f32.v2f32(<4 x float> %a, <2 x float> %b, i64 0)
@@ -66,13 +70,13 @@ define i32 @extract_v4i32_vector_insert(<4 x i32> %a, <2 x i32> %b, i32 %c) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x s32>), 0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[ZEXT]](s64)
- ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x i32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x i32>), 0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY2]](i32)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x i32>), [[ZEXT]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[EVEC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)
@@ -85,13 +89,13 @@ define i32 @extract_v4i32_vector_extract(<4 x i32> %a, <2 x i32> %b, i32 %c) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<4 x s32>), 0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[EXTRACT_SUBVECTOR]](<4 x s32>), [[ZEXT]](s64)
- ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<4 x i32>) = G_EXTRACT_SUBVECTOR [[COPY]](<4 x i32>), 0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY2]](i32)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[EXTRACT_SUBVECTOR]](<4 x i32>), [[ZEXT]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[EVEC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %a, i64 0)
@@ -104,13 +108,13 @@ define i32 @extract_v4i32_vector_extract_const(<vscale x 4 x i32> %a, i32 %c, pt
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $x1, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x s32>), 0
- ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 4 x s32>), [[COPY2]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x i32>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x i32>), 0
+ ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 4 x i32>), [[COPY2]](p0) :: (store (<vscale x 4 x i32>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <vscale x 4 x i32> @llvm.vector.extract(<vscale x 4 x i32> %a, i64 0)
@@ -123,13 +127,13 @@ define i32 @extract_v2double_vector_extract_const(<vscale x 2 x double> %a, i32
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $x1, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 2 x s64>), 0
- ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 2 x s64>), [[COPY2]](p0) :: (store (<vscale x 2 x s64>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x f64>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 2 x f64>), 0
+ ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 2 x f64>), [[COPY2]](p0) :: (store (<vscale x 2 x f64>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <vscale x 2 x double> @llvm.vector.extract(<vscale x 2 x double> %a, i64 0)
@@ -142,14 +146,14 @@ define i32 @extract_v4i32_vector_insert_const_vscale(<vscale x 4 x i32> %a, <vsc
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $x1, $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<vscale x 4 x s32>), 0
- ; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<vscale x 4 x s32>), [[COPY3]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x i32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<vscale x 4 x i32>), 0
+ ; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<vscale x 4 x i32>), [[COPY3]](p0) :: (store (<vscale x 4 x i32>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 0)
@@ -162,13 +166,13 @@ define i32 @extract_v4i32_vector_extract_const_illegal_fixed(<4 x i32> %a, ptr %
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[COPY1]](p0) :: (store (s32) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C]](i64)
+ ; CHECK-NEXT: G_STORE [[EVEC]](i32), [[COPY1]](p0) :: (store (i32) into %ir.p, align 16)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x i32> @llvm.vector.extract(<4 x i32> %a, i64 0)
@@ -181,15 +185,15 @@ define i32 @extract_v4i32_vector_extract_const_illegal_scalable(<vscale x 4 x i3
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s32>), [[MUL]](s64)
- ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[COPY1]](p0) :: (store (s32) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x i32>), [[MUL]](s64)
+ ; CHECK-NEXT: G_STORE [[EVEC]](i32), [[COPY1]](p0) :: (store (i32) into %ir.p, align 16)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x i32> @llvm.vector.extract(<vscale x 4 x i32> %a, i64 0)
@@ -202,18 +206,18 @@ define i32 @extract_v4i32_vector_insert_const_illegal_scalable(<vscale x 4 x i32
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $w0, $x1, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](s32), [[MUL]](s64)
- ; CHECK-NEXT: G_STORE [[IVEC]](<vscale x 4 x s32>), [[COPY3]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x i32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](i32), [[MUL]](s64)
+ ; CHECK-NEXT: G_STORE [[IVEC]](<vscale x 4 x i32>), [[COPY3]](p0) :: (store (<vscale x 4 x i32>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %a, <1 x i32> %b, i64 0)
@@ -226,16 +230,16 @@ define i32 @extract_v4i32_vector_insert_const_fixed(<4 x i32> %a, <1 x i32> %b,
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](s32), [[C]](s64)
- ; CHECK-NEXT: G_STORE [[IVEC]](<4 x s32>), [[COPY3]](p0) :: (store (<4 x s32>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](i32), [[C]](i64)
+ ; CHECK-NEXT: G_STORE [[IVEC]](<4 x i32>), [[COPY3]](p0) :: (store (<4 x i32>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x i32> @llvm.vector.insert.v4i32.v4i32(<4 x i32> %a, <1 x i32> %b, i64 0)
@@ -248,16 +252,16 @@ define i32 @extract_v4i32_vector_insert_const_fixed_illegal(<1 x i32> %a, <1 x i
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0, $d1, $w0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: G_STORE [[COPY4]](s32), [[COPY3]](p0) :: (store (s32) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY [[UV]](i32)
+ ; CHECK-NEXT: G_STORE [[COPY4]](i32), [[COPY3]](p0) :: (store (i32) into %ir.p, align 16)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x i32> @llvm.vector.insert.v1i32.v4i32(<1 x i32> %a, <1 x i32> %b, i64 0)
@@ -272,12 +276,12 @@ define i32 @extract_v4ptr_vector_insert_const_fixed_illegal(<1 x ptr> %a, <1 x p
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: G_STORE [[COPY4]](p0), [[COPY3]](p0) :: (store (p0) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x ptr> @llvm.vector.insert.v1ptr.v4ptr(<1 x ptr> %a, <1 x ptr> %b, i64 0)
@@ -290,16 +294,18 @@ define i32 @extract_v4ifloat_vector_insert_const_fixed_illegal(<1 x float> %a, <
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0, $d1, $s2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x f32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: G_STORE [[COPY4]](s32), [[COPY3]](p0) :: (store (s32) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY [[UV]](f32)
+ ; CHECK-NEXT: G_STORE [[COPY4]](f32), [[COPY3]](p0) :: (store (f32) into %ir.p, align 16)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x float> @llvm.vector.insert.v1f32.v4f32(<1 x float> %a, <1 x float> %b, i64 0)
@@ -316,10 +322,10 @@ define i32 @extract_v4iptr_vector_insert_const_fixed_illegal(<1 x ptr> %a, <1 x
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $d1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: G_STORE [[COPY4]](p0), [[COPY3]](p0) :: (store (p0) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x ptr> @llvm.vector.insert.v1ptr.v4ptr(<1 x ptr> %a, <1 x ptr> %b, i64 0)
@@ -332,18 +338,22 @@ define i32 @extract_v4iptr_vector_insert_const_fixed_legal(<4 x ptr> %a, <4 x pt
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[COPY2]](<2 x s64>), [[COPY3]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<2 x p0>), [[BITCAST1]](<2 x p0>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x p0>), [[BITCAST3]](<2 x p0>)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x p0>) = G_INSERT_SUBVECTOR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]](<4 x p0>), 0
; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<4 x p0>), [[COPY5]](p0) :: (store (<4 x p0>) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x ptr> @llvm.vector.insert.v4ptr.v4ptr(<4 x ptr> %a, <4 x ptr> %b, i64 0)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
index 1fa21bfb733e8..09efe53912453 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
@@ -6,9 +6,9 @@ define void @scmp_i32(i32 %arg1, i32 %arg2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(s4) = G_SCMP [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(i4) = G_SCMP [[COPY]](i32), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%res4 = call i4 @llvm.scmp.i4.i32(i32 %arg1, i32 %arg2)
ret void
@@ -19,9 +19,9 @@ define void @scmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(<4 x s32>) = G_SCMP [[COPY]](<4 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(<4 x i32>) = G_SCMP [[COPY]](<4 x i32>), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%res4 = call <4 x i32> @llvm.scmp.v4i32.i32(<4 x i32> %arg1, <4 x i32> %arg2)
ret void
@@ -32,9 +32,9 @@ define void @ucmp_i32(i32 %arg1, i32 %arg2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(s4) = G_UCMP [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(i4) = G_UCMP [[COPY]](i32), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%res4 = call i4 @llvm.ucmp.i4.i32(i32 %arg1, i32 %arg2)
ret void
@@ -45,9 +45,9 @@ define void @ucmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(<4 x s32>) = G_UCMP [[COPY]](<4 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(<4 x i32>) = G_UCMP [[COPY]](<4 x i32>), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%res4 = call <4 x i32> @llvm.ucmp.v4i32.i32(<4 x i32> %arg1, <4 x i32> %arg2)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
index 38c04e2a3ed69..d39fa9ecc3a42 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
@@ -7,45 +7,45 @@ define i32 @test_bittest(i16 %p) {
; CHECK-NEXT: successors: %bb.4(0x1b6db6db), %bb.5(0x64924925)
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 114
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ZEXT]], [[C3]]
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 59
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 114
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[ZEXT]], [[C3]]
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 59
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i32), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[ZEXT]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[ZEXT1]](s64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C6]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[ZEXT1]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i64), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.epilog:
- ; CHECK-NEXT: $w0 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C2]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cb1:
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
switch i16 %p, label %sw.epilog [
i16 58, label %cb1
@@ -71,47 +71,47 @@ define void @test_bittest_2_bt(i32 %p) {
; CHECK-NEXT: successors: %bb.5(0x345d1746), %bb.6(0x4ba2e8ba)
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 176
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.5
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 176
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.5
; CHECK-NEXT: G_BR %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.4(0x0ccccccd), %bb.7(0x73333333)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C2]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 38
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB1]](s32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.4
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB1]](i32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 38
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB1]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
; CHECK-NEXT: successors: %bb.2(0x76276276), %bb.5(0x09d89d8a)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[SUB]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 57351
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C5]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C6]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.2
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[C4]], [[SUB]](i32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 57351
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C5]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i32), [[C6]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.entry:
; CHECK-NEXT: successors: %bb.3(0x71c71c72), %bb.4(0x0e38e38e)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C7]], [[ZEXT]](s64)
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 365072220160
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C8]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND1]](s64), [[C9]]
- ; CHECK-NEXT: G_BRCOND [[ICMP3]](s1), %bb.3
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i64) = G_SHL [[C7]], [[ZEXT]](s64)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 365072220160
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SHL1]], [[C8]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND1]](i64), [[C9]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.bb37:
@@ -154,35 +154,35 @@ define i32 @test_bittest_single_bt_only_with_fallthrough(i16 %p) {
; CHECK-NEXT: successors: %bb.2(0x0aaaaaab), %bb.4(0x75555555)
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ZEXT]], [[C2]]
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 59
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[ZEXT]], [[C2]]
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 59
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.2(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C4]], [[ZEXT1]](s64)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C5]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C6]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C4]], [[ZEXT1]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C5]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i64), [[C6]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.epilog:
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cb1:
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
switch i16 %p, label %sw.epilog [
i16 58, label %cb1
@@ -203,36 +203,38 @@ define void @bit_test_block_incomplete_phi() {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[DEF]], [[C2]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.3(0x51745d17), %bb.4(0x2e8ba2e9)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[SUB]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 491
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C4]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C5]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[SUB]](i32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 491
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C4]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i32), [[C5]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
; CHECK-NEXT: successors:
- ; CHECK: bb.2.sw.epilog.i:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.sw.epilog.i:
; CHECK-NEXT: successors:
- ; CHECK: bb.3.if.end:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[DEF1]](p0) :: (load (p0) from `ptr undef`)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.return:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.3, [[C1]](s1), %bb.5
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i1) = G_PHI [[C]](i1), %bb.3, [[C1]](i1), %bb.5
; CHECK-NEXT: RET_ReallyLR
entry:
switch i32 undef, label %sw.epilog.i [
@@ -267,50 +269,50 @@ define i32 @test_odd_type(i328 %p) {
; CHECK-NEXT: successors: %bb.4(0x1b6db6db), %bb.5(0x64924925)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s384) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s328) = G_TRUNC [[MV]](s384)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s328) = G_CONSTANT i328 114
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s328) = G_CONSTANT i328 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s328) = G_SUB [[TRUNC]], [[C3]]
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](s328)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s328) = G_CONSTANT i328 59
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s328), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s384) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64), [[COPY2]](i64), [[COPY3]](i64), [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i328) = G_TRUNC [[MV]](s384)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i328) = G_CONSTANT i328 114
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i328) = G_CONSTANT i328 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i328) = G_SUB [[TRUNC]], [[C3]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](i328)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i328) = G_CONSTANT i328 59
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i328), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s328), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[TRUNC]](i328), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[TRUNC1]](s64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C6]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[TRUNC1]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i64), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.epilog:
- ; CHECK-NEXT: $w0 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C2]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cb1:
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
switch i328 %p, label %sw.epilog [
i328 58, label %cb1
@@ -332,47 +334,47 @@ define i32 @test_large_pow2_type(i256 %p) {
; CHECK-NEXT: successors: %bb.4(0x1b6db6db), %bb.5(0x64924925)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s256) = G_CONSTANT i256 114
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s256) = G_CONSTANT i256 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s256) = G_SUB [[MV]], [[C3]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](s256)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s256) = G_CONSTANT i256 59
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s256), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i256) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64), [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i256) = G_CONSTANT i256 114
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i256) = G_CONSTANT i256 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i256) = G_SUB [[MV]], [[C3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](i256)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i256) = G_CONSTANT i256 59
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i256), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[MV]](s256), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[MV]](i256), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[TRUNC]](s64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C6]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[TRUNC]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i64), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.epilog:
- ; CHECK-NEXT: $w0 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C2]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cb1:
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
switch i256 %p, label %sw.epilog [
i256 58, label %cb1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
index 3daeebe27a2a8..fd324071306e9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
@@ -1,14 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -mtriple=aarch64-unknown-unknown -stop-after=irtranslator -o - %s | FileCheck %s
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
define void @snork() {
+ ; CHECK-LABEL: name: snork
+ ; CHECK: bb.1.bb:
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i16) = G_LOAD [[C]](p0) :: (load (i16) from `ptr null`, !tbaa !0)
+ ; CHECK-NEXT: G_STORE [[LOAD]](i16), [[C2]](p0) :: (store (i16) into %ir.tmp5, !tbaa !0)
+ ; CHECK-NEXT: RET_ReallyLR
bb:
%tmp5 = getelementptr i16, ptr null, i64 2
%tmp6 = load i16, ptr null, align 2, !tbaa !0
store i16 %tmp6, ptr %tmp5, align 2, !tbaa !0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD %{{[0-9]+}}(p0) :: (load (s16) from `ptr null`, !tbaa !0)
- ; CHECK: G_STORE [[LOAD]](s16), %{{[0-9]+}}(p0) :: (store (s16) into %ir.tmp5, !tbaa !0)
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
index d87e9c4b18550..598e91fa0e2f5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
@@ -6,9 +6,9 @@ define i32 @call_trunc_no_flags(i64 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = trunc i64 %a to i32
@@ -20,9 +20,9 @@ define i32 @call_trunc_nsw_flags(i64 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nsw G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = nsw G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = trunc nsw i64 %a to i32
@@ -34,9 +34,9 @@ define i32 @call_trunc_nuw_flags(i64 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nuw G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = nuw G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = trunc nuw i64 %a to i32
@@ -48,9 +48,9 @@ define i32 @call_trunc_all_flags(i64 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nuw nsw G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = nuw nsw G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = trunc nsw nuw i64 %a to i32
@@ -62,10 +62,10 @@ define <2 x i64> @call_trunc_noop_signed_vector(<2 x i64> %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = nsw G_TRUNC [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[TRUNC]](<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[SEXT]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i32>) = nsw G_TRUNC [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<2 x i64>) = G_SEXT [[TRUNC]](<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[SEXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%truncate = trunc nsw <2 x i64> %a to <2 x i32>
@@ -78,10 +78,10 @@ define <2 x i64> @call_trunc_noop_unsigned_vector(<2 x i64> %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = nuw G_TRUNC [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[TRUNC]](<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i32>) = nuw G_TRUNC [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[TRUNC]](<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%truncate = trunc nuw <2 x i64> %a to <2 x i32>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
index fbffb50bcbc8a..a7f3888a46fed 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
@@ -35,7 +35,7 @@ define dso_local void @test() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY1]](p0)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[GV]](p0)
; CHECK-NEXT: BL @printf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
@@ -71,7 +71,7 @@ define void @test2() #0 personality ptr @__gcc_personality_v0 {
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[DEF]](p0)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3866633 /* reguse:GPR64common */, [[COPY]]
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
@@ -85,7 +85,7 @@ define void @test2() #0 personality ptr @__gcc_personality_v0 {
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
; CHECK-NEXT: BL @_Unwind_Resume, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
index 0b7fae47a65a5..950fdc60d6eaa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
@@ -6,10 +6,10 @@ define void @vector_deinterleave2_v4i32(<4 x i32> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[DEF]], shufflemask(0, 2)
- ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[DEF]], shufflemask(1, 3)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x i32>), [[DEF]], shufflemask(0, 2)
+ ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x i32>), [[DEF]], shufflemask(1, 3)
; CHECK-NEXT: RET_ReallyLR
%res = call {<2 x i32>, <2 x i32>} @llvm.vector.deinterleave2.v4i32(<4 x i32> %a)
ret void
@@ -20,14 +20,14 @@ define void @vector_deinterleave2_v8f32(<8 x float> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x s32>), [[BITCAST1]](<4 x s32>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x s32>), [[DEF]], shufflemask(0, 2, 4, 6)
- ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x s32>), [[DEF]], shufflemask(1, 3, 5, 7)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x f32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x f32>), [[BITCAST1]](<4 x f32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x f32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x f32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x f32>), [[DEF]], shufflemask(0, 2, 4, 6)
+ ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<4 x f32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x f32>), [[DEF]], shufflemask(1, 3, 5, 7)
; CHECK-NEXT: RET_ReallyLR
%res = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %a)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
index 0d8ac82c10513..ebf0b7868604b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
@@ -6,9 +6,9 @@ define void @vector_interleave2_v4i32(<2 x i32> %a, <2 x i32> %b) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s32>), [[COPY1]], shufflemask(0, 2, 1, 3)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x i32>), [[COPY1]], shufflemask(0, 2, 1, 3)
; CHECK-NEXT: RET_ReallyLR
%res = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b)
ret void
@@ -19,11 +19,11 @@ define void @vector_interleave2_v8f32(<4 x float> %a, <4 x float> %b) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x s32>) = G_SHUFFLE_VECTOR [[BITCAST]](<4 x s32>), [[BITCAST1]], shufflemask(0, 4, 1, 5, 2, 6, 3, 7)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x f32>) = G_SHUFFLE_VECTOR [[BITCAST]](<4 x f32>), [[BITCAST1]], shufflemask(0, 4, 1, 5, 2, 6, 3, 7)
; CHECK-NEXT: RET_ReallyLR
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
index d06e2c64c2457..137064dc3464a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
@@ -4,8 +4,8 @@
define i64 @call_vscale_i64() {
; CHECK-LABEL: name: call_vscale_i64
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
- ; CHECK-NEXT: $x0 = COPY [[VSCALE]](s64)
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(i64) = G_VSCALE i64 1
+ ; CHECK-NEXT: $x0 = COPY [[VSCALE]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%vscale = call i64 @llvm.vscale.64()
@@ -15,9 +15,9 @@ entry:
define i64 @call_vscale_i32() {
; CHECK-LABEL: name: call_vscale_i32
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s32) = G_VSCALE i32 1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s32)
- ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(i32) = G_VSCALE i32 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[VSCALE]](i32)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%vscale = call i32 @llvm.vscale.32()
@@ -28,9 +28,9 @@ entry:
define i64 @call_vscale_i16() {
; CHECK-LABEL: name: call_vscale_i16
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s16) = G_VSCALE i16 1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s16)
- ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(i16) = G_VSCALE i16 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[VSCALE]](i16)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%vscale = call i16 @llvm.vscale.16()
@@ -41,9 +41,9 @@ entry:
define i64 @call_vscale_i8() {
; CHECK-LABEL: name: call_vscale_i8
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s8) = G_VSCALE i8 1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s8)
- ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(i8) = G_VSCALE i8 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[VSCALE]](i8)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%vscale = call i8 @llvm.vscale.8()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index 1a210644f6517..da37555a4ef37 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -46,9 +46,8 @@ body: |
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD]]
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR]], [[C]]
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY1]](p0) :: (load (s16) from unknown-address + 8, align 8)
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 8, align 8)
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 10, align 2)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD3]](s32), [[DEF]](s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C3]](s64)
@@ -57,13 +56,15 @@ body: |
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[C]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[OR4]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[OR5]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
- ; CHECK-NEXT: G_STORE [[COPY2]](s64), %ptr(p0) :: (store (s64), align 16)
+ ; CHECK-NEXT: G_STORE [[COPY1]](s64), %ptr(p0) :: (store (s64), align 16)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 8, align 8)
- ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD3]](p0) :: (store (s16) into unknown-address + 8, align 8)
+ ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD4]](p0) :: (store (s8) into unknown-address + 10, align 2)
%ptr:_(p0) = COPY $x0
%a:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
%b:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
@@ -95,17 +96,17 @@ body: |
; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C]]
; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND5]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND6]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND8]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND9]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
@@ -139,17 +140,17 @@ body: |
; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C]]
; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND5]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND6]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND8]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND9]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
index 4d461c971d332..f08db556d14d8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
@@ -54,67 +54,67 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: boolean_vector_to_scalar
- ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s8>) = G_IMPLICIT_DEF
+ ; CHECK: [[DEF:%[0-9]+]]:_(<8 x i8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C4]](s64)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C5]](s64)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C1]]
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C6]](s64)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C1]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C7]](s64)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C1]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64)
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C8]](s64)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8)
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C1]]
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64)
- ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C9]](s64)
- ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C1]]
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64)
- ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[FRAME_INDEX]](p0) :: (store (s8) into %stack.0)
- ; CHECK-NEXT: %bc:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s8) from %stack.0)
- ; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %bc(s8)
- ; CHECK-NEXT: $w0 = COPY %ext(s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i8)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC1]](i8)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C3]](i64)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C4]](i64)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC2]](i8)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C4]](i64)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C5]](i64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC3]](i8)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ANYEXT3]], [[C1]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C5]](i64)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C6]](i64)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC4]](i8)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ANYEXT4]], [[C1]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C6]](i64)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C7]](i64)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC5]](i8)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ANYEXT5]], [[C1]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C7]](i64)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C8]](i64)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC6]](i8)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[ANYEXT6]], [[C1]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C8]](i64)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C9]](i64)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC7]](i8)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[ANYEXT7]], [[C1]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C9]](i64)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[OR6]], [[SHL7]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[OR7]](i32)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i8), [[FRAME_INDEX]](p0) :: (store (i8) into %stack.0)
+ ; CHECK-NEXT: %bc:_(i8) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i8) from %stack.0)
+ ; CHECK-NEXT: %ext:_(i32) = G_ANYEXT %bc(i8)
+ ; CHECK-NEXT: $w0 = COPY %ext(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %vec:_(<8 x s1>) = G_IMPLICIT_DEF
- %bc:_(s8) = G_BITCAST %vec(<8 x s1>)
- %ext:_(s32) = G_ANYEXT %bc(s8)
- $w0 = COPY %ext(s32)
+ %vec:_(<8 x i1>) = G_IMPLICIT_DEF
+ %bc:_(i8) = G_BITCAST %vec(<8 x i1>)
+ %ext:_(i32) = G_ANYEXT %bc(i8)
+ $w0 = COPY %ext(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
index 2378401b2e7ed..c220e14177bc9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
@@ -198,8 +198,8 @@ body: |
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[UV]](s64), [[COPY]](p0) :: (store (s32), align 16)
; CHECK-NEXT: G_STORE [[LSHR1]](s64), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4, align 4)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C1]](s64)
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[UV1]](s64), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 6, align 2)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
index 26230efbbe863..19f604fbd2b64 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
@@ -20,13 +20,13 @@ body: |
; CHECK-NOLSE-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NOLSE-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NOLSE-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NOLSE-NEXT: [[COPY5:%[0-9]+]]:gpr64(s64) = COPY [[COPY1]](s64)
- ; CHECK-NOLSE-NEXT: [[COPY6:%[0-9]+]]:gpr64(s64) = COPY [[COPY2]](s64)
- ; CHECK-NOLSE-NEXT: [[COPY7:%[0-9]+]]:gpr64(s64) = COPY [[COPY3]](s64)
- ; CHECK-NOLSE-NEXT: [[COPY8:%[0-9]+]]:gpr64(s64) = COPY [[COPY4]](s64)
- ; CHECK-NOLSE-NEXT: early-clobber %14:gpr64common(s64), early-clobber %15:gpr64common(s64), early-clobber %17:gpr32common = CMP_SWAP_128_ACQUIRE [[COPY]](p0), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64), [[COPY8]](s64) :: (load store acquire acquire (s128))
+ ; CHECK-NOLSE-NEXT: [[COPY5:%[0-9]+]]:gpr64(i64) = COPY [[COPY1]](s64)
+ ; CHECK-NOLSE-NEXT: [[COPY6:%[0-9]+]]:gpr64(i64) = COPY [[COPY2]](s64)
+ ; CHECK-NOLSE-NEXT: [[COPY7:%[0-9]+]]:gpr64(i64) = COPY [[COPY3]](s64)
+ ; CHECK-NOLSE-NEXT: [[COPY8:%[0-9]+]]:gpr64(i64) = COPY [[COPY4]](s64)
+ ; CHECK-NOLSE-NEXT: early-clobber %14:gpr64common(i64), early-clobber %15:gpr64common(i64), early-clobber %17:gpr32common = CMP_SWAP_128_ACQUIRE [[COPY]](p0), [[COPY5]](i64), [[COPY6]](i64), [[COPY7]](i64), [[COPY8]](i64) :: (load store acquire acquire (s128))
; CHECK-NOLSE-NEXT: [[COPY9:%[0-9]+]]:gpr64 = COPY %17
- ; CHECK-NOLSE-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES %14(s64), %15(s64)
+ ; CHECK-NOLSE-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES %14(i64), %15(i64)
; CHECK-NOLSE-NEXT: [[COPY10:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
; CHECK-NOLSE-NEXT: G_STORE [[COPY10]](s128), [[COPY]](p0) :: (store (s128))
; CHECK-NOLSE-NEXT: RET_ReallyLR
@@ -42,9 +42,9 @@ body: |
; CHECK-LSE-NEXT: [[REG_SEQUENCE:%[0-9]+]]:xseqpairsclass(s128) = REG_SEQUENCE [[COPY1]](s64), %subreg.sube64, [[COPY2]](s64), %subreg.subo64
; CHECK-LSE-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:xseqpairsclass(s128) = REG_SEQUENCE [[COPY3]](s64), %subreg.sube64, [[COPY4]](s64), %subreg.subo64
; CHECK-LSE-NEXT: [[CASPAX:%[0-9]+]]:xseqpairsclass(s128) = CASPAX [[REG_SEQUENCE]](s128), [[REG_SEQUENCE1]](s128), [[COPY]](p0) :: (load store acquire acquire (s128))
- ; CHECK-LSE-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[CASPAX]](s128), 0
- ; CHECK-LSE-NEXT: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[CASPAX]](s128), 64
- ; CHECK-LSE-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[EXTRACT]](s64), [[EXTRACT1]](s64)
+ ; CHECK-LSE-NEXT: [[EXTRACT:%[0-9]+]]:_(i64) = G_EXTRACT [[CASPAX]](s128), 0
+ ; CHECK-LSE-NEXT: [[EXTRACT1:%[0-9]+]]:_(i64) = G_EXTRACT [[CASPAX]](s128), 64
+ ; CHECK-LSE-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[EXTRACT]](i64), [[EXTRACT1]](i64)
; CHECK-LSE-NEXT: [[COPY5:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
; CHECK-LSE-NEXT: G_STORE [[COPY5]](s128), [[COPY]](p0) :: (store (s128))
; CHECK-LSE-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
index c00ce2242a888..ba7b3b426fce4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
@@ -97,17 +97,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C2]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C3]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C6]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C6]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C7]](s64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C7]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s318) = G_CONSTANT i318 1234
@@ -136,11 +136,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s158) = G_CONSTANT i158 1234
@@ -170,11 +170,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s16), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s142) = G_CONSTANT i142 1234
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
index f7550ceb2799a..a5c43a4ef9b46 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
@@ -16,8 +16,8 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: EH_LABEL <mcsymbol >
@@ -30,12 +30,12 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
; CHECK-NEXT: G_STORE [[COPY]](p0), [[FRAME_INDEX]](p0) :: (store (p0) into %ir.exn.slot)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
- ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.ehselector.slot)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %ir.ehselector.slot)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
index dafc304901209..fe0d46d47debd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
@@ -327,8 +327,8 @@ body: |
; CHECK-NEXT: %idx:_(s64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[COPY]](<2 x s64>), [[FRAME_INDEX]](p0) :: (store (<2 x s64>) into %stack.0, align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %idx, [[C1]]
@@ -425,8 +425,8 @@ body: |
; CHECK-NEXT: %idxprom:_(s64) = G_SEXT %idx(s32)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[COPY]](<4 x s32>), [[FRAME_INDEX]](p0) :: (store (<4 x s32>) into %stack.0, align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %idxprom, [[C1]]
@@ -459,8 +459,8 @@ body: |
; CHECK-NEXT: %idxprom:_(s64) = G_SEXT %idx(s32)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[COPY]](<8 x s16>), [[FRAME_INDEX]](p0) :: (store (<8 x s16>) into %stack.0, align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %idxprom, [[C1]]
@@ -494,8 +494,8 @@ body: |
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST]](<2 x s64>), [[FRAME_INDEX]](p0) :: (store (<2 x s64>) into %stack.0, align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
index 131a6563a1bcb..4f036d275b24d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
@@ -16,14 +16,15 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %val(s32), [[DEF]](s32)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %sign(s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](<2 x s32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[OR]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK-NEXT: %fcopysign:_(s32) = COPY [[UV]](s32)
; CHECK-NEXT: $s0 = COPY %fcopysign(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -48,14 +49,15 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %val(s64), [[DEF]](s64)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %sign(s64), [[DEF]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
- ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
- ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = disjoint G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[OR]](<2 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C1]](i64), [[C1]](i64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = disjoint G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[OR]](<2 x i64>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK-NEXT: %fcopysign:_(s64) = COPY [[UV]](s64)
; CHECK-NEXT: $d0 = COPY %fcopysign(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
index 42538d58c87bf..e3c0d4989fc2c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
@@ -150,10 +150,11 @@ body: |
; NO-FP16: liveins: $h0
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %x:_(s16) = COPY $h0
- ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %x(s16)
- ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT]], [[C]]
- ; NO-FP16-NEXT: %op:_(s16) = G_TRUNC [[XOR]](s32)
+ ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT %x(s16)
+ ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -32768
+ ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[ANYEXT]], [[C]]
+ ; NO-FP16-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[XOR]](i32)
+ ; NO-FP16-NEXT: %op:_(s16) = G_BITCAST [[TRUNC]](i16)
; NO-FP16-NEXT: $h0 = COPY %op(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
index 50394b6bbbf99..1bbdeedd87be8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
@@ -21,8 +21,8 @@ body: |
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
; CHECK-NEXT: G_STORE [[FPEXT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-NEXT: G_STORE [[FPEXT1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%0:_(<4 x s32>) = COPY $q0
@@ -61,9 +61,9 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f32>), [[UV1:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x f32>)
; CHECK-NEXT: $q0 = COPY [[FPEXT1]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(<4 x s16>) = COPY $d0
@@ -83,10 +83,10 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f32>), [[UV1:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x f32>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT1]](<2 x s64>)
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT2]](<2 x s64>)
; CHECK-NEXT: $d0 = COPY [[UV2]](s64)
@@ -114,10 +114,10 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f32>), [[UV1:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x f32>)
; CHECK-NEXT: $q0 = COPY [[FPEXT1]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[FPEXT2]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
@@ -140,14 +140,14 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s32>), [[UV3:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<2 x s32>), [[UV5:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT1]](<4 x s32>)
- ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV2]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV3]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT4:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV4]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT5:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV5]](<2 x s32>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV]](<4 x s16>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV1]](<4 x s16>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x f32>), [[UV3:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<2 x f32>), [[UV5:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT1]](<4 x f32>)
+ ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV2]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV3]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT4:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV4]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT5:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV5]](<2 x f32>)
; CHECK-NEXT: $q0 = COPY [[FPEXT2]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[FPEXT3]](<2 x s64>)
; CHECK-NEXT: $q2 = COPY [[FPEXT4]](<2 x s64>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
index a19ab0b5e7bfc..0113170631931 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
@@ -134,8 +134,8 @@ body: |
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[FPTRUNC]](<2 x s32>), [[FPTRUNC1]](<2 x s32>)
; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[FPTRUNC2]](<2 x s32>), [[FPTRUNC3]](<2 x s32>)
; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<4 x s32>), [[COPY5]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY5]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY5]], [[C]](i64)
; CHECK-NEXT: G_STORE [[CONCAT_VECTORS1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%2:_(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
index 1cf066dc894de..1bb66511ae7eb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
@@ -255,11 +255,11 @@ body: |
; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[BITCAST]](<4 x s32>)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UITOFP]](<4 x s32>)
; CHECK-NEXT: G_STORE [[UV6]](s32), [[COPY]](p0) :: (store (s32), align 16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
; CHECK-NEXT: G_STORE [[UV7]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
; CHECK-NEXT: G_BR %bb.1
bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
index fafaa4646fa22..dac87b1cedaeb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
@@ -17,8 +17,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -44,8 +44,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -71,8 +71,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -98,8 +98,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -127,8 +127,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -154,8 +154,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -181,8 +181,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -208,8 +208,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
index 29a3e383a4f53..98f822d09b035 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
@@ -45,8 +45,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x8
@@ -71,8 +71,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x8
@@ -94,8 +94,8 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64), align 16)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[C1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x8
@@ -139,8 +139,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: $q0 = COPY [[LOAD]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[LOAD1]](<2 x s64>)
@@ -165,8 +165,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: $q0 = COPY [[LOAD]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[LOAD1]](<2 x s64>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index eb305812a2061..92a82ba7bbf2b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -331,8 +331,8 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[DEF]](<16 x s8>), %ptr(p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[DEF]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%val:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -354,8 +354,8 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[DEF]](<8 x s16>), %ptr(p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[DEF]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%val:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -377,8 +377,8 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[DEF]](<4 x s32>), %ptr(p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[DEF]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%val:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -400,8 +400,8 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%val:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -422,11 +422,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD %ptr(p0) :: (load (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[PTR_ADD]](p0) :: (load (<16 x s8>) from unknown-address + 16)
; CHECK-NEXT: G_STORE [[LOAD]](<16 x s8>), %ptr(p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](<16 x s8>), [[PTR_ADD1]](p0) :: (store (<16 x s8>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -447,11 +447,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD %ptr(p0) :: (load (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load (<8 x s16>) from unknown-address + 16)
; CHECK-NEXT: G_STORE [[LOAD]](<8 x s16>), %ptr(p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](<8 x s16>), [[PTR_ADD1]](p0) :: (store (<8 x s16>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -472,11 +472,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD %ptr(p0) :: (load (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p0) :: (load (<4 x s32>) from unknown-address + 16)
; CHECK-NEXT: G_STORE [[LOAD]](<4 x s32>), %ptr(p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](<4 x s32>), [[PTR_ADD1]](p0) :: (store (<4 x s32>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -497,11 +497,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: G_STORE [[LOAD]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -551,11 +551,11 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>))
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR2]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 32)
; CHECK-NEXT: RET_ReallyLR
%val:_(<6 x s64>) = G_IMPLICIT_DEF
@@ -577,8 +577,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $s0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
; CHECK-NEXT: G_STORE [[UV]](s16), [[COPY]](p0) :: (store (s16), align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UV1]](s16), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
@@ -599,8 +599,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s16)
@@ -644,7 +644,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[OR1]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64)
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 16)
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD2]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
@@ -712,20 +713,20 @@ body: |
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load (<2 x s64>), align 64)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](i64)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 32, align 32)
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST3]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 64)
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST1]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST4]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](i64)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST2]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST5]](<2 x s64>), [[PTR_ADD3]](p0) :: (store (<2 x s64>) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
index 30afd7e85dfa7..b03163ee63f77 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
@@ -60,8 +60,8 @@ body: |
; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
%vec:_(<32 x s8>) = G_IMPLICIT_DEF
%vec1:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -129,8 +129,8 @@ body: |
; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
%vec:_(<16 x s16>) = G_IMPLICIT_DEF
%vec1:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -198,8 +198,8 @@ body: |
; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
%vec:_(<8 x s32>) = G_IMPLICIT_DEF
%vec1:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -220,12 +220,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND %vec, [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND %vec1, [[XOR]]
; CHECK-NEXT: %smin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY %smin(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -247,22 +247,22 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -330,8 +330,8 @@ body: |
; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<16 x s8>) = G_UMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
%vec:_(<32 x s8>) = G_IMPLICIT_DEF
%vec1:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -399,8 +399,8 @@ body: |
; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<8 x s16>) = G_UMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
%vec:_(<16 x s16>) = G_IMPLICIT_DEF
%vec1:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -468,8 +468,8 @@ body: |
; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<4 x s32>) = G_UMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
%vec:_(<8 x s32>) = G_IMPLICIT_DEF
%vec1:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -490,12 +490,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND %vec, [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND %vec1, [[XOR]]
; CHECK-NEXT: %umin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY %umin(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -517,22 +517,22 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -622,8 +622,8 @@ body: |
; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<16 x s8>) = G_SMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
%vec:_(<32 x s8>) = G_IMPLICIT_DEF
%vec1:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -669,8 +669,8 @@ body: |
; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<8 x s16>) = G_SMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
%vec:_(<16 x s16>) = G_IMPLICIT_DEF
%vec1:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -738,8 +738,8 @@ body: |
; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<4 x s32>) = G_SMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
%vec:_(<8 x s32>) = G_IMPLICIT_DEF
%vec1:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -760,12 +760,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND %vec, [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND %vec1, [[XOR]]
; CHECK-NEXT: %smax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY %smax(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -787,22 +787,22 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -870,8 +870,8 @@ body: |
; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<16 x s8>) = G_UMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
%vec:_(<32 x s8>) = G_IMPLICIT_DEF
%vec1:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -939,8 +939,8 @@ body: |
; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<8 x s16>) = G_UMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
%vec:_(<16 x s16>) = G_IMPLICIT_DEF
%vec1:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -1008,8 +1008,8 @@ body: |
; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<4 x s32>) = G_UMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
%vec:_(<8 x s32>) = G_IMPLICIT_DEF
%vec1:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -1030,12 +1030,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND %vec, [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND %vec1, [[XOR]]
; CHECK-NEXT: %umax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY %umax(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -1057,22 +1057,22 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
index b6488e94d7859..28ecce778c741 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
@@ -90,17 +90,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64))
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -129,11 +129,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64))
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 8)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -162,11 +162,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64))
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s16), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 16, align 8)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index 9edc1cb0b213d..a75c22fd74360 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -83,17 +83,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index 47aa570720a90..31d30126dd65d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -714,8 +714,8 @@ body: |
; CHECK-NEXT: %ptr1:_(p0) = COPY $x1
; CHECK-NEXT: %ptr2:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -727,8 +727,8 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -902,8 +902,8 @@ body: |
; CHECK-NEXT: %ptr2:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
@@ -917,8 +917,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD3]](<2 x s64>)
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
index a18bd0f2f90eb..bbb4ff258dfa5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
@@ -160,9 +160,10 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[IVEC]], [[C]](s64), [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s64), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[IVEC]], [[C]](s64), [[C2]](i64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[IVEC1]]
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
index 49e03251daa6c..543de33847303 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
@@ -29,17 +29,17 @@ body: |
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.v1ptr)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.v2ptr)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](s128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD1]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: BL &__udivti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
@@ -71,17 +71,17 @@ body: |
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.v1ptr)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.v2ptr)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](s128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD1]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: BL &__divti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
index 1c5ae0d49a148..0e41f0c21bfd9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
@@ -125,8 +125,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](i64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
@@ -197,8 +197,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](i64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
@@ -244,8 +244,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C2]](i64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C3]](s64), [[C3]](s64)
@@ -291,9 +291,9 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP2]], 1
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[DEF1]], [[TRUNC]](s16), [[C1]](s64)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[DEF1]], [[TRUNC]](s16), [[C1]](i64)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s16)
@@ -365,14 +365,16 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C1]](i64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[PTRTOINT]](<2 x s64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[PTRTOINT1]](<2 x s64>)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT]], [[SHUF]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT1]], [[XOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[BITCAST]], [[SHUF]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[BITCAST1]], [[XOR]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x s64>)
; CHECK-NEXT: $q0 = COPY [[INTTOPTR]](<2 x p0>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
index 352f4e7bd0b38..364df8a7c8cc9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
@@ -137,8 +137,8 @@ body: |
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY1]](<2 x s64>), [[COPY2]], shufflemask(1, 2)
; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY3]](<2 x s64>), [[COPY]], shufflemask(1, 2)
; CHECK-NEXT: G_STORE [[SHUF]](<2 x s64>), [[COPY4]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY4]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY4]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SHUF1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%3:_(<2 x s64>) = COPY $q0
@@ -180,8 +180,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[EVEC]](s32), [[EVEC1]](s32), [[EVEC2]](s32), [[EVEC3]](s32)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY1]](<4 x s32>), [[COPY]], shufflemask(2, 6, 5, 3)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY4]], [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY4]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[SHUF]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%3:_(<4 x s32>) = COPY $q0
@@ -243,11 +243,11 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[EVEC]](s64), [[EVEC1]](s64)
; CHECK-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[EVEC2]](s64), [[EVEC3]](s64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR6]](<2 x s64>), [[COPY8]](p0) :: (store (<2 x s64>), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR7]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C3]](i64)
; CHECK-NEXT: G_STORE [[SHUF]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR
%3:_(s64) = COPY $d0
@@ -292,14 +292,14 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[DEF]](s32)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[DEF]](s32)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]], shufflemask(0, 1, 5, 6)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](i64)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[EVEC]](s32), [[EVEC1]](s32), [[EVEC2]](s32), [[EVEC3]](s32)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR2]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -414,23 +414,23 @@ body: |
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]], shufflemask(3, 4, 7, 0)
; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]], shufflemask(1, 5, undef, undef)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](s64)
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF1]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF1]](<4 x s32>), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](i64)
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF1]](<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF1]](<4 x s32>), [[C1]](i64)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[EVEC]](s32), [[EVEC1]](s32)
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[EVEC2]](s32), [[EVEC3]](s32)
; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[EVEC4]](s32), [[EVEC5]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s32>), [[BUILD_VECTOR3]](<2 x s32>)
; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<4 x s32>), [[COPY8]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR4]](<2 x s32>), [[PTR_ADD]](p0) :: (store (<2 x s32>) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR
%3:_(s32) = COPY $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
index 1df6297e36383..84e4ca21a5575 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
@@ -21,58 +21,58 @@ body: |
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C1]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C4]](s64)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C5]](s64)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C6]](s64)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C2]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C7]](s64)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C2]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64)
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C8]](s64)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8)
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C2]]
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64)
- ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C9]](s64)
- ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C2]]
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64)
- ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32)
- ; CHECK-NEXT: G_STORE [[TRUNC3]](s8), %ptr(p0) :: (store (s8))
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C1]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](s8)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C1]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C3]], [[SHL]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C4]](i64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC1]](s8)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C4]](i64)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C5]](i64)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC2]](s8)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C2]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C5]](i64)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C6]](i64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC3]](s8)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ANYEXT3]], [[C2]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C6]](i64)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C7]](i64)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC4]](s8)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ANYEXT4]], [[C2]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C7]](i64)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C8]](i64)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC5]](s8)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ANYEXT5]], [[C2]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C8]](i64)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C9]](i64)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC6]](s8)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[ANYEXT6]], [[C2]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C9]](i64)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C10]](i64)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC7]](s8)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[ANYEXT7]], [[C2]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[OR6]], [[SHL7]]
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[OR7]](i32)
+ ; CHECK-NEXT: G_STORE [[TRUNC3]](i8), %ptr(p0) :: (store (i8))
; CHECK-NEXT: RET_ReallyLR
%1:_(<4 x s32>) = COPY $q0
%2:_(<4 x s32>) = COPY $q1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
index 4f93f69023b4e..eaae73dd90b7e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
@@ -23,21 +23,21 @@ body: |
; CHECK-LINUX-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-LINUX-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-LINUX-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load (s64))
- ; CHECK-LINUX-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-LINUX-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-LINUX-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-LINUX-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-LINUX-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8)
- ; CHECK-LINUX-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-LINUX-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
+ ; CHECK-LINUX-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-LINUX-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
; CHECK-LINUX-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from unknown-address + 16)
- ; CHECK-LINUX-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-LINUX-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-LINUX-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-LINUX-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
; CHECK-LINUX-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from unknown-address + 24)
; CHECK-LINUX-NEXT: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store (s64))
- ; CHECK-LINUX-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-LINUX-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-LINUX-NEXT: G_STORE [[LOAD1]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-LINUX-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-LINUX-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-LINUX-NEXT: G_STORE [[LOAD2]](s64), [[PTR_ADD4]](p0) :: (store (s64) into unknown-address + 16)
- ; CHECK-LINUX-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-LINUX-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-LINUX-NEXT: G_STORE [[LOAD3]](s64), [[PTR_ADD5]](p0) :: (store (s64) into unknown-address + 24)
; CHECK-LINUX-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
index c2bf95ce21adf..afa2f76375b15 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
@@ -135,8 +135,8 @@ body: |
; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C4]]
; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND7]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD3]](s32), [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ADD3]], [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](i32), [[ADD3]], [[C1]]
; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C1]]
; CHECK-NEXT: [[SEXT4:%[0-9]+]]:_(s64) = G_SEXT [[AND8]](s32)
; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s64) = G_MUL [[SEXT4]], [[C2]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index 1e1ae01786c05..aadb873da633c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -45,17 +45,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[XOR3]], [[C]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[XOR4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
@@ -89,17 +89,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[XOR3]], [[C]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[XOR4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s319) = G_IMPLICIT_DEF
@@ -132,11 +132,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s158) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
index dc2e1c5dc28d4..773f65c1d1b07 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
@@ -884,10 +884,11 @@ body: |
; CHECK-LABEL: name: ldrsrox
; CHECK: liveins: $d0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $d0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK-NEXT: [[LDRSroX:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[COPY1]], 0, 0 :: (load (s32) from %ir.addr)
- ; CHECK-NEXT: $s2 = COPY [[LDRSroX]]
+ ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADDXrr]], 0 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: $s2 = COPY [[LDRSui]]
; CHECK-NEXT: RET_ReallyLR implicit $h2
%0:gpr(p0) = COPY $d0
%1:gpr(s64) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
index c4e07de265edd..3edc7774ec4d9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
@@ -19,36 +19,36 @@ define i32 @foo() {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C3]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV3]](p0) :: (store (s32) into @var2)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[GV3]](p0) :: (store (i32) into @var2)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: G_STORE [[C6]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[C6]](i32), [[GV4]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV5]](p0) :: (store (s32) into @var3)
- ; CHECK-NEXT: G_STORE [[C6]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[GV5]](p0) :: (store (i32) into @var3)
+ ; CHECK-NEXT: G_STORE [[C6]](i32), [[GV4]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C7]](s32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C7]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, ptr @var1, align 4
@@ -80,26 +80,26 @@ define i32 @darwin_tls() {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @tls_gv
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[GV]](p0) :: (dereferenceable load (i32) from @tls_gv)
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: G_STORE [[LOAD1]](s32), [[GV3]](p0) :: (store (s32) into @var2)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](i32), [[GV3]](p0) :: (store (i32) into @var2)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C3]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, ptr @var1, align 4
@@ -122,36 +122,36 @@ define i32 @imm_cost_too_large_cost_of_2() {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2228259
- ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2228259
+ ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(i32) = G_CONSTANT_FOLD_BARRIER [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s32), [[GV3]](p0) :: (store (s32) into @var2)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV3]](p0) :: (store (i32) into @var2)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV4]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s32), [[GV5]](p0) :: (store (s32) into @var3)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C4]](s32)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV5]](p0) :: (store (i32) into @var3)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C4]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, ptr @var1, align 4
@@ -179,36 +179,36 @@ define i64 @imm_cost_too_large_cost_of_4() {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2228259
- ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s64) = G_CONSTANT_FOLD_BARRIER [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -2228259
+ ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(i64) = G_CONSTANT_FOLD_BARRIER [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s64), [[GV3]](p0) :: (store (s64) into @var2_64)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV3]](p0) :: (store (i64) into @var2_64)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s64), [[GV4]](p0) :: (store (s64) into @var1_64)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV4]](p0) :: (store (i64) into @var1_64)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s64), [[GV5]](p0) :: (store (s64) into @var3_64)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[C4]](s64)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV5]](p0) :: (store (i64) into @var3_64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[C4]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, ptr @var1_64, align 4
@@ -235,37 +235,37 @@ define i64 @f64_imm_cost_too_high(double %a) {
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e-02
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e-02
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
- ; CHECK-NEXT: G_STORE [[C]](s64), [[GV3]](p0) :: (store (s64) into @var2_64)
+ ; CHECK-NEXT: G_STORE [[C]](f64), [[GV3]](p0) :: (store (f64) into @var2_64)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: G_STORE [[C]](s64), [[GV4]](p0) :: (store (s64) into @var1_64)
+ ; CHECK-NEXT: G_STORE [[C]](f64), [[GV4]](p0) :: (store (f64) into @var1_64)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: G_STORE [[C]](s64), [[GV5]](p0) :: (store (s64) into @var3_64)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[C4]](s64)
+ ; CHECK-NEXT: G_STORE [[C]](f64), [[GV5]](p0) :: (store (f64) into @var3_64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[C4]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, ptr @var1_64, align 4
@@ -291,40 +291,40 @@ define i64 @f64_imm_cheap(double %a) {
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; CHECK-NEXT: G_STORE [[C4]](s64), [[GV3]](p0) :: (store (s64) into @var2_64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: G_STORE [[C4]](f64), [[GV3]](p0) :: (store (f64) into @var2_64)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: G_STORE [[C5]](s64), [[GV4]](p0) :: (store (s64) into @var1_64)
+ ; CHECK-NEXT: G_STORE [[C5]](f64), [[GV4]](p0) :: (store (f64) into @var1_64)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; CHECK-NEXT: G_STORE [[C6]](s64), [[GV5]](p0) :: (store (s64) into @var3_64)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: G_STORE [[C6]](f64), [[GV5]](p0) :: (store (f64) into @var3_64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[C7]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, ptr @var1_64, align 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll b/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
index 4aaa58e8dab2e..9ff99dae65fa2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
@@ -9,8 +9,8 @@ define %zero @test(%zero %x, %zero %y) {
; CHECK: bb.1.b1:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_BRCOND [[DEF]](s1), %bb.3
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: G_BRCOND [[DEF]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.b2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
index acfbec0dd0ef2..0b533ff85fe86 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
@@ -73,10 +73,10 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C2]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C2]](i64)
; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)
; CHECK-NEXT: $d1 = COPY [[EVEC1]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
index 22d1ccc056eb4..d7690085ae693 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
@@ -43,10 +43,10 @@ body: |
; LOWER-NEXT: %r:_(s32) = COPY $w0
; LOWER-NEXT: %q:_(s32) = COPY $w1
; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(s32), [[C]](s64)
- ; LOWER-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(s32), [[C1]](s64)
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(s32), [[C]](i64)
+ ; LOWER-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(s32), [[C1]](i64)
; LOWER-NEXT: %build_vector:_(<2 x s32>) = COPY [[IVEC1]](<2 x s32>)
; LOWER-NEXT: $d0 = COPY %build_vector(<2 x s32>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
index 80eda3db6e04a..0474e7312f16c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
@@ -22,10 +22,10 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -52,10 +52,10 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -83,10 +83,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -115,10 +115,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -146,10 +146,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -204,10 +204,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -235,10 +235,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -266,10 +266,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -296,10 +296,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: %right:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%left:_(<4 x s32>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
index f11396ee6c330..3906bbe94c620 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
@@ -354,14 +354,14 @@ body: |
; CHECK-NEXT: %c:_(s32) = COPY $w2
; CHECK-NEXT: %d:_(s32) = COPY $w3
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane(s32), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane(s32), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](i64)
; CHECK-NEXT: %buildvec:_(<4 x s32>) = COPY [[IVEC3]](<4 x s32>)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %shuf:_(<4 x s32>) = G_DUPLANE32 %buildvec, [[C4]](s64)
@@ -397,24 +397,24 @@ body: |
; CHECK-NEXT: %c:_(s32) = COPY $w3
; CHECK-NEXT: %d:_(s32) = COPY $w4
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane_0(s32), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane_0(s32), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](i64)
; CHECK-NEXT: %buildvec0:_(<4 x s32>) = COPY [[IVEC3]](<4 x s32>)
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], %lane_1(s32), [[C4]](s64)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC4]], %b(s32), [[C5]](s64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC5]], %c(s32), [[C6]](s64)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC6]], %d(s32), [[C7]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], %lane_1(s32), [[C4]](i64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC4]], %b(s32), [[C5]](i64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC5]], %c(s32), [[C6]](i64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC6]], %d(s32), [[C7]](i64)
; CHECK-NEXT: %buildvec1:_(<4 x s32>) = COPY [[IVEC7]](<4 x s32>)
; CHECK-NEXT: %shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %buildvec0(<4 x s32>), %buildvec1, shufflemask(4, 4, 4, 4)
; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll b/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
index 4405c06ff0e23..35b321ff22ab1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
@@ -10,36 +10,38 @@ define <4 x ptr> @pr168872(<4 x ptr> %ptrs) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x i64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[C]](p0), [[C]](p0)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[BITCAST]](<2 x p0>), [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[BITCAST1]](<2 x p0>), [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BITCAST2]](<2 x p0>)
- ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BITCAST3]](<2 x p0>)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[BITCAST]](<2 x p0>), [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[BITCAST1]](<2 x p0>), [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BITCAST]](<2 x p0>)
+ ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BITCAST1]](<2 x p0>)
; CHECK-NEXT: [[PTRTOINT2:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
; CHECK-NEXT: [[PTRTOINT3:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT1]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT2]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT3]], [[XOR1]]
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[PTRTOINT]](<2 x s64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[PTRTOINT1]](<2 x s64>)
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[PTRTOINT2]](<2 x s64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[PTRTOINT3]](<2 x s64>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C1]](i64), [[C1]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[BITCAST2]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[BITCAST3]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[BITCAST4]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[BITCAST5]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x s64>)
; CHECK-NEXT: [[INTTOPTR1:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR1]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[INTTOPTR]](<2 x p0>)
- ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[INTTOPTR1]](<2 x p0>)
- ; CHECK-NEXT: $q0 = COPY [[BITCAST4]](<2 x s64>)
- ; CHECK-NEXT: $q1 = COPY [[BITCAST5]](<2 x s64>)
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[INTTOPTR]](<2 x p0>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[INTTOPTR1]](<2 x p0>)
+ ; CHECK-NEXT: $q0 = COPY [[BITCAST6]](<2 x i64>)
+ ; CHECK-NEXT: $q1 = COPY [[BITCAST7]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
entry:
%cmp = icmp ugt <4 x ptr> %ptrs, zeroinitializer
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
index 34dbad5a94977..cd3690776df01 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
@@ -41,7 +41,7 @@ body: |
%0:gpr(s32) = G_IMPLICIT_DEF
%4:gpr(p0) = G_IMPLICIT_DEF
- %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
+ %8:fpr(f32) = G_FCONSTANT float 0x7FF8000000000000
bb.1:
successors: %bb.2(0x80000000)
@@ -54,7 +54,7 @@ body: |
successors: %bb.2(0x80000000)
%3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
- %5:fpr(s16) = G_FPTRUNC %8(s32)
+ %5:fpr(f16) = G_FPTRUNC %8(s32)
G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)
G_BR %bb.2
@@ -100,7 +100,7 @@ body: |
%0:gpr(s32) = G_IMPLICIT_DEF
%4:gpr(p0) = G_IMPLICIT_DEF
- %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
+ %8:fpr(f32) = G_FCONSTANT float 0x7FF8000000000000
bb.1:
successors: %bb.2(0x80000000)
@@ -113,7 +113,7 @@ body: |
successors: %bb.2(0x80000000)
%3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
- %5:fpr(s16) = G_FPTRUNC %8(s32)
+ %5:fpr(f16) = G_FPTRUNC %8(s32)
G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)
G_BR %bb.2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
index 496e01e8f39c4..88ecbd6bb9341 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
@@ -204,7 +204,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -257,7 +257,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
index 06c221adee123..16ab28f4bd46a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
@@ -204,7 +204,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -257,7 +257,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll b/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
index 1758856a9722a..8a47bd8a062a4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
@@ -6,11 +6,12 @@ define <1 x float> @ret_v1f32(<1 x float> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[DEF]](s32)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[UV]](f32), [[DEF]](f32)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x float> %v
}
@@ -42,11 +43,11 @@ define <1 x i16> @ret_v1i16(<1 x i16> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i16>) = G_BUILD_VECTOR [[UV]](i16), [[DEF]](i16), [[DEF]](i16), [[DEF]](i16)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x i16> %v
}
@@ -56,11 +57,11 @@ define <1 x i8> @ret_v1i8(<1 x i8> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[UV]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<8 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8), [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[COPY]](<8 x i8>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[UV]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x i8> %v
}
@@ -70,11 +71,11 @@ define <1 x i32> @ret_v1i32(<1 x i32> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[DEF]](s32)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[UV]](i32), [[DEF]](i32)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x i32> %v
}
@@ -84,8 +85,8 @@ define <1 x i64> @ret_v1i64(<1 x i64> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $d0
+ ; CHECK-NEXT: $d0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x i64> %v
}
@@ -94,11 +95,11 @@ define <1 x i1> @ret_v1i1(<1 x i1> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret <1 x i1> %v
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll b/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
index 04734caf01ef7..241a71105f115 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
@@ -8,9 +8,9 @@ define <4 x i1> @ret_v4i1(ptr %v) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s1>) = G_LOAD [[COPY]](p0) :: (load (<4 x s1>) from %ir.v)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[LOAD]](<4 x s1>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<4 x s16>)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x i1>) = G_LOAD [[COPY]](p0) :: (load (<4 x i1>) from %ir.v)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x i16>) = G_ANYEXT [[LOAD]](<4 x i1>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%v2 = load <4 x i1>, ptr %v
ret <4 x i1> %v2
@@ -21,12 +21,12 @@ define <1 x i12> @ret_v1i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%a = insertelement <1 x i12> poison, i12 %v1, i32 0
ret <1 x i12> %a
@@ -37,17 +37,17 @@ define <2 x i12> @ret_v2i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[IVEC1]](<2 x s12>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i32>) = G_ANYEXT [[IVEC1]](<2 x i12>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%a = insertelement <2 x i12> poison, i12 %v1, i32 0
%b = insertelement <2 x i12> %a, i12 %v2, i32 1
@@ -59,24 +59,24 @@ define <3 x i12> @ret_v3i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s12), [[UV1:%[0-9]+]]:_(s12), [[UV2:%[0-9]+]]:_(s12) = G_UNMERGE_VALUES [[IVEC2]](<3 x s12>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s12)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s12)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i12), [[UV1:%[0-9]+]]:_(i12), [[UV2:%[0-9]+]]:_(i12) = G_UNMERGE_VALUES [[IVEC2]](<3 x i12>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i12)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[UV1]](i12)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[UV2]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2
%a = insertelement <3 x i12> poison, i12 %v1, i32 0
%b = insertelement <3 x i12> %a, i12 %v2, i32 1
@@ -89,21 +89,21 @@ define <4 x i12> @ret_v4i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[IVEC3]](<4 x s12>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x i16>) = G_ANYEXT [[IVEC3]](<4 x i12>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%a = insertelement <4 x i12> poison, i12 %v1, i32 0
%b = insertelement <4 x i12> %a, i12 %v2, i32 1
@@ -117,32 +117,32 @@ define <5 x i12> @ret_v5i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<5 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s12), [[UV1:%[0-9]+]]:_(s12), [[UV2:%[0-9]+]]:_(s12), [[UV3:%[0-9]+]]:_(s12), [[UV4:%[0-9]+]]:_(s12) = G_UNMERGE_VALUES [[IVEC4]](<5 x s12>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s12)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s12)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s12)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s12)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
- ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](s32)
- ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<5 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i12), [[UV1:%[0-9]+]]:_(i12), [[UV2:%[0-9]+]]:_(i12), [[UV3:%[0-9]+]]:_(i12), [[UV4:%[0-9]+]]:_(i12) = G_UNMERGE_VALUES [[IVEC4]](<5 x i12>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i12)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[UV1]](i12)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[UV2]](i12)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[UV3]](i12)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[UV4]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](i32)
+ ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](i32)
+ ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4
%a = insertelement <5 x i12> poison, i12 %v2, i32 0
%b = insertelement <5 x i12> %a, i12 %v1, i32 1
@@ -157,36 +157,36 @@ define <6 x i12> @ret_v6i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<6 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](s12), [[C5]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s12), [[UV1:%[0-9]+]]:_(s12), [[UV2:%[0-9]+]]:_(s12), [[UV3:%[0-9]+]]:_(s12), [[UV4:%[0-9]+]]:_(s12), [[UV5:%[0-9]+]]:_(s12) = G_UNMERGE_VALUES [[IVEC5]](<6 x s12>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s12)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s12)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s12)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s12)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s12)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
- ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](s32)
- ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](s32)
- ; CHECK-NEXT: $w5 = COPY [[ANYEXT5]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<6 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](i12), [[C5]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i12), [[UV1:%[0-9]+]]:_(i12), [[UV2:%[0-9]+]]:_(i12), [[UV3:%[0-9]+]]:_(i12), [[UV4:%[0-9]+]]:_(i12), [[UV5:%[0-9]+]]:_(i12) = G_UNMERGE_VALUES [[IVEC5]](<6 x i12>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i12)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[UV1]](i12)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[UV2]](i12)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[UV3]](i12)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[UV4]](i12)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[UV5]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](i32)
+ ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](i32)
+ ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](i32)
+ ; CHECK-NEXT: $w5 = COPY [[ANYEXT5]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5
%a = insertelement <6 x i12> poison, i12 %v2, i32 0
%b = insertelement <6 x i12> %a, i12 %v1, i32 1
@@ -202,40 +202,40 @@ define <7 x i12> @ret_v7i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<7 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](s12), [[C5]](s64)
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](s12), [[C6]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s12), [[UV1:%[0-9]+]]:_(s12), [[UV2:%[0-9]+]]:_(s12), [[UV3:%[0-9]+]]:_(s12), [[UV4:%[0-9]+]]:_(s12), [[UV5:%[0-9]+]]:_(s12), [[UV6:%[0-9]+]]:_(s12) = G_UNMERGE_VALUES [[IVEC6]](<7 x s12>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s12)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s12)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s12)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s12)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s12)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s12)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
- ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](s32)
- ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](s32)
- ; CHECK-NEXT: $w5 = COPY [[ANYEXT5]](s32)
- ; CHECK-NEXT: $w6 = COPY [[ANYEXT6]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<7 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](i12), [[C5]](i64)
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](i12), [[C6]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i12), [[UV1:%[0-9]+]]:_(i12), [[UV2:%[0-9]+]]:_(i12), [[UV3:%[0-9]+]]:_(i12), [[UV4:%[0-9]+]]:_(i12), [[UV5:%[0-9]+]]:_(i12), [[UV6:%[0-9]+]]:_(i12) = G_UNMERGE_VALUES [[IVEC6]](<7 x i12>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i12)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[UV1]](i12)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[UV2]](i12)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[UV3]](i12)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[UV4]](i12)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[UV5]](i12)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[UV6]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](i32)
+ ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](i32)
+ ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](i32)
+ ; CHECK-NEXT: $w5 = COPY [[ANYEXT5]](i32)
+ ; CHECK-NEXT: $w6 = COPY [[ANYEXT6]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5, implicit $w6
%a = insertelement <7 x i12> poison, i12 %v2, i32 0
%b = insertelement <7 x i12> %a, i12 %v1, i32 1
@@ -252,29 +252,29 @@ define <8 x i12> @ret_v8i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](s12), [[C5]](s64)
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](s12), [[C6]](s64)
- ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC6]], [[TRUNC]](s12), [[C7]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[IVEC7]](<8 x s12>)
- ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](i12), [[C5]](i64)
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](i12), [[C6]](i64)
+ ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC6]], [[TRUNC]](i12), [[C7]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x i16>) = G_ANYEXT [[IVEC7]](<8 x i12>)
+ ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%a = insertelement <8 x i12> poison, i12 %v2, i32 0
%b = insertelement <8 x i12> %a, i12 %v1, i32 1
@@ -293,36 +293,36 @@ define <12 x i12> @ret_v12i12(i12 %v1, i12 %v2) {
; CHECK-NEXT: liveins: $w0, $w1, $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY2]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<12 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](s12), [[C5]](s64)
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](s12), [[C6]](s64)
- ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC6]], [[TRUNC]](s12), [[C7]](s64)
- ; CHECK-NEXT: [[IVEC8:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC7]], [[TRUNC]](s12), [[C8]](s64)
- ; CHECK-NEXT: [[IVEC9:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC8]], [[TRUNC]](s12), [[C9]](s64)
- ; CHECK-NEXT: [[IVEC10:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC9]], [[TRUNC]](s12), [[C10]](s64)
- ; CHECK-NEXT: [[IVEC11:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC10]], [[TRUNC]](s12), [[C11]](s64)
- ; CHECK-NEXT: G_STORE [[IVEC11]](<12 x s12>), [[COPY]](p0) :: (store (<12 x s12>), align 32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY2]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<12 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 9
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 10
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 11
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](i12), [[C5]](i64)
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](i12), [[C6]](i64)
+ ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC6]], [[TRUNC]](i12), [[C7]](i64)
+ ; CHECK-NEXT: [[IVEC8:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC7]], [[TRUNC]](i12), [[C8]](i64)
+ ; CHECK-NEXT: [[IVEC9:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC8]], [[TRUNC]](i12), [[C9]](i64)
+ ; CHECK-NEXT: [[IVEC10:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC9]], [[TRUNC]](i12), [[C10]](i64)
+ ; CHECK-NEXT: [[IVEC11:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC10]], [[TRUNC]](i12), [[C11]](i64)
+ ; CHECK-NEXT: G_STORE [[IVEC11]](<12 x i12>), [[COPY]](p0) :: (store (<12 x i12>), align 32)
; CHECK-NEXT: RET_ReallyLR
%a = insertelement <12 x i12> poison, i12 %v2, i32 0
%b = insertelement <12 x i12> %a, i12 %v1, i32 1
@@ -345,18 +345,18 @@ define <1 x i100> @ret_v1i100(i100 %v1, i100 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%a = insertelement <1 x i100> poison, i100 %v1, i32 0
ret <1 x i100> %a
@@ -367,25 +367,25 @@ define <2 x i100> @ret_v2i100(i100 %v1, i100 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s100>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s100), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s100), [[C1]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s128>) = G_ANYEXT [[IVEC1]](<2 x s100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](<2 x s128>)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i100>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i100), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s128>) = G_ANYEXT [[IVEC1]](<2 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<2 x s128>)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3
%a = insertelement <2 x i100> poison, i100 %v1, i32 0
%b = insertelement <2 x i100> %a, i100 %v2, i32 1
@@ -397,29 +397,29 @@ define <3 x i100> @ret_v3i100(i100 %v1, i100 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x s100>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s100), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s100), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](s100), [[C2]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<3 x s128>) = G_ANYEXT [[IVEC2]](<3 x s100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](<3 x s128>)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
- ; CHECK-NEXT: $x4 = COPY [[UV4]](s64)
- ; CHECK-NEXT: $x5 = COPY [[UV5]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x i100>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i100), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](i100), [[C2]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<3 x s128>) = G_ANYEXT [[IVEC2]](<3 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64), [[UV4:%[0-9]+]]:_(i64), [[UV5:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<3 x s128>)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
+ ; CHECK-NEXT: $x4 = COPY [[UV4]](i64)
+ ; CHECK-NEXT: $x5 = COPY [[UV5]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5
%a = insertelement <3 x i100> poison, i100 %v1, i32 0
%b = insertelement <3 x i100> %a, i100 %v2, i32 1
@@ -432,33 +432,33 @@ define <4 x i100> @ret_v4i100(i100 %v1, i100 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s100>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s100), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s100), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s100), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s100>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s100), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s128>) = G_ANYEXT [[IVEC3]](<4 x s100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](<4 x s128>)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
- ; CHECK-NEXT: $x4 = COPY [[UV4]](s64)
- ; CHECK-NEXT: $x5 = COPY [[UV5]](s64)
- ; CHECK-NEXT: $x6 = COPY [[UV6]](s64)
- ; CHECK-NEXT: $x7 = COPY [[UV7]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i100>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i100), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i100), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i100), [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s128>) = G_ANYEXT [[IVEC3]](<4 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64), [[UV4:%[0-9]+]]:_(i64), [[UV5:%[0-9]+]]:_(i64), [[UV6:%[0-9]+]]:_(i64), [[UV7:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<4 x s128>)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
+ ; CHECK-NEXT: $x4 = COPY [[UV4]](i64)
+ ; CHECK-NEXT: $x5 = COPY [[UV5]](i64)
+ ; CHECK-NEXT: $x6 = COPY [[UV6]](i64)
+ ; CHECK-NEXT: $x7 = COPY [[UV7]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7
%a = insertelement <4 x i100> poison, i100 %v1, i32 0
%b = insertelement <4 x i100> %a, i100 %v2, i32 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
index 41231eae78195..9f43e1a1ab42a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -917,10 +917,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FADDSrr]]
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = G_FADD %0, %1
- $s0 = COPY %2(s32)
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = G_FADD %0, %1
+ $s0 = COPY %2(f32)
...
---
@@ -944,10 +944,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FADDDrr]]
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = G_FADD %0, %1
- $d0 = COPY %2(s64)
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = G_FADD %0, %1
+ $d0 = COPY %2(f64)
...
---
@@ -971,10 +971,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FSUBSrr]]
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = G_FSUB %0, %1
- $s0 = COPY %2(s32)
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = G_FSUB %0, %1
+ $s0 = COPY %2(f32)
...
---
@@ -998,10 +998,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FSUBDrr]]
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = G_FSUB %0, %1
- $d0 = COPY %2(s64)
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = G_FSUB %0, %1
+ $d0 = COPY %2(f64)
...
---
@@ -1025,10 +1025,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FMULSrr]]
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = G_FMUL %0, %1
- $s0 = COPY %2(s32)
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = G_FMUL %0, %1
+ $s0 = COPY %2(f32)
...
---
@@ -1052,10 +1052,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FMULDrr]]
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = G_FMUL %0, %1
- $d0 = COPY %2(s64)
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = G_FMUL %0, %1
+ $d0 = COPY %2(f64)
...
---
@@ -1079,10 +1079,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FDIVSrr]]
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = G_FDIV %0, %1
- $s0 = COPY %2(s32)
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = G_FDIV %0, %1
+ $s0 = COPY %2(f32)
...
---
@@ -1106,10 +1106,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FDIVDrr]]
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = G_FDIV %0, %1
- $d0 = COPY %2(s64)
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = G_FDIV %0, %1
+ $d0 = COPY %2(f64)
...
---
name: add_v8i16
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
index c0150ae9f73f7..d6adac923f2d5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
@@ -15,9 +15,9 @@ body: |
; CHECK-LABEL: name: ceil_float
; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FRINTPSr %{{[0-9]+}}
liveins: $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FCEIL %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FCEIL %0
+ $s0 = COPY %1(f32)
...
---
@@ -33,9 +33,9 @@ body: |
; CHECK-LABEL: name: ceil_double
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPDr %{{[0-9]+}}
liveins: $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FCEIL %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FCEIL %0
+ $d0 = COPY %1(f64)
...
---
@@ -51,9 +51,9 @@ body: |
; CHECK-LABEL: name: ceil_v2f32
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPv2f32 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FCEIL %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FCEIL %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: ceil_v4f32
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv4f32 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FCEIL %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FCEIL %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK-LABEL: name: ceil_v2f64
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv2f64 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FCEIL %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FCEIL %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -105,9 +105,9 @@ body: |
; CHECK-LABEL: name: ceil_v4f16
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPv4f16 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FCEIL %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FCEIL %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -123,8 +123,8 @@ body: |
; CHECK-LABEL: name: ceil_v8f16
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv8f16 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FCEIL %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FCEIL %0
+ $q0 = COPY %1(<8 x f16>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index 417ac91113f2c..1cd5742423599 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -140,8 +140,8 @@ body: |
; CHECK-LABEL: name: fconst_s32
; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 12
; CHECK-NEXT: $s0 = COPY [[FMOVSi]]
- %0(s32) = G_FCONSTANT float 3.5
- $s0 = COPY %0(s32)
+ %0(f32) = G_FCONSTANT float 3.5
+ $s0 = COPY %0(f32)
...
---
@@ -156,8 +156,8 @@ body: |
; CHECK-LABEL: name: fconst_s64
; CHECK: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
; CHECK-NEXT: $d0 = COPY [[FMOVDi]]
- %0(s64) = G_FCONSTANT double 1.0
- $d0 = COPY %0(s64)
+ %0(f64) = G_FCONSTANT double 1.0
+ $d0 = COPY %0(f64)
...
---
@@ -172,8 +172,8 @@ body: |
; CHECK-LABEL: name: fconst_s32_0
; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
; CHECK-NEXT: $s0 = COPY [[FMOVS0_]]
- %0(s32) = G_FCONSTANT float 0.0
- $s0 = COPY %0(s32)
+ %0(f32) = G_FCONSTANT float 0.0
+ $s0 = COPY %0(f32)
...
---
@@ -188,8 +188,8 @@ body: |
; CHECK-LABEL: name: fconst_s64_0
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
; CHECK-NEXT: $x0 = COPY [[FMOVD0_]]
- %0(s64) = G_FCONSTANT double 0.0
- $x0 = COPY %0(s64)
+ %0(f64) = G_FCONSTANT double 0.0
+ $x0 = COPY %0(f64)
...
---
name: optnone_i64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
index cf2bab78fe5a6..1f89cf4b158cb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
@@ -19,9 +19,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv4i32gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<4 x s32>) = G_DUP %copy(s32)
- $q0 = COPY %dup(<4 x s32>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<4 x i32>) = G_DUP %copy(i32)
+ $q0 = COPY %dup(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -41,9 +41,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv2i64gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s64) = COPY $x0
- %dup:fpr(<2 x s64>) = G_DUP %copy(s64)
- $q0 = COPY %dup(<2 x s64>)
+ %copy:gpr(i64) = COPY $x0
+ %dup:fpr(<2 x i64>) = G_DUP %copy(i64)
+ $q0 = COPY %dup(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -63,9 +63,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv2i32gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<2 x s32>) = G_DUP %copy(s32)
- $d0 = COPY %dup(<2 x s32>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<2 x i32>) = G_DUP %copy(i32)
+ $d0 = COPY %dup(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -88,9 +88,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(s32) = COPY $s0
- %dup:fpr(<4 x s32>) = G_DUP %copy(s32)
- $q0 = COPY %dup(<4 x s32>)
+ %copy:fpr(i32) = COPY $s0
+ %dup:fpr(<4 x i32>) = G_DUP %copy(i32)
+ $q0 = COPY %dup(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -112,9 +112,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(s64) = COPY $d0
- %dup:fpr(<2 x s64>) = G_DUP %copy(s64)
- $q0 = COPY %dup(<2 x s64>)
+ %copy:fpr(i64) = COPY $d0
+ %dup:fpr(<2 x i64>) = G_DUP %copy(i64)
+ $q0 = COPY %dup(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -136,9 +136,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(s32) = COPY $s0
- %dup:fpr(<2 x s32>) = G_DUP %copy(s32)
- $d0 = COPY %dup(<2 x s32>)
+ %copy:fpr(i32) = COPY $s0
+ %dup:fpr(<2 x i32>) = G_DUP %copy(i32)
+ $d0 = COPY %dup(<2 x i32>)
RET_ReallyLR implicit $d0
@@ -161,9 +161,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(s16) = COPY $h0
- %dup:fpr(<4 x s16>) = G_DUP %copy(s16)
- $d0 = COPY %dup(<4 x s16>)
+ %copy:fpr(i16) = COPY $h0
+ %dup:fpr(<4 x i16>) = G_DUP %copy(i16)
+ $d0 = COPY %dup(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -182,9 +182,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<4 x s16>) = G_DUP %copy(s32)
- $d0 = COPY %dup(<4 x s16>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<4 x i16>) = G_DUP %copy(i32)
+ $d0 = COPY %dup(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -206,9 +206,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(s16) = COPY $h0
- %dup:fpr(<8 x s16>) = G_DUP %copy(s16)
- $q0 = COPY %dup(<8 x s16>)
+ %copy:fpr(i16) = COPY $h0
+ %dup:fpr(<8 x i16>) = G_DUP %copy(i16)
+ $q0 = COPY %dup(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -228,9 +228,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<8 x s16>) = G_DUP %copy(s32)
- $q0 = COPY %dup(<8 x s16>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<8 x i16>) = G_DUP %copy(i32)
+ $q0 = COPY %dup(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -250,10 +250,10 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %trunc:gpr(s16) = G_TRUNC %copy
- %dup:fpr(<8 x s16>) = G_DUP %trunc(s16)
- $q0 = COPY %dup(<8 x s16>)
+ %copy:gpr(i32) = COPY $w0
+ %trunc:gpr(i16) = G_TRUNC %copy
+ %dup:fpr(<8 x i16>) = G_DUP %trunc(i16)
+ $q0 = COPY %dup(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -273,10 +273,10 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %trunc:gpr(s16) = G_TRUNC %copy
- %dup:fpr(<4 x s16>) = G_DUP %trunc(s16)
- $d0 = COPY %dup(<4 x s16>)
+ %copy:gpr(i32) = COPY $w0
+ %trunc:gpr(i16) = G_TRUNC %copy
+ %dup:fpr(<4 x i16>) = G_DUP %trunc(i16)
+ $d0 = COPY %dup(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -296,9 +296,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<8 x s8>) = G_DUP %copy(s32)
- $d0 = COPY %dup(<8 x s8>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<8 x i8>) = G_DUP %copy(i32)
+ $d0 = COPY %dup(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -318,10 +318,10 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %trunc:gpr(s8) = G_TRUNC %copy(s32)
- %dup:fpr(<8 x s8>) = G_DUP %trunc(s8)
- $d0 = COPY %dup(<8 x s8>)
+ %copy:gpr(i32) = COPY $w0
+ %trunc:gpr(i8) = G_TRUNC %copy(i32)
+ %dup:fpr(<8 x i8>) = G_DUP %trunc(i8)
+ $d0 = COPY %dup(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -341,9 +341,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<16 x s8>) = G_DUP %copy(s32)
- $q0 = COPY %dup(<16 x s8>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<16 x i8>) = G_DUP %copy(i32)
+ $q0 = COPY %dup(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -362,10 +362,10 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %trunc:gpr(s8) = G_TRUNC %copy
- %dup:fpr(<16 x s8>) = G_DUP %trunc(s8)
- $q0 = COPY %dup(<16 x s8>)
+ %copy:gpr(i32) = COPY $w0
+ %trunc:gpr(i8) = G_TRUNC %copy
+ %dup:fpr(<16 x i8>) = G_DUP %trunc(i8)
+ $q0 = COPY %dup(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -408,9 +408,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = MOVIv4i32 3, 0
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %cst:gpr(s32) = G_CONSTANT i32 3
- %dup:fpr(<4 x s32>) = G_DUP %cst(s32)
- $q0 = COPY %dup(<4 x s32>)
+ %cst:gpr(i32) = G_CONSTANT i32 3
+ %dup:fpr(<4 x i32>) = G_DUP %cst(i32)
+ $q0 = COPY %dup(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -428,9 +428,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = MOVIv8b_ns 3
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %cst:gpr(s8) = G_CONSTANT i8 3
- %dup:fpr(<8 x s8>) = G_DUP %cst(s8)
- $d0 = COPY %dup(<8 x s8>)
+ %cst:gpr(i8) = G_CONSTANT i8 3
+ %dup:fpr(<8 x i8>) = G_DUP %cst(i8)
+ $d0 = COPY %dup(<8 x i8>)
RET_ReallyLR implicit $d0
...
---
@@ -444,7 +444,9 @@ body: |
; CHECK-LABEL: name: cst_v2p0
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %cst:gpr64 = MOVi64imm 3
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
+ ; CHECK-NEXT: %cst:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %cst
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
@@ -466,9 +468,9 @@ body: |
; CHECK: %dup:fpr64 = MOVIv4i16 3, 0
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %cst:gpr(s32) = G_CONSTANT i32 3
- %dup:fpr(<4 x s16>) = G_DUP %cst(s32)
- $d0 = COPY %dup(<4 x s16>)
+ %cst:gpr(i32) = G_CONSTANT i32 3
+ %dup:fpr(<4 x i16>) = G_DUP %cst(i32)
+ $d0 = COPY %dup(<4 x i16>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fabs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fabs.mir
index e7d74cc4baa60..f538431d9052a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fabs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fabs.mir
@@ -15,9 +15,9 @@ body: |
; CHECK-LABEL: name: fabs_float
; CHECK: %{{[0-9]+}}:fpr32 = FABSSr %{{[0-9]+}}
liveins: $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FABS %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FABS %0
+ $s0 = COPY %1(f32)
...
---
@@ -33,9 +33,9 @@ body: |
; CHECK-LABEL: name: fabs_double
; CHECK: %{{[0-9]+}}:fpr64 = FABSDr %{{[0-9]+}}
liveins: $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FABS %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FABS %0
+ $d0 = COPY %1(f64)
...
---
@@ -51,9 +51,9 @@ body: |
; CHECK-LABEL: name: fabs_v2f32
; CHECK: %{{[0-9]+}}:fpr64 = FABSv2f32 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FABS %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FABS %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: fabs_v4f32
; CHECK: %{{[0-9]+}}:fpr128 = FABSv4f32 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FABS %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FABS %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK-LABEL: name: fabs_v2f64
; CHECK: %{{[0-9]+}}:fpr128 = FABSv2f64 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FABS %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FABS %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -105,9 +105,9 @@ body: |
; CHECK-LABEL: name: fabs_v4f16
; CHECK: %{{[0-9]+}}:fpr64 = FABSv4f16 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FABS %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FABS %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -123,8 +123,8 @@ body: |
; CHECK-LABEL: name: fabs_v8f16
; CHECK: %{{[0-9]+}}:fpr128 = FABSv8f16 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FABS %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FABS %0
+ $q0 = COPY %1(<8 x f16>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
index 20a37f2573569..f3004fb652a7a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
@@ -21,13 +21,13 @@ body: |
; CHECK-NEXT: [[FADDPv2i64p:%[0-9]+]]:fpr64 = nofpexcept FADDPv2i64p [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FADDPv2i64p]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %6:gpr(s64) = G_CONSTANT i64 0
- %7:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %6(s64)
- %8:gpr(s64) = G_CONSTANT i64 1
- %9:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %8(s64)
- %4:fpr(s64) = G_FADD %7, %9
- $d0 = COPY %4(s64)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %6:gpr(i64) = G_CONSTANT i64 0
+ %7:fpr(f64) = G_EXTRACT_VECTOR_ELT %0(<2 x f64>), %6(i64)
+ %8:gpr(i64) = G_CONSTANT i64 1
+ %9:fpr(f64) = G_EXTRACT_VECTOR_ELT %0(<2 x f64>), %8(i64)
+ %4:fpr(f64) = G_FADD %7, %9
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -52,13 +52,13 @@ body: |
; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nofpexcept FADDPv2i32p [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(<2 x s32>) = COPY $d0
- %6:gpr(s64) = G_CONSTANT i64 0
- %7:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %6(s64)
- %8:gpr(s64) = G_CONSTANT i64 1
- %9:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s64)
- %4:fpr(s32) = G_FADD %7, %9
- $s0 = COPY %4(s32)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %6:gpr(i64) = G_CONSTANT i64 0
+ %7:fpr(f32) = G_EXTRACT_VECTOR_ELT %0(<2 x f32>), %6(i64)
+ %8:gpr(i64) = G_CONSTANT i64 1
+ %9:fpr(f32) = G_EXTRACT_VECTOR_ELT %0(<2 x f32>), %8(i64)
+ %4:fpr(f32) = G_FADD %7, %9
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
index 62d55a270b5e2..e2d8dfa63abeb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
@@ -50,11 +50,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 1.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
- $s0 = COPY %3(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 1.000000e+00
+ %3:gpr(f32) = G_FCMP floatpred(oeq), %0(f32), %2
+ $s0 = COPY %3(f32)
RET_ReallyLR implicit $s0
...
@@ -78,11 +78,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 1.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
- $s0 = COPY %3(s32)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 1.000000e+00
+ %3:gpr(i32) = G_FCMP floatpred(oeq), %0(f64), %2
+ $s0 = COPY %3(i32)
RET_ReallyLR implicit $s0
@@ -105,11 +105,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
- $s0 = COPY %3(s32)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %3:gpr(i32) = G_FCMP floatpred(oeq), %0(f64), %2
+ $s0 = COPY %3(i32)
RET_ReallyLR implicit $s0
...
@@ -131,11 +131,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %0
- $s0 = COPY %3(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %3:gpr(i32) = G_FCMP floatpred(oeq), %2(f32), %0
+ $s0 = COPY %3(i32)
RET_ReallyLR implicit $s0
...
@@ -158,11 +158,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(olt), %2(s32), %0
- $s0 = COPY %3(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %3:gpr(i32) = G_FCMP floatpred(olt), %2(f32), %0
+ $s0 = COPY %3(i32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
index af2478393f3f2..360369416191b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
@@ -15,9 +15,9 @@ body: |
; CHECK-LABEL: name: floor_float
; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FRINTMSr %{{[0-9]+}}
liveins: $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FFLOOR %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FFLOOR %0
+ $s0 = COPY %1(f32)
...
---
@@ -33,9 +33,9 @@ body: |
; CHECK-LABEL: name: floor_double
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMDr %{{[0-9]+}}
liveins: $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FFLOOR %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FFLOOR %0
+ $d0 = COPY %1(f64)
...
---
@@ -51,9 +51,9 @@ body: |
; CHECK-LABEL: name: floor_v2f32
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMv2f32 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FFLOOR %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FFLOOR %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: floor_v4f32
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv4f32 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FFLOOR %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FFLOOR %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK-LABEL: name: floor_v2f64
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv2f64 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FFLOOR %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FFLOOR %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -105,9 +105,9 @@ body: |
; CHECK-LABEL: name: floor_v4f16
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMv4f16 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FFLOOR %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FFLOOR %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -123,8 +123,8 @@ body: |
; CHECK-LABEL: name: floor_v8f16
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv8f16 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FFLOOR %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FFLOOR %0
+ $q0 = COPY %1(<8 x f16>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
index fb04eff54e041..072346df06bc3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
@@ -19,10 +19,10 @@ body: |
; CHECK-NEXT: %select_me:fpr16 = nofpexcept FMAXHrr %a, %b, implicit $fpcr
; CHECK-NEXT: $h0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %a:fpr(s16) = COPY $h0
- %b:fpr(s16) = COPY $h1
- %select_me:fpr(s16) = G_FMAXIMUM %a, %b
- $h0 = COPY %select_me(s16)
+ %a:fpr(f16) = COPY $h0
+ %b:fpr(f16) = COPY $h1
+ %select_me:fpr(f16) = G_FMAXIMUM %a, %b
+ $h0 = COPY %select_me(f16)
RET_ReallyLR implicit $h0
...
@@ -43,10 +43,10 @@ body: |
; CHECK-NEXT: %select_me:fpr32 = nofpexcept FMAXSrr %a, %b, implicit $fpcr
; CHECK-NEXT: $s0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %a:fpr(s32) = COPY $s0
- %b:fpr(s32) = COPY $s1
- %select_me:fpr(s32) = G_FMAXIMUM %a, %b
- $s0 = COPY %select_me(s32)
+ %a:fpr(f32) = COPY $s0
+ %b:fpr(f32) = COPY $s1
+ %select_me:fpr(f32) = G_FMAXIMUM %a, %b
+ $s0 = COPY %select_me(f32)
RET_ReallyLR implicit $s0
...
@@ -67,8 +67,8 @@ body: |
; CHECK-NEXT: %select_me:fpr64 = nofpexcept FMAXDrr %a, %b, implicit $fpcr
; CHECK-NEXT: $d0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:fpr(s64) = COPY $d0
- %b:fpr(s64) = COPY $d1
- %select_me:fpr(s64) = G_FMAXIMUM %a, %b
- $d0 = COPY %select_me(s64)
+ %a:fpr(f64) = COPY $d0
+ %b:fpr(f64) = COPY $d1
+ %select_me:fpr(f64) = G_FMAXIMUM %a, %b
+ $d0 = COPY %select_me(f64)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
index 457a6ef1d123f..453e8669864d5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
@@ -19,10 +19,10 @@ body: |
; CHECK-NEXT: %select_me:fpr16 = nofpexcept FMINHrr %a, %b, implicit $fpcr
; CHECK-NEXT: $h0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %a:fpr(s16) = COPY $h0
- %b:fpr(s16) = COPY $h1
- %select_me:fpr(s16) = G_FMINIMUM %a, %b
- $h0 = COPY %select_me(s16)
+ %a:fpr(f16) = COPY $h0
+ %b:fpr(f16) = COPY $h1
+ %select_me:fpr(f16) = G_FMINIMUM %a, %b
+ $h0 = COPY %select_me(f16)
RET_ReallyLR implicit $h0
...
@@ -43,10 +43,10 @@ body: |
; CHECK-NEXT: %select_me:fpr32 = nofpexcept FMINSrr %a, %b, implicit $fpcr
; CHECK-NEXT: $s0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %a:fpr(s32) = COPY $s0
- %b:fpr(s32) = COPY $s1
- %select_me:fpr(s32) = G_FMINIMUM %a, %b
- $s0 = COPY %select_me(s32)
+ %a:fpr(f32) = COPY $s0
+ %b:fpr(f32) = COPY $s1
+ %select_me:fpr(f32) = G_FMINIMUM %a, %b
+ $s0 = COPY %select_me(f32)
RET_ReallyLR implicit $s0
...
@@ -67,8 +67,8 @@ body: |
; CHECK-NEXT: %select_me:fpr64 = nofpexcept FMINDrr %a, %b, implicit $fpcr
; CHECK-NEXT: $d0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:fpr(s64) = COPY $d0
- %b:fpr(s64) = COPY $d1
- %select_me:fpr(s64) = G_FMINIMUM %a, %b
- $d0 = COPY %select_me(s64)
+ %a:fpr(f64) = COPY $d0
+ %b:fpr(f64) = COPY $d1
+ %select_me:fpr(f64) = G_FMINIMUM %a, %b
+ $d0 = COPY %select_me(f64)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
index 491835a5079d7..5bee4c06670aa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
@@ -21,21 +21,21 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x s32>), align 4)
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x f32>), align 4)
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRDui]], %subreg.dsub
; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = nofpexcept FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0, implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FMULv2i32_indexed]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
+ %0:fpr(<2 x f32>) = COPY $d0
%1:gpr(p0) = COPY $x0
- %2:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>), align 4)
- %9:fpr(<2 x s32>) = G_IMPLICIT_DEF
- %10:fpr(<4 x s32>) = G_CONCAT_VECTORS %2(<2 x s32>), %9(<2 x s32>)
- %8:gpr(s64) = G_CONSTANT i64 0
- %5:fpr(<2 x s32>) = G_DUPLANE32 %10, %8(s64)
- %7:fpr(<2 x s32>) = G_FMUL %0, %5
- $d0 = COPY %7(<2 x s32>)
+ %2:fpr(<2 x f32>) = G_LOAD %1(p0) :: (load (<2 x f32>), align 4)
+ %9:fpr(<2 x f32>) = G_IMPLICIT_DEF
+ %10:fpr(<4 x f32>) = G_CONCAT_VECTORS %2(<2 x f32>), %9(<2 x f32>)
+ %8:gpr(i64) = G_CONSTANT i64 0
+ %5:fpr(<2 x f32>) = G_DUPLANE32 %10, %8(i64)
+ %7:fpr(<2 x f32>) = G_FMUL %0, %5
+ $d0 = COPY %7(<2 x f32>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
index a58492114003a..9bc66bbdcb6b0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FCVTHSr]]
- %0(s32) = COPY $s0
- %1(s16) = G_FPTRUNC %0
- $h0 = COPY %1(s16)
+ %0(f32) = COPY $s0
+ %1(f16) = G_FPTRUNC %0
+ $h0 = COPY %1(f16)
...
---
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTHDr:%[0-9]+]]:fpr16 = nofpexcept FCVTHDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FCVTHDr]]
- %0(s64) = COPY $d0
- %1(s16) = G_FPTRUNC %0
- $h0 = COPY %1(s16)
+ %0(f64) = COPY $d0
+ %1(f16) = G_FPTRUNC %0
+ $h0 = COPY %1(f16)
...
---
@@ -68,9 +68,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTSDr:%[0-9]+]]:fpr32 = nofpexcept FCVTSDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FCVTSDr]]
- %0(s64) = COPY $d0
- %1(s32) = G_FPTRUNC %0
- $s0 = COPY %1(s32)
+ %0(f64) = COPY $d0
+ %1(f32) = G_FPTRUNC %0
+ $s0 = COPY %1(f32)
...
---
@@ -91,9 +91,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTNv4i16_]]
- %0(<4 x s32>) = COPY $q0
- %1(<4 x s16>) = G_FPTRUNC %0
- $d0 = COPY %1(<4 x s16>)
+ %0(<4 x f32>) = COPY $q0
+ %1(<4 x f16>) = G_FPTRUNC %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -114,9 +114,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTNv2i32_]]
- %0(<2 x s64>) = COPY $q0
- %1(<2 x s32>) = G_FPTRUNC %0
- $d0 = COPY %1(<2 x s32>)
+ %0(<2 x f64>) = COPY $q0
+ %1(<2 x f32>) = G_FPTRUNC %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -138,9 +138,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FCVTSHr]]
- %0(s16) = COPY $h0
- %1(s32) = G_FPEXT %0
- $s0 = COPY %1(s32)
+ %0(f16) = COPY $h0
+ %1(f32) = G_FPEXT %0
+ $s0 = COPY %1(f32)
...
---
@@ -162,9 +162,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK-NEXT: [[FCVTDHr:%[0-9]+]]:fpr64 = nofpexcept FCVTDHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTDHr]]
- %0(s16) = COPY $h0
- %1(s64) = G_FPEXT %0
- $d0 = COPY %1(s64)
+ %0(f16) = COPY $h0
+ %1(f64) = G_FPEXT %0
+ $d0 = COPY %1(f64)
...
---
@@ -186,9 +186,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTDSr:%[0-9]+]]:fpr64 = nofpexcept FCVTDSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTDSr]]
- %0(s32) = COPY $s0
- %1(s64) = G_FPEXT %0
- $d0 = COPY %1(s64)
+ %0(f32) = COPY $s0
+ %1(f64) = G_FPEXT %0
+ $d0 = COPY %1(f64)
...
---
@@ -209,9 +209,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FCVTLv4i16_]]
- %0(<4 x s16>) = COPY $d0
- %1(<4 x s32>) = G_FPEXT %0
- $q0 = COPY %1(<4 x s32>)
+ %0(<4 x f16>) = COPY $d0
+ %1(<4 x f32>) = G_FPEXT %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -232,9 +232,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FCVTLv2i32_]]
- %0(<2 x s32>) = COPY $d0
- %1(<2 x s64>) = G_FPEXT %0
- $q0 = COPY %1(<2 x s64>)
+ %0(<2 x f32>) = COPY $d0
+ %1(<2 x f64>) = G_FPEXT %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -256,9 +256,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUWSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFUWSri]]
- %0(s32) = COPY $w0
- %1(s32) = G_SITOFP %0
- $s0 = COPY %1(s32)
+ %0(i32) = COPY $w0
+ %1(f32) = G_SITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -280,9 +280,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept SCVTFv1i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFv1i32_]]
- %0(s32) = COPY $s0
- %1(s32) = G_SITOFP %0
- $s0 = COPY %1(s32)
+ %0(i32) = COPY $s0
+ %1(f32) = G_SITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -304,9 +304,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept UCVTFv1i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFv1i32_]]
- %0(s32) = COPY $s0
- %1(s32) = G_UITOFP %0
- $s0 = COPY %1(s32)
+ %0(i32) = COPY $s0
+ %1(f32) = G_UITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -328,9 +328,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[SCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUXSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFUXSri]]
- %0(s64) = COPY $x0
- %1(s32) = G_SITOFP %0
- $s0 = COPY %1(s32)
+ %0(i64) = COPY $x0
+ %1(f32) = G_SITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -352,9 +352,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUWDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[SCVTFUWDri]]
- %0(s32) = COPY $w0
- %1(s64) = G_SITOFP %0
- $d0 = COPY %1(s64)
+ %0(i32) = COPY $w0
+ %1(f64) = G_SITOFP %0
+ $d0 = COPY %1(f64)
...
---
@@ -376,9 +376,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[SCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUXDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[SCVTFUXDri]]
- %0(s64) = COPY $x0
- %1(s64) = G_SITOFP %0
- $d0 = COPY %1(s64)
+ %0(i64) = COPY $x0
+ %1(f64) = G_SITOFP %0
+ $d0 = COPY %1(f64)
...
---
@@ -400,9 +400,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUWSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFUWSri]]
- %0(s32) = COPY $w0
- %1(s32) = G_UITOFP %0
- $s0 = COPY %1(s32)
+ %0(i32) = COPY $w0
+ %1(f32) = G_UITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -424,9 +424,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUXSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFUXSri]]
- %0(s64) = COPY $x0
- %1(s32) = G_UITOFP %0
- $s0 = COPY %1(s32)
+ %0(i64) = COPY $x0
+ %1(f32) = G_UITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -448,9 +448,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUWDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[UCVTFUWDri]]
- %0(s32) = COPY $w0
- %1(s64) = G_UITOFP %0
- $d0 = COPY %1(s64)
+ %0(i32) = COPY $w0
+ %1(f64) = G_UITOFP %0
+ $d0 = COPY %1(f64)
...
---
@@ -472,9 +472,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUXDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[UCVTFUXDri]]
- %0(s64) = COPY $x0
- %1(s64) = G_UITOFP %0
- $d0 = COPY %1(s64)
+ %0(i64) = COPY $x0
+ %1(f64) = G_UITOFP %0
+ $d0 = COPY %1(f64)
...
---
@@ -496,9 +496,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZSUWSr]]
- %0(s32) = COPY $s0
- %1(s32) = G_FPTOSI %0
- $w0 = COPY %1(s32)
+ %0(f32) = COPY $s0
+ %1(i32) = G_FPTOSI %0
+ $w0 = COPY %1(i32)
...
---
@@ -520,9 +520,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZSUWDr]]
- %0(s64) = COPY $d0
- %1(s32) = G_FPTOSI %0
- $w0 = COPY %1(s32)
+ %0(f64) = COPY $d0
+ %1(i32) = G_FPTOSI %0
+ $w0 = COPY %1(i32)
...
---
@@ -544,9 +544,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZSUXSr]]
- %0(s32) = COPY $s0
- %1(s64) = G_FPTOSI %0
- $x0 = COPY %1(s64)
+ %0(f32) = COPY $s0
+ %1(i64) = G_FPTOSI %0
+ $x0 = COPY %1(i64)
...
---
@@ -568,9 +568,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZSUXDr]]
- %0(s64) = COPY $d0
- %1(s64) = G_FPTOSI %0
- $x0 = COPY %1(s64)
+ %0(f64) = COPY $d0
+ %1(i64) = G_FPTOSI %0
+ $x0 = COPY %1(i64)
...
---
@@ -592,9 +592,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZUUWSr]]
- %0(s32) = COPY $s0
- %1(s32) = G_FPTOUI %0
- $w0 = COPY %1(s32)
+ %0(f32) = COPY $s0
+ %1(i32) = G_FPTOUI %0
+ $w0 = COPY %1(i32)
...
---
@@ -616,9 +616,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZUUWDr]]
- %0(s64) = COPY $d0
- %1(s32) = G_FPTOUI %0
- $w0 = COPY %1(s32)
+ %0(f64) = COPY $d0
+ %1(i32) = G_FPTOUI %0
+ $w0 = COPY %1(i32)
...
---
@@ -640,9 +640,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZUUXSr]]
- %0(s32) = COPY $s0
- %1(s64) = G_FPTOUI %0
- $x0 = COPY %1(s64)
+ %0(f32) = COPY $s0
+ %1(i64) = G_FPTOUI %0
+ $x0 = COPY %1(i64)
...
---
@@ -664,7 +664,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZUUXDr]]
- %0(s64) = COPY $d0
- %1(s64) = G_FPTOUI %0
- $x0 = COPY %1(s64)
+ %0(f64) = COPY $d0
+ %1(i64) = G_FPTOUI %0
+ $x0 = COPY %1(i64)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir
index 5b6726d6e5bf3..7c7a9cee81ba4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir
@@ -12,8 +12,8 @@ body: |
; CHECK: [[FMOVH0_:%[0-9]+]]:fpr16 = FMOVH0
; CHECK-NEXT: $h0 = COPY [[FMOVH0_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = G_FCONSTANT half 0.0
- $h0 = COPY %0(s16)
+ %0:fpr(f16) = G_FCONSTANT half 0.0
+ $h0 = COPY %0(f16)
RET_ReallyLR implicit $h0
...
---
@@ -27,8 +27,8 @@ body: |
; CHECK: [[FMOVHi:%[0-9]+]]:fpr16 = FMOVHi 112
; CHECK-NEXT: $h0 = COPY [[FMOVHi]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = G_FCONSTANT half 1.0
- $h0 = COPY %0(s16)
+ %0:fpr(f16) = G_FCONSTANT half 1.0
+ $h0 = COPY %0(f16)
RET_ReallyLR implicit $h0
...
---
@@ -43,6 +43,6 @@ body: |
; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s16) from constant-pool)
; CHECK-NEXT: $h0 = COPY [[LDRHui]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = G_FCONSTANT half 0xH000B
- $h0 = COPY %0(s16)
+ %0:fpr(f16) = G_FCONSTANT half 0xH000B
+ $h0 = COPY %0(f16)
RET_ReallyLR implicit $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
index fe4adfac8e721..1ca06aa2c70ea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
@@ -22,11 +22,11 @@ body: |
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FCVTHSr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %2:fpr(s32) = G_FPEXT %0(s16)
- %3:fpr(s32) = G_FRINT %2
- %1:fpr(s16) = G_FPTRUNC %3(s32)
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %2:fpr(f32) = G_FPEXT %0(f16)
+ %3:fpr(f32) = G_FRINT %2
+ %1:fpr(f16) = G_FPTRUNC %3(f32)
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
@@ -81,22 +81,22 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
- %16:fpr(s32) = G_FPEXT %2(s16)
- %17:fpr(s32) = G_FRINT %16
- %6:fpr(s16) = G_FPTRUNC %17(s32)
- %14:fpr(s32) = G_FPEXT %3(s16)
- %15:fpr(s32) = G_FRINT %14
- %7:fpr(s16) = G_FPTRUNC %15(s32)
- %12:fpr(s32) = G_FPEXT %4(s16)
- %13:fpr(s32) = G_FRINT %12
- %8:fpr(s16) = G_FPTRUNC %13(s32)
- %10:fpr(s32) = G_FPEXT %5(s16)
- %11:fpr(s32) = G_FRINT %10
- %9:fpr(s16) = G_FPTRUNC %11(s32)
- %1:fpr(<4 x s16>) = G_BUILD_VECTOR %6(s16), %7(s16), %8(s16), %9(s16)
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %2:fpr(f16), %3:fpr(f16), %4:fpr(f16), %5:fpr(f16) = G_UNMERGE_VALUES %0(<4 x f16>)
+ %16:fpr(f32) = G_FPEXT %2(f16)
+ %17:fpr(f32) = G_FRINT %16
+ %6:fpr(f16) = G_FPTRUNC %17(f32)
+ %14:fpr(f32) = G_FPEXT %3(f16)
+ %15:fpr(f32) = G_FRINT %14
+ %7:fpr(f16) = G_FPTRUNC %15(f32)
+ %12:fpr(f32) = G_FPEXT %4(f16)
+ %13:fpr(f32) = G_FRINT %12
+ %8:fpr(f16) = G_FPTRUNC %13(f32)
+ %10:fpr(f32) = G_FPEXT %5(f16)
+ %11:fpr(f32) = G_FRINT %10
+ %9:fpr(f16) = G_FPTRUNC %11(f32)
+ %1:fpr(<4 x f16>) = G_BUILD_VECTOR %6(f16), %7(f16), %8(f16), %9(f16)
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -172,32 +172,32 @@ body: |
; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
- %32:fpr(s32) = G_FPEXT %2(s16)
- %33:fpr(s32) = G_FRINT %32
- %10:fpr(s16) = G_FPTRUNC %33(s32)
- %30:fpr(s32) = G_FPEXT %3(s16)
- %31:fpr(s32) = G_FRINT %30
- %11:fpr(s16) = G_FPTRUNC %31(s32)
- %28:fpr(s32) = G_FPEXT %4(s16)
- %29:fpr(s32) = G_FRINT %28
- %12:fpr(s16) = G_FPTRUNC %29(s32)
- %26:fpr(s32) = G_FPEXT %5(s16)
- %27:fpr(s32) = G_FRINT %26
- %13:fpr(s16) = G_FPTRUNC %27(s32)
- %24:fpr(s32) = G_FPEXT %6(s16)
- %25:fpr(s32) = G_FRINT %24
- %14:fpr(s16) = G_FPTRUNC %25(s32)
- %22:fpr(s32) = G_FPEXT %7(s16)
- %23:fpr(s32) = G_FRINT %22
- %15:fpr(s16) = G_FPTRUNC %23(s32)
- %20:fpr(s32) = G_FPEXT %8(s16)
- %21:fpr(s32) = G_FRINT %20
- %16:fpr(s16) = G_FPTRUNC %21(s32)
- %18:fpr(s32) = G_FPEXT %9(s16)
- %19:fpr(s32) = G_FRINT %18
- %17:fpr(s16) = G_FPTRUNC %19(s32)
- %1:fpr(<8 x s16>) = G_BUILD_VECTOR %10(s16), %11(s16), %12(s16), %13(s16), %14(s16), %15(s16), %16(s16), %17(s16)
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %2:fpr(f16), %3:fpr(f16), %4:fpr(f16), %5:fpr(f16), %6:fpr(f16), %7:fpr(f16), %8:fpr(f16), %9:fpr(f16) = G_UNMERGE_VALUES %0(<8 x s16>)
+ %32:fpr(f32) = G_FPEXT %2(f16)
+ %33:fpr(f32) = G_FRINT %32
+ %10:fpr(f16) = G_FPTRUNC %33(f32)
+ %30:fpr(f32) = G_FPEXT %3(f16)
+ %31:fpr(f32) = G_FRINT %30
+ %11:fpr(f16) = G_FPTRUNC %31(f32)
+ %28:fpr(f32) = G_FPEXT %4(f16)
+ %29:fpr(f32) = G_FRINT %28
+ %12:fpr(f16) = G_FPTRUNC %29(f32)
+ %26:fpr(f32) = G_FPEXT %5(f16)
+ %27:fpr(f32) = G_FRINT %26
+ %13:fpr(f16) = G_FPTRUNC %27(f32)
+ %24:fpr(f32) = G_FPEXT %6(f16)
+ %25:fpr(f32) = G_FRINT %24
+ %14:fpr(f16) = G_FPTRUNC %25(f32)
+ %22:fpr(f32) = G_FPEXT %7(f16)
+ %23:fpr(f32) = G_FRINT %22
+ %15:fpr(f16) = G_FPTRUNC %23(f32)
+ %20:fpr(f32) = G_FPEXT %8(f16)
+ %21:fpr(f32) = G_FRINT %20
+ %16:fpr(f16) = G_FPTRUNC %21(f32)
+ %18:fpr(f32) = G_FPEXT %9(f16)
+ %19:fpr(f32) = G_FRINT %18
+ %17:fpr(f16) = G_FPTRUNC %19(f32)
+ %1:fpr(<8 x f16>) = G_BUILD_VECTOR %10(f16), %11(f16), %12(f16), %13(f16), %14(f16), %15(f16), %16(f16), %17(f16)
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
index 737c31cd81796..dd83cfa9d6320 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[FRINTXHr:%[0-9]+]]:fpr16 = nofpexcept FRINTXHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FRINTXHr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %1:fpr(s16) = G_FRINT %0
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(f16) = G_FRINT %0
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FRINTXSr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FRINT %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FRINT %0
+ $s0 = COPY %1(f32)
RET_ReallyLR implicit $s0
...
@@ -68,9 +68,9 @@ body: |
; CHECK-NEXT: [[FRINTXDr:%[0-9]+]]:fpr64 = nofpexcept FRINTXDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTXDr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FRINT %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FRINT %0
+ $d0 = COPY %1(f64)
RET_ReallyLR implicit $d0
...
@@ -92,9 +92,9 @@ body: |
; CHECK-NEXT: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTXv4f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FRINT %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FRINT %0
+ $q0 = COPY %1(<4 x f32>)
RET_ReallyLR implicit $q0
...
@@ -116,9 +116,9 @@ body: |
; CHECK-NEXT: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTXv2f64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FRINT %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FRINT %0
+ $q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
...
@@ -140,9 +140,9 @@ body: |
; CHECK-NEXT: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv4f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTXv4f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FRINT %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FRINT %0
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -164,9 +164,9 @@ body: |
; CHECK-NEXT: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv8f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTXv8f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FRINT %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FRINT %0
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
@@ -188,9 +188,9 @@ body: |
; CHECK-NEXT: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTXv2f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FRINT %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FRINT %0
+ $d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
index 9f02f31a15e32..84b595ca60974 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
@@ -104,10 +104,10 @@ body: |
; CHECK-TINY-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[LDRDl]], implicit $fpcr
; CHECK-TINY-NEXT: $d0 = COPY [[FADDDrr]]
; CHECK-TINY-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FCONSTANT double 0x3FEFF7CED916872B
- %2:fpr(s64) = G_FADD %0, %1
- $d0 = COPY %2(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FCONSTANT double 0x3FEFF7CED916872B
+ %2:fpr(f64) = G_FADD %0, %1
+ $d0 = COPY %2(f64)
RET_ReallyLR implicit $d0
...
@@ -140,10 +140,10 @@ body: |
; CHECK-TINY-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSl]], implicit $fpcr
; CHECK-TINY-NEXT: $s0 = COPY [[FADDSrr]]
; CHECK-TINY-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
- %2:fpr(s32) = G_FADD %0, %1
- $s0 = COPY %2(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FCONSTANT float 0x3FDB267DE0000000
+ %2:fpr(f32) = G_FADD %0, %1
+ $s0 = COPY %2(f32)
RET_ReallyLR implicit $s0
...
@@ -176,10 +176,10 @@ body: |
; CHECK-TINY-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSl]], implicit $fpcr
; CHECK-TINY-NEXT: $s0 = COPY [[FADDSrr]]
; CHECK-TINY-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
- %2:fpr(s32) = G_FADD %0, %1
- $s0 = COPY %2(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FCONSTANT float 0x3FDB267DE0000000
+ %2:fpr(f32) = G_FADD %0, %1
+ $s0 = COPY %2(f32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
index 33f7e58804f14..ed665271472cb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
@@ -107,11 +107,11 @@ body: |
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi16lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(s16) = COPY $h0
- %1:fpr(<8 x s16>) = COPY $q1
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s64)
- $q0 = COPY %2(<8 x s16>)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(<8 x f16>) = COPY $q1
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(<8 x f16>) = G_INSERT_VECTOR_ELT %1, %0(f16), %3(i64)
+ $q0 = COPY %2(<8 x f16>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
index 53f2fbb328460..dca4ebdaab165 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[FRINTADr:%[0-9]+]]:fpr64 = nofpexcept FRINTADr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTADr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_INTRINSIC_ROUND %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(f64)
RET_ReallyLR implicit $d0
...
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[FRINTASr:%[0-9]+]]:fpr32 = nofpexcept FRINTASr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FRINTASr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_INTRINSIC_ROUND %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_INTRINSIC_ROUND %0
+ $s0 = COPY %1(f32)
RET_ReallyLR implicit $s0
...
@@ -70,9 +70,9 @@ body: |
; CHECK-NEXT: [[FRINTAHr:%[0-9]+]]:fpr16 = nofpexcept FRINTAHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FRINTAHr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %1:fpr(s16) = G_INTRINSIC_ROUND %0
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(f16) = G_INTRINSIC_ROUND %0
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
@@ -96,9 +96,9 @@ body: |
; CHECK-NEXT: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv4f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTAv4f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_INTRINSIC_ROUND %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -122,9 +122,9 @@ body: |
; CHECK-NEXT: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv8f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTAv8f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_INTRINSIC_ROUND %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
@@ -148,9 +148,9 @@ body: |
; CHECK-NEXT: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTAv2f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_INTRINSIC_ROUND %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
@@ -174,9 +174,9 @@ body: |
; CHECK-NEXT: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTAv4f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_INTRINSIC_ROUND %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<4 x f32>)
RET_ReallyLR implicit $q0
...
@@ -200,7 +200,7 @@ body: |
; CHECK-NEXT: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTAv2f64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_INTRINSIC_ROUND %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
index 57f8ed8b459fc..aa833ede3bda5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[FRINTZDr:%[0-9]+]]:fpr64 = nofpexcept FRINTZDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTZDr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_INTRINSIC_TRUNC %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(f64)
RET_ReallyLR implicit $d0
...
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[FRINTZSr:%[0-9]+]]:fpr32 = nofpexcept FRINTZSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FRINTZSr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_INTRINSIC_TRUNC %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_INTRINSIC_TRUNC %0
+ $s0 = COPY %1(f32)
RET_ReallyLR implicit $s0
...
@@ -70,9 +70,9 @@ body: |
; CHECK-NEXT: [[FRINTZHr:%[0-9]+]]:fpr16 = nofpexcept FRINTZHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FRINTZHr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %1:fpr(s16) = G_INTRINSIC_TRUNC %0
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(f16) = G_INTRINSIC_TRUNC %0
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
@@ -96,9 +96,9 @@ body: |
; CHECK-NEXT: [[FRINTZv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTZv4f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTZv4f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_INTRINSIC_TRUNC %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -122,9 +122,9 @@ body: |
; CHECK-NEXT: [[FRINTZv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv8f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTZv8f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_INTRINSIC_TRUNC %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
@@ -148,9 +148,9 @@ body: |
; CHECK-NEXT: [[FRINTZv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTZv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTZv2f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_INTRINSIC_TRUNC %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
@@ -174,9 +174,9 @@ body: |
; CHECK-NEXT: [[FRINTZv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTZv4f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_INTRINSIC_TRUNC %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<4 x f32>)
RET_ReallyLR implicit $q0
...
@@ -200,7 +200,7 @@ body: |
; CHECK-NEXT: [[FRINTZv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTZv2f64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_INTRINSIC_TRUNC %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
index 9a181adfc0b31..19b1c43d605b7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[FRINTIv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTIv4f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTIv4f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FNEARBYINT %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[FRINTIv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTIv8f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTIv8f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FNEARBYINT %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
@@ -68,9 +68,9 @@ body: |
; CHECK-NEXT: [[FRINTIv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTIv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTIv2f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FNEARBYINT %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
@@ -92,9 +92,9 @@ body: |
; CHECK-NEXT: [[FRINTIv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTIv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTIv2f64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FNEARBYINT %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
...
@@ -116,9 +116,9 @@ body: |
; CHECK-NEXT: [[FRINTISr:%[0-9]+]]:fpr32 = nofpexcept FRINTISr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FRINTISr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FNEARBYINT %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FNEARBYINT %0
+ $s0 = COPY %1(f32)
RET_ReallyLR implicit $s0
...
@@ -140,9 +140,9 @@ body: |
; CHECK-NEXT: [[FRINTIDr:%[0-9]+]]:fpr64 = nofpexcept FRINTIDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTIDr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FNEARBYINT %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FNEARBYINT %0
+ $d0 = COPY %1(f64)
RET_ReallyLR implicit $d0
...
@@ -164,9 +164,9 @@ body: |
; CHECK-NEXT: [[FRINTIHr:%[0-9]+]]:fpr16 = nofpexcept FRINTIHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FRINTIHr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %1:fpr(s16) = G_FNEARBYINT %0
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(f16) = G_FNEARBYINT %0
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir
index 85d9e1ca85a33..f3339542c510a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir
@@ -16,9 +16,9 @@ body: |
; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nofpexcept FADDPv2i32p [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FADDPv2i32p]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(s32) = G_VECREDUCE_FADD %0(<2 x s32>)
- $w0 = COPY %1(s32)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(f32) = G_VECREDUCE_FADD %0(<2 x f32>)
+ $w0 = COPY %1(f32)
RET_ReallyLR implicit $w0
...
@@ -38,9 +38,9 @@ body: |
; CHECK-NEXT: [[FADDPv2i64p:%[0-9]+]]:fpr64 = nofpexcept FADDPv2i64p [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FADDPv2i64p]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:fpr(<2 x s64>) = COPY $q0
- %2:fpr(s64) = G_VECREDUCE_FADD %0(<2 x s64>)
- $x0 = COPY %2(s64)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %2:fpr(f64) = G_VECREDUCE_FADD %0(<2 x f64>)
+ $x0 = COPY %2(f64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
index 13ce9f9966b42..daf552b401c7e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
@@ -15,9 +15,9 @@ body: |
; CHECK-LABEL: name: sqrt_float
; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FSQRTSr %{{[0-9]+}}
liveins: $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FSQRT %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FSQRT %0
+ $s0 = COPY %1(f32)
...
---
@@ -33,9 +33,9 @@ body: |
; CHECK-LABEL: name: sqrt_double
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTDr %{{[0-9]+}}
liveins: $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FSQRT %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FSQRT %0
+ $d0 = COPY %1(f64)
...
---
@@ -51,9 +51,9 @@ body: |
; CHECK-LABEL: name: sqrt_v2f32
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTv2f32 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FSQRT %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FSQRT %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: sqrt_v4f32
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv4f32 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FSQRT %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FSQRT %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK-LABEL: name: sqrt_v2f64
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv2f64 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FSQRT %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FSQRT %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -105,9 +105,9 @@ body: |
; CHECK-LABEL: name: sqrt_v4f16
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTv4f16 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FSQRT %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FSQRT %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -123,8 +123,8 @@ body: |
; CHECK-LABEL: name: sqrt_v8f16
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv8f16 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FSQRT %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FSQRT %0
+ $q0 = COPY %1(<8 x f16>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
index f49d8e733156d..603ded2030b8e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
@@ -22,11 +22,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (f128))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
- %0:fpr(s128) = G_LOAD %1(p0) :: (load (s128))
- $noreg = PATCHABLE_RET %0(s128)
+ %0:fpr(f128) = G_LOAD %1(p0) :: (load (f128))
+ $noreg = PATCHABLE_RET %0(f128)
...
---
@@ -231,11 +231,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (s128))
+ ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (f128))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
- %0:fpr(s128) = COPY $q0
- G_STORE %0(s128), %1(p0) :: (store (s128))
+ %0:fpr(f128) = COPY $q0
+ G_STORE %0(f128), %1(p0) :: (store (f128))
$noreg = PATCHABLE_RET
...
@@ -489,13 +489,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
- %5:fpr(s32) = COPY $s2
- %4:fpr(s32) = COPY $s1
- %3:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FNEG %5
- %0:fpr(s32) = G_FNEG %4
- %2:fpr(s32) = G_FMA %0, %3, %1
- $noreg = PATCHABLE_RET %2(s32)
+ %5:fpr(f32) = COPY $s2
+ %4:fpr(f32) = COPY $s1
+ %3:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FNEG %5
+ %0:fpr(f32) = G_FNEG %4
+ %2:fpr(f32) = G_FMA %0, %3, %1
+ $noreg = PATCHABLE_RET %2(f32)
...
---
@@ -527,13 +527,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
- %5:fpr(s64) = COPY $d2
- %4:fpr(s64) = COPY $d1
- %3:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FNEG %5
- %0:fpr(s64) = G_FNEG %4
- %2:fpr(s64) = G_FMA %0, %3, %1
- $noreg = PATCHABLE_RET %2(s64)
+ %5:fpr(f64) = COPY $d2
+ %4:fpr(f64) = COPY $d1
+ %3:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FNEG %5
+ %0:fpr(f64) = G_FNEG %4
+ %2:fpr(f64) = G_FMA %0, %3, %1
+ $noreg = PATCHABLE_RET %2(f64)
...
---
@@ -565,13 +565,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
- %5:fpr(s32) = COPY $s2
- %4:fpr(s32) = COPY $s1
- %3:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FNEG %5
- %0:fpr(s32) = G_FNEG %4
- %2:fpr(s32) = G_FMA %3, %0, %1
- $noreg = PATCHABLE_RET %2(s32)
+ %5:fpr(f32) = COPY $s2
+ %4:fpr(f32) = COPY $s1
+ %3:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FNEG %5
+ %0:fpr(f32) = G_FNEG %4
+ %2:fpr(f32) = G_FMA %3, %0, %1
+ $noreg = PATCHABLE_RET %2(f32)
...
---
@@ -603,13 +603,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
- %5:fpr(s64) = COPY $d2
- %4:fpr(s64) = COPY $d1
- %3:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FNEG %5
- %0:fpr(s64) = G_FNEG %4
- %2:fpr(s64) = G_FMA %3, %0, %1
- $noreg = PATCHABLE_RET %2(s64)
+ %5:fpr(f64) = COPY $d2
+ %4:fpr(f64) = COPY $d1
+ %3:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FNEG %5
+ %0:fpr(f64) = G_FNEG %4
+ %2:fpr(f64) = G_FMA %3, %0, %1
+ $noreg = PATCHABLE_RET %2(f64)
...
---
@@ -638,12 +638,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]]
- %4:fpr(<8 x s8>) = COPY $d1
- %3:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
- %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
- %2:fpr(<8 x s16>) = G_ADD %0, %1
- $noreg = PATCHABLE_RET %2(<8 x s16>)
+ %4:fpr(<8 x i8>) = COPY $d1
+ %3:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i16>) = G_SEXT %4(<8 x i8>)
+ %0:fpr(<8 x i16>) = G_SEXT %3(<8 x i8>)
+ %2:fpr(<8 x i16>) = G_ADD %0, %1
+ $noreg = PATCHABLE_RET %2(<8 x i16>)
...
---
@@ -1048,12 +1048,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
- %4:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FNEG %4
- %1:fpr(s32) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(s32)
+ %4:fpr(f32) = COPY $s2
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FNEG %4
+ %1:fpr(f32) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -1084,12 +1084,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
- %4:fpr(s64) = COPY $d2
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FNEG %4
- %1:fpr(s64) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(s64)
+ %4:fpr(f64) = COPY $d2
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FNEG %4
+ %1:fpr(f64) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -1120,12 +1120,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
- %4:fpr(<2 x s32>) = COPY $d2
- %3:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FNEG %4
- %1:fpr(<2 x s32>) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(<2 x s32>)
+ %4:fpr(<2 x f32>) = COPY $d2
+ %3:fpr(<2 x f32>) = COPY $d1
+ %2:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FNEG %4
+ %1:fpr(<2 x f32>) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(<2 x f32>)
...
---
@@ -1156,12 +1156,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
- %4:fpr(<4 x s32>) = COPY $q2
- %3:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FNEG %4
- %1:fpr(<4 x s32>) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %4:fpr(<4 x f32>) = COPY $q2
+ %3:fpr(<4 x f32>) = COPY $q1
+ %2:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FNEG %4
+ %1:fpr(<4 x f32>) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(<4 x f32>)
...
---
@@ -1192,12 +1192,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
- %4:fpr(<2 x s64>) = COPY $q2
- %3:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FNEG %4
- %1:fpr(<2 x s64>) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %4:fpr(<2 x f64>) = COPY $q2
+ %3:fpr(<2 x f64>) = COPY $q1
+ %2:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FNEG %4
+ %1:fpr(<2 x f64>) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(<2 x f64>)
...
---
@@ -1228,12 +1228,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
- %4:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FNEG %4
- %1:fpr(s32) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(s32)
+ %4:fpr(f32) = COPY $s2
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FNEG %4
+ %1:fpr(f32) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -1264,12 +1264,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
- %4:fpr(s64) = COPY $d2
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FNEG %4
- %1:fpr(s64) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(s64)
+ %4:fpr(f64) = COPY $d2
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FNEG %4
+ %1:fpr(f64) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -1300,12 +1300,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
- %4:fpr(<2 x s32>) = COPY $d2
- %3:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FNEG %4
- %1:fpr(<2 x s32>) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(<2 x s32>)
+ %4:fpr(<2 x f32>) = COPY $d2
+ %3:fpr(<2 x f32>) = COPY $d1
+ %2:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FNEG %4
+ %1:fpr(<2 x f32>) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(<2 x f32>)
...
---
@@ -1336,12 +1336,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
- %4:fpr(<4 x s32>) = COPY $q2
- %3:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FNEG %4
- %1:fpr(<4 x s32>) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %4:fpr(<4 x f32>) = COPY $q2
+ %3:fpr(<4 x f32>) = COPY $q1
+ %2:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FNEG %4
+ %1:fpr(<4 x f32>) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(<4 x f32>)
...
---
@@ -1372,12 +1372,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
- %4:fpr(<2 x s64>) = COPY $q2
- %3:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FNEG %4
- %1:fpr(<2 x s64>) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %4:fpr(<2 x f64>) = COPY $q2
+ %3:fpr(<2 x f64>) = COPY $q1
+ %2:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FNEG %4
+ %1:fpr(<2 x f64>) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(<2 x f64>)
...
---
@@ -1408,12 +1408,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]
- %4:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FNEG %4
- %1:fpr(s32) = G_FMA %2, %3, %0
- $noreg = PATCHABLE_RET %1(s32)
+ %4:fpr(f32) = COPY $s2
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FNEG %4
+ %1:fpr(f32) = G_FMA %2, %3, %0
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -1444,12 +1444,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]
- %4:fpr(s64) = COPY $d2
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FNEG %4
- %1:fpr(s64) = G_FMA %2, %3, %0
- $noreg = PATCHABLE_RET %1(s64)
+ %4:fpr(f64) = COPY $d2
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FNEG %4
+ %1:fpr(f64) = G_FMA %2, %3, %0
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -2500,12 +2500,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
- %4:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FMA %2, %3, %4
- %1:fpr(s32) = G_FNEG %0
- $noreg = PATCHABLE_RET %1(s32)
+ %4:fpr(f32) = COPY $s2
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FMA %2, %3, %4
+ %1:fpr(f32) = G_FNEG %0
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -2536,12 +2536,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
- %4:fpr(s64) = COPY $d2
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FMA %2, %3, %4
- %1:fpr(s64) = G_FNEG %0
- $noreg = PATCHABLE_RET %1(s64)
+ %4:fpr(f64) = COPY $d2
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FMA %2, %3, %4
+ %1:fpr(f64) = G_FNEG %0
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -2569,11 +2569,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMULSrr:%[0-9]+]]:fpr32 = nofpexcept FNMULSrr [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMULSrr]]
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FMUL %2, %3
- %1:fpr(s32) = G_FNEG %0
- $noreg = PATCHABLE_RET %1(s32)
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FMUL %2, %3
+ %1:fpr(f32) = G_FNEG %0
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -2601,11 +2601,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMULDrr:%[0-9]+]]:fpr64 = nofpexcept FNMULDrr [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMULDrr]]
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FMUL %2, %3
- %1:fpr(s64) = G_FNEG %0
- $noreg = PATCHABLE_RET %1(s64)
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FMUL %2, %3
+ %1:fpr(f64) = G_FNEG %0
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -2695,11 +2695,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMLAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv2f32_]]
- %3:fpr(<2 x s32>) = COPY $d2
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FMA %1, %2, %3
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %3:fpr(<2 x f32>) = COPY $d2
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FMA %1, %2, %3
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -2729,11 +2729,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv4f32_]]
- %3:fpr(<4 x s32>) = COPY $q2
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FMA %1, %2, %3
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %3:fpr(<4 x f32>) = COPY $q2
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FMA %1, %2, %3
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -2763,11 +2763,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv2f64_]]
- %3:fpr(<2 x s64>) = COPY $q2
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FMA %1, %2, %3
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %3:fpr(<2 x f64>) = COPY $q2
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FMA %1, %2, %3
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3034,10 +3034,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = nofpexcept FADDv2f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv2f32_]]
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FADD %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FADD %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -3064,10 +3064,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDv4f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv4f32_]]
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FADD %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FADD %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -3094,10 +3094,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FADDv2f64_:%[0-9]+]]:fpr128 = nofpexcept FADDv2f64 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv2f64_]]
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FADD %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FADD %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3124,10 +3124,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FDIVv2f32_:%[0-9]+]]:fpr64 = nofpexcept FDIVv2f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv2f32_]]
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FDIV %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FDIV %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -3154,10 +3154,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FDIVv4f32_:%[0-9]+]]:fpr128 = nofpexcept FDIVv4f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv4f32_]]
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FDIV %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FDIV %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -3184,10 +3184,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FDIVv2f64_:%[0-9]+]]:fpr128 = nofpexcept FDIVv2f64 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv2f64_]]
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FDIV %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FDIV %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3214,10 +3214,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMULv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMULv2f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv2f32_]]
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FMUL %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FMUL %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -3244,10 +3244,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMULv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMULv4f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv4f32_]]
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FMUL %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FMUL %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -3274,10 +3274,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMULv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMULv2f64 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv2f64_]]
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FMUL %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FMUL %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3304,10 +3304,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FSUBv2f32_:%[0-9]+]]:fpr64 = nofpexcept FSUBv2f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv2f32_]]
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FSUB %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FSUB %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -3334,10 +3334,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FSUBv4f32_:%[0-9]+]]:fpr128 = nofpexcept FSUBv4f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv4f32_]]
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FSUB %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FSUB %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -3364,10 +3364,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FSUBv2f64_:%[0-9]+]]:fpr128 = nofpexcept FSUBv2f64 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv2f64_]]
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FSUB %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FSUB %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3949,9 +3949,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGSr]]
- %1:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(s32)
+ %1:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(f32)
...
---
@@ -3975,9 +3975,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGDr]]
- %1:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(s64)
+ %1:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(f64)
...
---
@@ -4001,9 +4001,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -4027,9 +4027,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -4053,9 +4053,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -4079,9 +4079,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTLv2i32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f64>) = G_FPEXT %1(<2 x f32>)
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -4105,9 +4105,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x f16>) = COPY $d0
+ %0:fpr(<4 x f32>) = G_FPEXT %1(<4 x f16>)
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -4131,9 +4131,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZSv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x i32>) = G_FPTOSI %1(<2 x f32>)
+ $noreg = PATCHABLE_RET %0(<2 x i32>)
...
---
@@ -4157,9 +4157,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_FPTOSI %1(<4 x f32>)
+ $noreg = PATCHABLE_RET %0(<4 x i32>)
...
---
@@ -4183,9 +4183,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_FPTOSI %1(<2 x f64>)
+ $noreg = PATCHABLE_RET %0(<2 x i64>)
...
---
@@ -4209,9 +4209,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZUv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x i32>) = G_FPTOUI %1(<2 x f32>)
+ $noreg = PATCHABLE_RET %0(<2 x i32>)
...
---
@@ -4235,9 +4235,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_FPTOUI %1(<4 x f32>)
+ $noreg = PATCHABLE_RET %0(<4 x i32>)
...
---
@@ -4261,9 +4261,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_FPTOUI %1(<2 x f64>)
+ $noreg = PATCHABLE_RET %0(<2 x i64>)
...
---
@@ -4287,9 +4287,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTNv2i32_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f32>) = G_FPTRUNC %1(<2 x f64>)
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -4313,9 +4313,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f16>) = G_FPTRUNC %1(<4 x f32>)
+ $noreg = PATCHABLE_RET %0(<4 x f16>)
...
---
@@ -4417,9 +4417,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept SCVTFv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x i32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_SITOFP %1(<2 x i32>)
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -4443,9 +4443,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_SITOFP %1(<4 x i32>)
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -4469,9 +4469,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_SITOFP %1(<2 x i64>)
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -4573,9 +4573,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x i32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_UITOFP %1(<2 x i32>)
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -4599,9 +4599,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_UITOFP %1(<4 x i32>)
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -4625,9 +4625,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_UITOFP %1(<2 x i64>)
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
index 94af12a91ae97..894cf33aa182a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
@@ -124,10 +124,11 @@ body: |
; CHECK-LABEL: name: strsrox
; CHECK: liveins: $x0, $x1, $s2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: %ptr:gpr64common = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s2
- ; CHECK-NEXT: STRSroX [[COPY2]], [[COPY]], [[COPY1]], 0, 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRSui [[COPY2]], %ptr, 0 :: (store (s32) into %ir.addr)
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = COPY $x1
%ptr:gpr(p0) = G_PTR_ADD %0, %1
@@ -147,10 +148,11 @@ body: |
; CHECK-LABEL: name: strhrox
; CHECK: liveins: $x0, $x1, $h0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: %ptr:gpr64common = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK-NEXT: STRHroX [[COPY2]], [[COPY]], [[COPY1]], 0, 0 :: (store (s16) into %ir.addr)
+ ; CHECK-NEXT: STRHui [[COPY2]], %ptr, 0 :: (store (s16) into %ir.addr)
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = COPY $x1
%ptr:gpr(p0) = G_PTR_ADD %0, %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
index 9a025aa35b874..e7592fe49c863 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
@@ -6,28 +6,29 @@
define void @test_const(ptr %dst) {
; CHECK-LABEL: name: test_const
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (s8) into %ir.dst)
- ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 20
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (s8) into %ir.dst + 1)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (s8) into %ir.dst + 2)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (s8) into %ir.dst + 3)
- ; CHECK: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 50
- ; CHECK: STRBBui [[MOVi32imm2]], [[COPY]], 4 :: (store (s8) into %ir.dst + 4)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (s8) into %ir.dst + 5)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (s8) into %ir.dst + 6)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (s8) into %ir.dst + 7)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (s8) into %ir.dst)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (s8) into %ir.dst + 1)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (s8) into %ir.dst + 2)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (s8) into %ir.dst + 3)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 4 :: (store (s8) into %ir.dst + 4)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (s8) into %ir.dst + 5)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (s8) into %ir.dst + 6)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (s8) into %ir.dst + 7)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (i8) into %ir.dst)
+ ; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 20
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (i8) into %ir.dst + 1)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (i8) into %ir.dst + 2)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (i8) into %ir.dst + 3)
+ ; CHECK-NEXT: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 50
+ ; CHECK-NEXT: STRBBui [[MOVi32imm2]], [[COPY]], 4 :: (store (i8) into %ir.dst + 4)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (i8) into %ir.dst + 5)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (i8) into %ir.dst + 6)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (i8) into %ir.dst + 7)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (i8) into %ir.dst)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (i8) into %ir.dst + 1)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (i8) into %ir.dst + 2)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (i8) into %ir.dst + 3)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 4 :: (store (i8) into %ir.dst + 4)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (i8) into %ir.dst + 5)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (i8) into %ir.dst + 6)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (i8) into %ir.dst + 7)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
%updated = insertvalue
; Check that we're visiting constants with shared parts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
index 5b2d6607f6297..06b9359d0078b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
@@ -8,9 +8,9 @@ define ptr @translate_element_size1(i64 %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[C]], [[COPY]](s64)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[C]], [[COPY]](i64)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -25,8 +25,8 @@ define ptr @first_offset_const(ptr %addr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type, ptr %addr, i32 1
@@ -54,10 +54,10 @@ define ptr @first_offset_variable(ptr %addr, i64 %idx) {
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -72,11 +72,11 @@ define ptr @first_offset_ext(ptr %addr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -92,12 +92,12 @@ define ptr @const_then_var(ptr %addr, i64 %idx) {
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 272
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 272
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD1]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -112,12 +112,12 @@ define ptr @var_then_const(ptr %addr, i64 %idx) {
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type1, ptr %addr, i64 %idx, i32 2, i32 2
@@ -131,13 +131,13 @@ define <2 x ptr> @vec_gep_scalar_base(<2 x i64> %offs) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @arr
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[GV]](p0), [[GV]](p0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x s64>) = nsw G_MUL [[COPY]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p0>) = nusw inbounds G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = nsw G_MUL [[COPY]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p0>) = nusw inbounds G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x i64>)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY [[PTR_ADD]](<2 x p0>)
; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -151,16 +151,18 @@ define <4 x ptr> @vector_gep_v4i32(<4 x ptr> %b, <4 x i32> %off) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s64>) = G_SEXT [[COPY2]](<4 x s32>)
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<4 x p0>) = G_PTR_ADD [[CONCAT_VECTORS]], [[SEXT]](<4 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<2 x p0>), [[BITCAST1]](<2 x p0>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x i32>) = COPY $q2
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<4 x i64>) = G_SEXT [[COPY2]](<4 x i32>)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<4 x p0>) = G_PTR_ADD [[CONCAT_VECTORS]], [[SEXT]](<4 x i64>)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x p0>) = COPY [[PTR_ADD]](<4 x p0>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[COPY3]](<4 x p0>)
- ; CHECK-NEXT: $q0 = COPY [[UV]](<2 x s64>)
- ; CHECK-NEXT: $q1 = COPY [[UV1]](<2 x s64>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i64>), [[UV1:%[0-9]+]]:_(<2 x i64>) = G_UNMERGE_VALUES [[COPY3]](<4 x p0>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<2 x i64>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
entry:
%g = getelementptr i8, <4 x ptr> %b, <4 x i32> %off
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
index cf620cc52b906..c5748c83bb88a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
@@ -8,10 +8,10 @@ define i128 @func_i128(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.ptr)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i128) = G_LOAD [[COPY]](p0) :: (load (i128) from %ir.ptr)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](i128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%val = load i128, ptr %ptr
ret i128 %val
@@ -24,10 +24,10 @@ define <8 x float> @func_v8f32(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p0) :: (load (<8 x s32>) from %ir.ptr)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[LOAD]](<8 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
- ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x f32>) = G_LOAD [[COPY]](p0) :: (load (<8 x f32>) from %ir.ptr)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x f32>), [[UV1:%[0-9]+]]:_(<4 x f32>) = G_UNMERGE_VALUES [[LOAD]](<8 x f32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x f32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%val = load <8 x float>, ptr %ptr
ret <8 x float> %val
@@ -41,14 +41,14 @@ define <6 x float> @func_v6f32(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<6 x s32>) = G_LOAD [[COPY]](p0) :: (load (<6 x s32>) from %ir.ptr, align 32)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<6 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[UV]](s32)
- ; CHECK-NEXT: $s1 = COPY [[UV1]](s32)
- ; CHECK-NEXT: $s2 = COPY [[UV2]](s32)
- ; CHECK-NEXT: $s3 = COPY [[UV3]](s32)
- ; CHECK-NEXT: $s4 = COPY [[UV4]](s32)
- ; CHECK-NEXT: $s5 = COPY [[UV5]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<6 x f32>) = G_LOAD [[COPY]](p0) :: (load (<6 x f32>) from %ir.ptr, align 32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[LOAD]](<6 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[UV]](f32)
+ ; CHECK-NEXT: $s1 = COPY [[UV1]](f32)
+ ; CHECK-NEXT: $s2 = COPY [[UV2]](f32)
+ ; CHECK-NEXT: $s3 = COPY [[UV3]](f32)
+ ; CHECK-NEXT: $s4 = COPY [[UV4]](f32)
+ ; CHECK-NEXT: $s5 = COPY [[UV5]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1, implicit $s2, implicit $s3, implicit $s4, implicit $s5
%val = load <6 x float>, ptr %ptr
ret <6 x float> %val
@@ -59,13 +59,14 @@ define i128 @ABIi128(i128 %arg1) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s128) = G_FPTOUI [[MV]](s128)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPTOUI]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f128) = G_BITCAST [[MV]](i128)
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(i128) = G_FPTOUI [[BITCAST]](f128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[FPTOUI]](i128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%farg1 = bitcast i128 %arg1 to fp128
%res = fptoui fp128 %farg1 to i128
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
index 28d53dab9d99f..255b2c6505e79 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
@@ -11,16 +11,20 @@ define void @formal_argument_mix_sve(
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
<vscale x 8 x i16> %0, <vscale x 8 x float> %1, <vscale x 16 x i8> %2, <vscale x 8 x ptr> %3
) {
@@ -34,8 +38,8 @@ define void @formal_argument_mix_sve_double(
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $d1, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $d1
; CHECK-NEXT: RET_ReallyLR
<vscale x 8 x i16> %0, double %1
) {
@@ -47,10 +51,10 @@ define void @formal_argument_mix_sve_int_double(
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $d0, $w0, $z1, $z2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
; CHECK-NEXT: RET_ReallyLR
double %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i16> %3
) {
@@ -66,14 +70,14 @@ define void @formal_argument_nxv2i64_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3,
<vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7
@@ -86,14 +90,14 @@ define void @formal_argument_nxv2f64_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3,
<vscale x 2 x double> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %6, <vscale x 2 x double> %7
@@ -127,14 +131,14 @@ define void @formal_argument_nxv4i32_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3,
<vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7
@@ -147,14 +151,14 @@ define void @formal_argument_nxv4f32_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3,
<vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7
@@ -167,18 +171,18 @@ define void @formal_argument_nxv4i64_4(<vscale x 4 x i64> %0, <vscale x 4 x i64>
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x i64>), [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 2 x i64>), [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -188,18 +192,26 @@ define void @formal_argument_nxv4p0_4(<vscale x 4 x ptr> %0, <vscale x 4 x ptr>
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST4]](<vscale x 2 x p0>), [[BITCAST5]](<vscale x 2 x p0>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST6]](<vscale x 2 x p0>), [[BITCAST7]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -210,14 +222,14 @@ define void @formal_argument_nxv8i16_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3,
<vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7
@@ -230,18 +242,18 @@ define void @formal_argument_nxv8i32_4(<vscale x 8 x i32> %0, <vscale x 8 x i32>
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x i32>), [[COPY5]](<vscale x 4 x i32>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 4 x i32>), [[COPY7]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -251,18 +263,18 @@ define void @formal_argument_nxv8f32_4(<vscale x 8 x float> %0, <vscale x 8 x fl
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x f32>), [[COPY5]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 4 x f32>), [[COPY7]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -272,16 +284,16 @@ define void @formal_argument_nxv8i64_2(<vscale x 8 x i64> %0, <vscale x 8 x i64>
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>), [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x i64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x i64>), [[COPY5]](<vscale x 2 x i64>), [[COPY6]](<vscale x 2 x i64>), [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -291,16 +303,16 @@ define void @formal_argument_nxv8f64_2(<vscale x 8 x double> %0, <vscale x 8 x d
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x f64>), [[COPY1]](<vscale x 2 x f64>), [[COPY2]](<vscale x 2 x f64>), [[COPY3]](<vscale x 2 x f64>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x f64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x f64>), [[COPY5]](<vscale x 2 x f64>), [[COPY6]](<vscale x 2 x f64>), [[COPY7]](<vscale x 2 x f64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -310,16 +322,24 @@ define void @formal_argument_nxv8p0_2(<vscale x 8 x ptr> %0, <vscale x 8 x ptr>
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[BITCAST4]](<vscale x 2 x p0>), [[BITCAST5]](<vscale x 2 x p0>), [[BITCAST6]](<vscale x 2 x p0>), [[BITCAST7]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -331,14 +351,14 @@ define void @formal_argument_nxv16i8_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3,
<vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7
@@ -351,18 +371,18 @@ define void @formal_argument_nxv16i16_4(<vscale x 16 x i16> %0, <vscale x 16 x i
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 8 x s16>), [[COPY5]](<vscale x 8 x s16>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 8 x s16>), [[COPY7]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 8 x i16>), [[COPY5]](<vscale x 8 x i16>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 8 x i16>), [[COPY7]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -372,16 +392,16 @@ define void @formal_argument_nxv16i32_2(<vscale x 16 x i32> %0, <vscale x 16 x i
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>), [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x i32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x i32>), [[COPY5]](<vscale x 4 x i32>), [[COPY6]](<vscale x 4 x i32>), [[COPY7]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -391,16 +411,16 @@ define void @formal_argument_nxv16f32_2(<vscale x 16 x float> %0, <vscale x 16 x
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x f32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x f32>), [[COPY5]](<vscale x 4 x f32>), [[COPY6]](<vscale x 4 x f32>), [[COPY7]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -410,15 +430,15 @@ define void @formal_argument_nxv16i64_1(<vscale x 16 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>), [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>), [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>), [[COPY4]](<vscale x 2 x i64>), [[COPY5]](<vscale x 2 x i64>), [[COPY6]](<vscale x 2 x i64>), [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -428,15 +448,23 @@ define void @formal_argument_nxv16p0_1(<vscale x 16 x ptr> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x p0>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>), [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>), [[BITCAST4]](<vscale x 2 x p0>), [[BITCAST5]](<vscale x 2 x p0>), [[BITCAST6]](<vscale x 2 x p0>), [[BITCAST7]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -448,18 +476,18 @@ define void @formal_argument_nxv32i8_4(<vscale x 32 x i8> %0, <vscale x 32 x i8>
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 16 x s8>), [[COPY3]](<vscale x 16 x s8>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 16 x s8>), [[COPY5]](<vscale x 16 x s8>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 16 x s8>), [[COPY7]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 16 x i8>), [[COPY3]](<vscale x 16 x i8>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 16 x i8>), [[COPY5]](<vscale x 16 x i8>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 16 x i8>), [[COPY7]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -469,16 +497,16 @@ define void @formal_argument_nxv32i16_2(<vscale x 32 x i16> %0, <vscale x 32 x i
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>), [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 32 x s16>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 8 x s16>), [[COPY5]](<vscale x 8 x s16>), [[COPY6]](<vscale x 8 x s16>), [[COPY7]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>), [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 32 x i16>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 8 x i16>), [[COPY5]](<vscale x 8 x i16>), [[COPY6]](<vscale x 8 x i16>), [[COPY7]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -488,15 +516,15 @@ define void @formal_argument_nxv32i32_1(<vscale x 32 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>), [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>), [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>), [[COPY4]](<vscale x 4 x i32>), [[COPY5]](<vscale x 4 x i32>), [[COPY6]](<vscale x 4 x i32>), [[COPY7]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -506,15 +534,15 @@ define void @formal_argument_nxv32f32_1(<vscale x 32 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>), [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>), [[COPY4]](<vscale x 4 x f32>), [[COPY5]](<vscale x 4 x f32>), [[COPY6]](<vscale x 4 x f32>), [[COPY7]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -526,16 +554,16 @@ define void @formal_argument_nxv64i8_2(<vscale x 64 x i8> %0, <vscale x 64 x i8>
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>), [[COPY2]](<vscale x 16 x s8>), [[COPY3]](<vscale x 16 x s8>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 16 x s8>), [[COPY5]](<vscale x 16 x s8>), [[COPY6]](<vscale x 16 x s8>), [[COPY7]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>), [[COPY2]](<vscale x 16 x i8>), [[COPY3]](<vscale x 16 x i8>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 64 x i8>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 16 x i8>), [[COPY5]](<vscale x 16 x i8>), [[COPY6]](<vscale x 16 x i8>), [[COPY7]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -545,15 +573,15 @@ define void @formal_argument_nxv64i16_1(<vscale x 64 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>), [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>), [[COPY4]](<vscale x 8 x s16>), [[COPY5]](<vscale x 8 x s16>), [[COPY6]](<vscale x 8 x s16>), [[COPY7]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>), [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>), [[COPY4]](<vscale x 8 x i16>), [[COPY5]](<vscale x 8 x i16>), [[COPY6]](<vscale x 8 x i16>), [[COPY7]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
index ec89da824779a..4e96cc0d9b08f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
@@ -9,7 +9,7 @@ define void @formal_argument_nxv16i8(<vscale x 16 x i8> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -19,7 +19,7 @@ define void @formal_argument_nxv8i16(<vscale x 8 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -29,7 +29,7 @@ define void @formal_argument_nxv4i32(<vscale x 4 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -39,7 +39,7 @@ define void @formal_argument_nxv2i64(<vscale x 2 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -49,7 +49,7 @@ define void @formal_argument_nxv4f32(<vscale x 4 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -59,7 +59,7 @@ define void @formal_argument_nxv2f64(<vscale x 2 x double> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -81,9 +81,9 @@ define void @formal_argument_nxv32i8(<vscale x 32 x i8> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -93,9 +93,9 @@ define void @formal_argument_nxv16i16(<vscale x 16 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -105,9 +105,9 @@ define void @formal_argument_nxv8i32(<vscale x 8 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -117,9 +117,9 @@ define void @formal_argument_nxv4i64(<vscale x 4 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -129,9 +129,9 @@ define void @formal_argument_nxv8f32(<vscale x 8 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -141,9 +141,9 @@ define void @formal_argument_nxv4f64(<vscale x 4 x double> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x f64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x f64>), [[COPY1]](<vscale x 2 x f64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -153,9 +153,11 @@ define void @formal_argument_nxv4p0(<vscale x 4 x ptr> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -167,11 +169,11 @@ define void @formal_argument_nxv64i8(<vscale x 64 x i8> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>), [[COPY2]](<vscale x 16 x s8>), [[COPY3]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>), [[COPY2]](<vscale x 16 x i8>), [[COPY3]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -181,11 +183,11 @@ define void @formal_argument_nxv32i16(<vscale x 32 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>), [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>), [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -195,11 +197,11 @@ define void @formal_argument_nxv16i32(<vscale x 16 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>), [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -209,11 +211,11 @@ define void @formal_argument_nxv8i64(<vscale x 8 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>), [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -223,11 +225,11 @@ define void @formal_argument_nxv16f32(<vscale x 16 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -237,11 +239,11 @@ define void @formal_argument_nxv8f64(<vscale x 8 x double> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x f64>), [[COPY1]](<vscale x 2 x f64>), [[COPY2]](<vscale x 2 x f64>), [[COPY3]](<vscale x 2 x f64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -251,11 +253,15 @@ define void @formal_argument_nxv8p0(<vscale x 8 x ptr> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -267,15 +273,15 @@ define void @formal_argument_nxv128i8(<vscale x 128 x i8> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 128 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>), [[COPY2]](<vscale x 16 x s8>), [[COPY3]](<vscale x 16 x s8>), [[COPY4]](<vscale x 16 x s8>), [[COPY5]](<vscale x 16 x s8>), [[COPY6]](<vscale x 16 x s8>), [[COPY7]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 128 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>), [[COPY2]](<vscale x 16 x i8>), [[COPY3]](<vscale x 16 x i8>), [[COPY4]](<vscale x 16 x i8>), [[COPY5]](<vscale x 16 x i8>), [[COPY6]](<vscale x 16 x i8>), [[COPY7]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -285,15 +291,15 @@ define void @formal_argument_nxv64i16(<vscale x 64 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>), [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>), [[COPY4]](<vscale x 8 x s16>), [[COPY5]](<vscale x 8 x s16>), [[COPY6]](<vscale x 8 x s16>), [[COPY7]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>), [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>), [[COPY4]](<vscale x 8 x i16>), [[COPY5]](<vscale x 8 x i16>), [[COPY6]](<vscale x 8 x i16>), [[COPY7]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -303,15 +309,15 @@ define void @formal_argument_nxv32i32(<vscale x 32 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>), [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>), [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>), [[COPY4]](<vscale x 4 x i32>), [[COPY5]](<vscale x 4 x i32>), [[COPY6]](<vscale x 4 x i32>), [[COPY7]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -321,15 +327,15 @@ define void @formal_argument_nxv16i64(<vscale x 16 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>), [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>), [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>), [[COPY4]](<vscale x 2 x i64>), [[COPY5]](<vscale x 2 x i64>), [[COPY6]](<vscale x 2 x i64>), [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -339,15 +345,15 @@ define void @formal_argument_nxv32f32(<vscale x 32 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>), [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>), [[COPY4]](<vscale x 4 x f32>), [[COPY5]](<vscale x 4 x f32>), [[COPY6]](<vscale x 4 x f32>), [[COPY7]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -357,15 +363,15 @@ define void @formal_argument_nxv16f64(<vscale x 16 x double> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>), [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x f64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x f64>), [[COPY1]](<vscale x 2 x f64>), [[COPY2]](<vscale x 2 x f64>), [[COPY3]](<vscale x 2 x f64>), [[COPY4]](<vscale x 2 x f64>), [[COPY5]](<vscale x 2 x f64>), [[COPY6]](<vscale x 2 x f64>), [[COPY7]](<vscale x 2 x f64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -375,15 +381,23 @@ define void @formal_argument_nxv16p0(<vscale x 16 x ptr> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x p0>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>), [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>), [[BITCAST4]](<vscale x 2 x p0>), [[BITCAST5]](<vscale x 2 x p0>), [[BITCAST6]](<vscale x 2 x p0>), [[BITCAST7]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
index 40bb8a89ca5e4..9274680c93824 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
@@ -6,10 +6,10 @@ define i12 @v1i12(<1 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <1 x i12> %v, i32 0
ret i12 %r
@@ -20,12 +20,12 @@ define i12 @v2i12(<2 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s12>) = G_TRUNC [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<2 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i12>) = G_TRUNC [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<2 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <2 x i12> %v, i32 1
ret i12 %r
@@ -36,15 +36,15 @@ define i12 @v3i12(<3 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x s12>) = G_TRUNC [[BUILD_VECTOR]](<3 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<3 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x i12>) = G_TRUNC [[BUILD_VECTOR]](<3 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<3 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <3 x i12> %v, i32 1
ret i12 %r
@@ -55,12 +55,12 @@ define i12 @v4i12(<4 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s12>) = G_TRUNC [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<4 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $d0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x i12>) = G_TRUNC [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<4 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <4 x i12> %v, i32 1
ret i12 %r
@@ -71,17 +71,17 @@ define i12 @v5i12(<5 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<5 x s12>) = G_TRUNC [[BUILD_VECTOR]](<5 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<5 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<5 x i12>) = G_TRUNC [[BUILD_VECTOR]](<5 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<5 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <5 x i12> %v, i32 1
ret i12 %r
@@ -92,18 +92,18 @@ define i12 @v6i12(<6 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4, $w5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<6 x s12>) = G_TRUNC [[BUILD_VECTOR]](<6 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<6 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<6 x i12>) = G_TRUNC [[BUILD_VECTOR]](<6 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<6 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <6 x i12> %v, i32 1
ret i12 %r
@@ -114,19 +114,19 @@ define i12 @v7i12(<7 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4, $w5, $w6
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $w6
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<7 x s12>) = G_TRUNC [[BUILD_VECTOR]](<7 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<7 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $w6
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<7 x i12>) = G_TRUNC [[BUILD_VECTOR]](<7 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<7 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <7 x i12> %v, i32 1
ret i12 %r
@@ -137,12 +137,12 @@ define i12 @v8i12(<8 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s12>) = G_TRUNC [[COPY]](<8 x s16>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<8 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i16>) = COPY $q0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x i12>) = G_TRUNC [[COPY]](<8 x i16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<8 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <8 x i12> %v, i32 1
ret i12 %r
@@ -153,28 +153,28 @@ define i12 @v12i12(<12 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4, $w5, $w6, $w7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $w6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $w7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $w6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $w7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.3, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i32) from %fixed-stack.3, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.2, align 8)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i32) from %fixed-stack.2, align 8)
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (s32) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (i32) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load (s32) from %fixed-stack.0, align 8)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<12 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<12 x s12>) = G_TRUNC [[BUILD_VECTOR]](<12 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<12 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load (i32) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<12 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[LOAD]](i32), [[LOAD1]](i32), [[LOAD2]](i32), [[LOAD3]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<12 x i12>) = G_TRUNC [[BUILD_VECTOR]](<12 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<12 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <12 x i12> %v, i32 1
ret i12 %r
@@ -186,14 +186,14 @@ define i100 @v1i100(<1 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <1 x i100> %v, i32 0
ret i100 %r
@@ -204,21 +204,21 @@ define i100 @v2i100(<2 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s100>) = G_BUILD_VECTOR [[TRUNC]](s100), [[TRUNC1]](s100)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s100>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x i100>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <2 x i100> %v, i32 1
ret i100 %r
@@ -229,25 +229,25 @@ define i100 @v3i100(<3 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](s64), [[COPY5]](s64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s100) = G_TRUNC [[MV2]](s128)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s100>) = G_BUILD_VECTOR [[TRUNC]](s100), [[TRUNC1]](s100), [[TRUNC2]](s100)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s100>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x i100>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <3 x i100> %v, i32 1
ret i100 %r
@@ -258,29 +258,29 @@ define i100 @v4i100(<4 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](s64), [[COPY5]](s64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s100) = G_TRUNC [[MV2]](s128)
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](s64), [[COPY7]](s64)
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s100) = G_TRUNC [[MV3]](s128)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s100>) = G_BUILD_VECTOR [[TRUNC]](s100), [[TRUNC1]](s100), [[TRUNC2]](s100), [[TRUNC3]](s100)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x s100>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](i64), [[COPY7]](i64)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i100) = G_TRUNC [[MV3]](s128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100), [[TRUNC3]](i100)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x i100>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <4 x i100> %v, i32 1
ret i100 %r
@@ -291,53 +291,53 @@ define i100 @v8i100(<8 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.7, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.7, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s64) from %fixed-stack.6)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i64) from %fixed-stack.6)
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (s64) from %fixed-stack.5, align 16)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (i64) from %fixed-stack.5, align 16)
; CHECK-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load (s64) from %fixed-stack.4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load (i64) from %fixed-stack.4)
; CHECK-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load (s64) from %fixed-stack.3, align 16)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load (i64) from %fixed-stack.3, align 16)
; CHECK-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load (s64) from %fixed-stack.2)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load (i64) from %fixed-stack.2)
; CHECK-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load (s64) from %fixed-stack.0)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](s64), [[COPY5]](s64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s100) = G_TRUNC [[MV2]](s128)
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](s64), [[COPY7]](s64)
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s100) = G_TRUNC [[MV3]](s128)
- ; CHECK-NEXT: [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](s64), [[LOAD1]](s64)
- ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s100) = G_TRUNC [[MV4]](s128)
- ; CHECK-NEXT: [[MV5:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD2]](s64), [[LOAD3]](s64)
- ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s100) = G_TRUNC [[MV5]](s128)
- ; CHECK-NEXT: [[MV6:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD4]](s64), [[LOAD5]](s64)
- ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s100) = G_TRUNC [[MV6]](s128)
- ; CHECK-NEXT: [[MV7:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD6]](s64), [[LOAD7]](s64)
- ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s100) = G_TRUNC [[MV7]](s128)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s100>) = G_BUILD_VECTOR [[TRUNC]](s100), [[TRUNC1]](s100), [[TRUNC2]](s100), [[TRUNC3]](s100), [[TRUNC4]](s100), [[TRUNC5]](s100), [[TRUNC6]](s100), [[TRUNC7]](s100)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<8 x s100>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load (i64) from %fixed-stack.0)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](i64), [[COPY7]](i64)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i100) = G_TRUNC [[MV3]](s128)
+ ; CHECK-NEXT: [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](i64), [[LOAD1]](i64)
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i100) = G_TRUNC [[MV4]](s128)
+ ; CHECK-NEXT: [[MV5:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD2]](i64), [[LOAD3]](i64)
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i100) = G_TRUNC [[MV5]](s128)
+ ; CHECK-NEXT: [[MV6:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD4]](i64), [[LOAD5]](i64)
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(i100) = G_TRUNC [[MV6]](s128)
+ ; CHECK-NEXT: [[MV7:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD6]](i64), [[LOAD7]](i64)
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(i100) = G_TRUNC [[MV7]](s128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100), [[TRUNC3]](i100), [[TRUNC4]](i100), [[TRUNC5]](i100), [[TRUNC6]](i100), [[TRUNC7]](i100)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<8 x i100>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <8 x i100> %v, i32 1
ret i100 %r
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
index c79093e37101d..50517866173f5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
@@ -6,12 +6,12 @@ define <2 x half> @f16_vec_param(<2 x half> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[UV]](<2 x s16>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV2]](s16), [[UV3]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[UV]](<2 x f16>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV2]](f16), [[UV3]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x f16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <2 x half> %v
}
@@ -21,10 +21,10 @@ define <2 x i16> @i16_vec_param(<2 x i16> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[TRUNC]](<2 x s16>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i16>) = G_TRUNC [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i32>) = G_ANYEXT [[TRUNC]](<2 x i16>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <2 x i16> %v
}
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
index bccb70ccd5c03..22f89a78c6eeb 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
@@ -10,9 +10,10 @@ define ptr @memset_tagged_0_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_0_zeroval:
; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: mov x8, xzr
-; GISel-O0-NEXT: setgp [x0]!, x8!, x8
-; GISel-O0-NEXT: setgm [x0]!, x8!, x8
-; GISel-O0-NEXT: setge [x0]!, x8!, x8
+; GISel-O0-NEXT: mov x9, xzr
+; GISel-O0-NEXT: setgp [x0]!, x8!, x9
+; GISel-O0-NEXT: setgm [x0]!, x8!, x9
+; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret
;
; GISel-LABEL: memset_tagged_0_zeroval:
@@ -38,7 +39,7 @@ entry:
define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_1_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #1
+; GISel-O0-NEXT: mov w8, #1 // =0x1
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -48,7 +49,7 @@ define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_1_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #1
+; GISel-NEXT: mov w8, #1 // =0x1
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -56,7 +57,7 @@ define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_1_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #1
+; SDAG-NEXT: mov w8, #1 // =0x1
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -69,7 +70,7 @@ entry:
define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10
+; GISel-O0-NEXT: mov w8, #10 // =0xa
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -79,7 +80,7 @@ define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_10_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10
+; GISel-NEXT: mov w8, #10 // =0xa
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -87,7 +88,7 @@ define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_10_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10
+; SDAG-NEXT: mov w8, #10 // =0xa
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -100,7 +101,7 @@ entry:
define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10000_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10000
+; GISel-O0-NEXT: mov w8, #10000 // =0x2710
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -110,7 +111,7 @@ define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_10000_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10000
+; GISel-NEXT: mov w8, #10000 // =0x2710
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -118,7 +119,7 @@ define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_10000_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10000
+; SDAG-NEXT: mov w8, #10000 // =0x2710
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -192,7 +193,7 @@ entry:
define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_1:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #1
+; GISel-O0-NEXT: mov w8, #1 // =0x1
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -203,7 +204,7 @@ define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_1:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #1
+; GISel-NEXT: mov w8, #1 // =0x1
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -212,7 +213,7 @@ define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_1:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #1
+; SDAG-NEXT: mov w8, #1 // =0x1
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
@@ -227,7 +228,7 @@ entry:
define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10
+; GISel-O0-NEXT: mov w8, #10 // =0xa
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -238,7 +239,7 @@ define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_10:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10
+; GISel-NEXT: mov w8, #10 // =0xa
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -247,7 +248,7 @@ define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_10:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10
+; SDAG-NEXT: mov w8, #10 // =0xa
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
@@ -262,7 +263,7 @@ entry:
define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10000:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10000
+; GISel-O0-NEXT: mov w8, #10000 // =0x2710
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -273,7 +274,7 @@ define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_10000:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10000
+; GISel-NEXT: mov w8, #10000 // =0x2710
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -282,7 +283,7 @@ define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_10000:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10000
+; SDAG-NEXT: mov w8, #10000 // =0x2710
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
diff --git a/llvm/test/CodeGen/AArch64/add.ll b/llvm/test/CodeGen/AArch64/add.ll
index 7502db4c5aa93..f2c7ca7bac03d 100644
--- a/llvm/test/CodeGen/AArch64/add.ll
+++ b/llvm/test/CodeGen/AArch64/add.ll
@@ -174,8 +174,7 @@ define void @v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/andorxor.ll b/llvm/test/CodeGen/AArch64/andorxor.ll
index d8d003c85eed6..f967bf2fbaefc 100644
--- a/llvm/test/CodeGen/AArch64/andorxor.ll
+++ b/llvm/test/CodeGen/AArch64/andorxor.ll
@@ -472,8 +472,7 @@ define void @and_v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
@@ -521,8 +520,7 @@ define void @or_v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
@@ -570,8 +568,7 @@ define void @xor_v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll b/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
index 07c4dbcf41096..16a53fa089857 100644
--- a/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
@@ -208,7 +208,8 @@ define <4 x i32> @sqxtn_ins(<4 x i32> noundef %a, i64 %c) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d1, x0
; CHECK-NEXT: sqxtn s1, d1
-; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret
entry:
%vqmovnd_s64.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %c)
@@ -221,7 +222,8 @@ define <4 x i32> @sqxtun_insext(<4 x i32> noundef %a, <2 x i64> %e) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: sqxtun s1, d1
-; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret
entry:
%c = extractelement <2 x i64> %e, i64 1
@@ -235,7 +237,8 @@ define <4 x i32> @saddluse(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 %c, f
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: saddlv d1, v1.4s
; CHECK-NEXT: sqxtn s1, d1
-; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: ret
entry:
%vaddlvq_s32.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %b)
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index a729772f2897a..58e8f27fb657a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -1,20 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK
-
-; CHECK-GI: warning: Instruction selection used fallback path for fptosi_i32_f16_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f16_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f32_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f64_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f64_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f32_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f16_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f16_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f32_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f64_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f64_simd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f32_simd
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-SD-FPRCVT
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-GI-FPRCVT
;
; FPTOI
@@ -27,10 +14,10 @@ define float @test_fptosi_f16_i32_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptosi_f16_i32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptosi_f16_i32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = fptosi half %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -43,10 +30,10 @@ define double @test_fptosi_f16_i64_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptosi_f16_i64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptosi_f16_i64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = fptosi half %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -59,10 +46,10 @@ define float @test_fptosi_f64_i32_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptosi_f64_i32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptosi_f64_i32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = fptosi double %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -75,21 +62,16 @@ define double @test_fptosi_f32_i64_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptosi_f32_i64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptosi_f32_i64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = fptosi float %a to i64
%bc = bitcast i64 %r to double
ret double %bc
}
define double @test_fptosi_f64_i64_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: test_fptosi_f64_i64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -101,11 +83,6 @@ define double @test_fptosi_f64_i64_simd(double %a) {
define float @test_fptosi_f32_i32_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: test_fptosi_f32_i32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -122,10 +99,10 @@ define float @test_fptoui_f16_i32_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptoui_f16_i32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptoui_f16_i32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = fptoui half %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -138,10 +115,10 @@ define double @test_fptoui_f16_i64_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptoui_f16_i64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptoui_f16_i64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = fptoui half %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -154,10 +131,10 @@ define float @test_fptoui_f64_i32_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptoui_f64_i32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptoui_f64_i32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = fptoui double %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -170,21 +147,16 @@ define double @test_fptoui_f32_i64_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptoui_f32_i64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptoui_f32_i64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = fptoui float %a to i64
%bc = bitcast i64 %r to double
ret double %bc
}
define double @test_fptoui_f64_i64_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: test_fptoui_f64_i64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
@@ -196,11 +168,6 @@ define double @test_fptoui_f64_i64_simd(double %a) {
define float @test_fptoui_f32_i32_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: test_fptoui_f32_i32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
@@ -222,10 +189,10 @@ define float @fptosi_i32_f16_simd(half %x) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fptosi_i32_f16_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fptosi_i32_f16_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
+; CHECK-FPRCVT-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i32 %val to float
ret float %sum
@@ -238,10 +205,10 @@ define double @fptosi_i64_f16_simd(half %x) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fptosi_i64_f16_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fptosi_i64_f16_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
+; CHECK-FPRCVT-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i64 %val to double
ret double %sum
@@ -254,10 +221,10 @@ define double @fptosi_i64_f32_simd(float %x) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fptosi_i64_f32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fptosi_i64_f32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
@@ -270,21 +237,16 @@ define float @fptosi_i32_f64_simd(double %x) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fptosi_i32_f64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fptosi_i32_f64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
}
define double @fptosi_i64_f64_simd(double %x) {
-; CHECK-NOFPRCVT-LABEL: fptosi_i64_f64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fptosi_i64_f64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -295,11 +257,6 @@ define double @fptosi_i64_f64_simd(double %x) {
}
define float @fptosi_i32_f32_simd(float %x) {
-; CHECK-NOFPRCVT-LABEL: fptosi_i32_f32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fptosi_i32_f32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -318,10 +275,10 @@ define float @fptoui_i32_f16_simd(half %x) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fptoui_i32_f16_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fptoui_i32_f16_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i32 %val to float
ret float %sum
@@ -334,10 +291,10 @@ define double @fptoui_i64_f16_simd(half %x) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fptoui_i64_f16_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fptoui_i64_f16_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i64 %val to double
ret double %sum
@@ -350,10 +307,10 @@ define double @fptoui_i64_f32_simd(float %x) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fptoui_i64_f32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fptoui_i64_f32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
@@ -366,21 +323,16 @@ define float @fptoui_i32_f64_simd(double %x) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fptoui_i32_f64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fptoui_i32_f64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
}
define double @fptoui_i64_f64_simd(double %x) {
-; CHECK-NOFPRCVT-LABEL: fptoui_i64_f64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fptoui_i64_f64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
@@ -391,11 +343,6 @@ define double @fptoui_i64_f64_simd(double %x) {
}
define float @fptoui_i32_f32_simd(float %x) {
-; CHECK-NOFPRCVT-LABEL: fptoui_i32_f32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fptoui_i32_f32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
@@ -417,10 +364,10 @@ define double @fcvtas_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -434,10 +381,10 @@ define float @fcvtas_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -445,11 +392,6 @@ define float @fcvtas_sd_round_simd(double %a) {
}
define float @fcvtas_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtas_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
@@ -461,11 +403,6 @@ define float @fcvtas_ss_round_simd(float %a) {
}
define double @fcvtas_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtas_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
@@ -484,10 +421,10 @@ define double @fcvtau_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -501,10 +438,10 @@ define float @fcvtau_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -512,11 +449,6 @@ define float @fcvtau_sd_round_simd(double %a) {
}
define float @fcvtau_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtau_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
@@ -528,11 +460,6 @@ define float @fcvtau_ss_round_simd(float %a) {
}
define double @fcvtau_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtau_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
@@ -551,10 +478,10 @@ define double @fcvtms_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -568,10 +495,10 @@ define float @fcvtms_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -579,11 +506,6 @@ define float @fcvtms_sd_round_simd(double %a) {
}
define float @fcvtms_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtms_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
@@ -595,11 +517,6 @@ define float @fcvtms_ss_round_simd(float %a) {
}
define double @fcvtms_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtms_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
@@ -619,10 +536,10 @@ define double @fcvtmu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -636,10 +553,10 @@ define float @fcvtmu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -647,11 +564,6 @@ define float @fcvtmu_sd_round_simd(double %a) {
}
define float @fcvtmu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtmu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
@@ -663,11 +575,6 @@ define float @fcvtmu_ss_round_simd(float %a) {
}
define double @fcvtmu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtmu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
@@ -686,10 +593,10 @@ define double @fcvtps_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -703,10 +610,10 @@ define float @fcvtps_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -714,11 +621,6 @@ define float @fcvtps_sd_round_simd(double %a) {
}
define float @fcvtps_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtps_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
@@ -730,11 +632,6 @@ define float @fcvtps_ss_round_simd(float %a) {
}
define double @fcvtps_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtps_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
@@ -753,10 +650,10 @@ define double @fcvtpu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -770,10 +667,10 @@ define float @fcvtpu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -781,11 +678,6 @@ define float @fcvtpu_sd_round_simd(double %a) {
}
define float @fcvtpu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtpu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
@@ -797,11 +689,6 @@ define float @fcvtpu_ss_round_simd(float %a) {
}
define double @fcvtpu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtpu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
@@ -820,10 +707,10 @@ define double @fcvtzs_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -837,10 +724,10 @@ define float @fcvtzs_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -848,11 +735,6 @@ define float @fcvtzs_sd_round_simd(double %a) {
}
define float @fcvtzs_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -864,11 +746,6 @@ define float @fcvtzs_ss_round_simd(float %a) {
}
define double @fcvtzs_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -886,10 +763,10 @@ define double @fcvtzu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -903,10 +780,10 @@ define float @fcvtzu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -914,11 +791,6 @@ define float @fcvtzu_sd_round_simd(double %a) {
}
define float @fcvtzu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -930,11 +802,6 @@ define float @fcvtzu_ss_round_simd(float %a) {
}
define double @fcvtzu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -957,10 +824,10 @@ define float @fcvtzs_sh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sh_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sh_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
+; CHECK-FPRCVT-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f16(half %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -973,10 +840,10 @@ define double @fcvtzs_dh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_dh_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_dh_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
+; CHECK-FPRCVT-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f16(half %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -989,10 +856,10 @@ define double @fcvtzs_ds_sat_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_ds_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_ds_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f32(float %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1005,21 +872,16 @@ define float @fcvtzs_sd_sat_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sd_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sd_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f64(double %a)
%bc = bitcast i32 %i to float
ret float %bc
}
define float @fcvtzs_ss_sat_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_ss_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -1030,11 +892,6 @@ define float @fcvtzs_ss_sat_simd(float %a) {
}
define double @fcvtzs_dd_sat_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_dd_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -1051,10 +908,10 @@ define float @fcvtzu_sh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sh_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sh_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%i = call i32 @llvm.fptoui.sat.i32.f16(half %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1067,10 +924,10 @@ define double @fcvtzu_dh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_dh_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_dh_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%i = call i64 @llvm.fptoui.sat.i64.f16(half %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1083,10 +940,10 @@ define double @fcvtzu_ds_sat_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_ds_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_ds_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%i = call i64 @llvm.fptoui.sat.i64.f32(float %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1099,21 +956,16 @@ define float @fcvtzu_sd_sat_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sd_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sd_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%i = call i32 @llvm.fptoui.sat.i32.f64(double %a)
%bc = bitcast i32 %i to float
ret float %bc
}
define float @fcvtzu_ss_sat_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_ss_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -1124,11 +976,6 @@ define float @fcvtzu_ss_sat_simd(float %a) {
}
define double @fcvtzu_dd_sat_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_dd_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -1149,10 +996,10 @@ define float @fcvtas_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.round.f16(half %a) nounwind readnone
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1166,10 +1013,10 @@ define double @fcvtas_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.round.f16(half %a) nounwind readnone
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1183,10 +1030,10 @@ define double @fcvtas_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1200,10 +1047,10 @@ define float @fcvtas_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1211,11 +1058,6 @@ define float @fcvtas_sd_simd(double %a) {
}
define float @fcvtas_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtas_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
@@ -1227,11 +1069,6 @@ define float @fcvtas_ss_simd(float %a) {
}
define double @fcvtas_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtas_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
@@ -1249,10 +1086,10 @@ define float @fcvtau_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.round.f16(half %a) nounwind readnone
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1266,10 +1103,10 @@ define double @fcvtau_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.round.f16(half %a) nounwind readnone
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1283,10 +1120,10 @@ define double @fcvtau_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1300,10 +1137,10 @@ define float @fcvtau_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1311,11 +1148,6 @@ define float @fcvtau_sd_simd(double %a) {
}
define float @fcvtau_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtau_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
@@ -1327,11 +1159,6 @@ define float @fcvtau_ss_simd(float %a) {
}
define double @fcvtau_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtau_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
@@ -1349,10 +1176,10 @@ define float @fcvtms_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.floor.f16(half %a) nounwind readnone
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1366,10 +1193,10 @@ define double @fcvtms_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.floor.f16(half %a) nounwind readnone
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1383,10 +1210,10 @@ define double @fcvtms_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1400,10 +1227,10 @@ define float @fcvtms_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1411,11 +1238,6 @@ define float @fcvtms_sd_simd(double %a) {
}
define float @fcvtms_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtms_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
@@ -1427,11 +1249,6 @@ define float @fcvtms_ss_simd(float %a) {
}
define double @fcvtms_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtms_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
@@ -1449,10 +1266,10 @@ define float @fcvtmu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.floor.f16(half %a) nounwind readnone
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1466,10 +1283,10 @@ define double @fcvtmu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.floor.f16(half %a) nounwind readnone
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1483,10 +1300,10 @@ define double @fcvtmu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1500,10 +1317,10 @@ define float @fcvtmu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1511,11 +1328,6 @@ define float @fcvtmu_sd_simd(double %a) {
}
define float @fcvtmu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtmu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
@@ -1527,11 +1339,6 @@ define float @fcvtmu_ss_simd(float %a) {
}
define double @fcvtmu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtmu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
@@ -1549,10 +1356,10 @@ define float @fcvtps_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.ceil.f16(half %a) nounwind readnone
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1566,10 +1373,10 @@ define double @fcvtps_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.ceil.f16(half %a) nounwind readnone
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1583,10 +1390,10 @@ define double @fcvtps_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1600,10 +1407,10 @@ define float @fcvtps_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1611,11 +1418,6 @@ define float @fcvtps_sd_simd(double %a) {
}
define float @fcvtps_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtps_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
@@ -1627,11 +1429,6 @@ define float @fcvtps_ss_simd(float %a) {
}
define double @fcvtps_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtps_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
@@ -1649,10 +1446,10 @@ define float @fcvtpu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.ceil.f16(half %a) nounwind readnone
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1666,10 +1463,10 @@ define double @fcvtpu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.ceil.f16(half %a) nounwind readnone
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1683,10 +1480,10 @@ define double @fcvtpu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1700,10 +1497,10 @@ define float @fcvtpu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1711,11 +1508,6 @@ define float @fcvtpu_sd_simd(double %a) {
}
define float @fcvtpu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtpu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
@@ -1727,11 +1519,6 @@ define float @fcvtpu_ss_simd(float %a) {
}
define double @fcvtpu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtpu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
@@ -1749,10 +1536,10 @@ define float @fcvtzs_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.trunc.f16(half %a) nounwind readnone
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1766,10 +1553,10 @@ define double @fcvtzs_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.trunc.f16(half %a) nounwind readnone
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1783,10 +1570,10 @@ define double @fcvtzs_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1800,10 +1587,10 @@ define float @fcvtzs_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1811,11 +1598,6 @@ define float @fcvtzs_sd_simd(double %a) {
}
define float @fcvtzs_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -1827,11 +1609,6 @@ define float @fcvtzs_ss_simd(float %a) {
}
define double @fcvtzs_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -1849,10 +1626,10 @@ define float @fcvtzu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.trunc.f16(half %a) nounwind readnone
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1866,10 +1643,10 @@ define double @fcvtzu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, h0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.trunc.f16(half %a) nounwind readnone
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1883,10 +1660,10 @@ define double @fcvtzu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1900,10 +1677,10 @@ define float @fcvtzu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1911,11 +1688,6 @@ define float @fcvtzu_sd_simd(double %a) {
}
define float @fcvtzu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
@@ -1927,11 +1699,6 @@ define float @fcvtzu_ss_simd(float %a) {
}
define double @fcvtzu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
@@ -1941,3 +1708,6 @@ define double @fcvtzu_dd_simd(double %a) {
%bc = bitcast i64 %i to double
ret double %bc
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI-FPRCVT: {{.*}}
+; CHECK-SD-FPRCVT: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index d8f370884c84a..071eb8f08cc42 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -2,11 +2,6 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for test_bitcastv2f32tov1f64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_bitcastv1f64tov2f32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_v1i32_undef
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_diff_v1i32_v1i32
-
define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
; CHECK-LABEL: ins16bw:
; CHECK: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll b/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
index f47c06e1ba4cb..7483eab10df65 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
%struct.uint8x16x2_t = type { [2 x <16 x i8>] }
@@ -296,18 +296,18 @@ entry:
define <1 x i64> @testDUP.v1i64(ptr %a, ptr %b) #0 {
; As there is a store operation depending on %1, LD1R pattern can't be selected.
; So LDR and FMOV should be emitted.
-; CHECK-GI-LABEL: testDUP.v1i64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr x8, [x0]
-; CHECK-GI-NEXT: fmov d0, x8
-; CHECK-GI-NEXT: str x8, [x1]
-; CHECK-GI-NEXT: ret
-;
; CHECK-SD-LABEL: testDUP.v1i64:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldr d0, [x0]
-; CHECK-SD-NEXT: str d0, [x1]
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: str x8, [x1]
; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testDUP.v1i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: str d0, [x1]
+; CHECK-GI-NEXT: ret
%1 = load i64, ptr %a, align 8
store i64 %1, ptr %b, align 8
%vecinit.i = insertelement <1 x i64> undef, i64 %1, i32 0
@@ -614,16 +614,16 @@ entry:
}
define void @test_vst1_lane0_s16(ptr %a, <4 x i16> %b) {
-; CHECK-GI-LABEL: test_vst1_lane0_s16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: str h0, [x0]
-; CHECK-GI-NEXT: ret
-;
; CHECK-SD-LABEL: test_vst1_lane0_s16:
; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: str h0, [x0]
; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vst1_lane0_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str h0, [x0]
+; CHECK-GI-NEXT: ret
entry:
%0 = extractelement <4 x i16> %b, i32 0
store i16 %0, ptr %a, align 2
@@ -643,16 +643,16 @@ entry:
}
define void @test_vst1_lane0_s32(ptr %a, <2 x i32> %b) {
-; CHECK-GI-LABEL: test_vst1_lane0_s32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: str s0, [x0]
-; CHECK-GI-NEXT: ret
-;
; CHECK-SD-LABEL: test_vst1_lane0_s32:
; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vst1_lane0_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str s0, [x0]
+; CHECK-GI-NEXT: ret
entry:
%0 = extractelement <2 x i32> %b, i32 0
store i32 %0, ptr %a, align 4
@@ -683,16 +683,16 @@ entry:
}
define void @test_vst1_lane0_f32(ptr %a, <2 x float> %b) {
-; CHECK-GI-LABEL: test_vst1_lane0_f32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: str s0, [x0]
-; CHECK-GI-NEXT: ret
-;
; CHECK-SD-LABEL: test_vst1_lane0_f32:
; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vst1_lane0_f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str s0, [x0]
+; CHECK-GI-NEXT: ret
entry:
%0 = extractelement <2 x float> %b, i32 0
store float %0, ptr %a, align 4
diff --git a/llvm/test/CodeGen/AArch64/arm64-smaxv.ll b/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
index cae7c99558c75..ba8cb7b684961 100644
--- a/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
@@ -1,12 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
; RUN: llc < %s -global-isel=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {
-; CHECK: test_vmaxv_s8
-; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxv_s8:
+; CHECK: smaxv.8b b0, v0
+; CHECK-NEXT: smov.b w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
%0 = trunc i32 %vmaxv.i to i8
@@ -14,10 +15,10 @@ entry:
}
define signext i16 @test_vmaxv_s16(<4 x i16> %a1) {
-; CHECK: test_vmaxv_s16
-; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxv_s16:
+; CHECK: smaxv.4h h0, v0
+; CHECK-NEXT: smov.h w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
%0 = trunc i32 %vmaxv.i to i16
@@ -25,21 +26,21 @@ entry:
}
define i32 @test_vmaxv_s32(<2 x i32> %a1) {
-; CHECK: test_vmaxv_s32
+; CHECK-LABEL: test_vmaxv_s32:
+; CHECK: smaxp.2s v0, v0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
; 2 x i32 is not supported by the ISA, thus, this is a special case
-; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v0, v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
ret i32 %vmaxv.i
}
define signext i8 @test_vmaxvq_s8(<16 x i8> %a1) {
-; CHECK: test_vmaxvq_s8
-; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxvq_s8:
+; CHECK: smaxv.16b b0, v0
+; CHECK-NEXT: smov.b w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
%0 = trunc i32 %vmaxv.i to i8
@@ -47,10 +48,10 @@ entry:
}
define signext i16 @test_vmaxvq_s16(<8 x i16> %a1) {
-; CHECK: test_vmaxvq_s16
-; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxvq_s16:
+; CHECK: smaxv.8h h0, v0
+; CHECK-NEXT: smov.h w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
%0 = trunc i32 %vmaxv.i to i16
@@ -58,10 +59,10 @@ entry:
}
define i32 @test_vmaxvq_s32(<4 x i32> %a1) {
-; CHECK: test_vmaxvq_s32
-; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
-; CHECK-NEXT: fmov w0, [[REGNUM]]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxvq_s32:
+; CHECK: smaxv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a1)
ret i32 %vmaxv.i
@@ -69,9 +70,9 @@ entry:
define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:
-; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.8b b1, v1
+; CHECK-NEXT: mov.b v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -81,9 +82,9 @@ entry:
define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:
-; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.4h h1, v1
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -93,9 +94,9 @@ entry:
define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:
-; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxp.2s v1, v1, v1
+; CHECK-NEXT: mov.s v0[1], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2)
%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
@@ -104,9 +105,9 @@ entry:
define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:
-; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.16b b1, v1
+; CHECK-NEXT: mov.b v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -116,9 +117,9 @@ entry:
define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop:
-; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.8h h1, v1
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -128,9 +129,9 @@ entry:
define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop:
-; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.4s s1, v1
+; CHECK-NEXT: mov.s v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2)
%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
diff --git a/llvm/test/CodeGen/AArch64/arm64-sminv.ll b/llvm/test/CodeGen/AArch64/arm64-sminv.ll
index 683044c9e8e0b..6d27249c32432 100644
--- a/llvm/test/CodeGen/AArch64/arm64-sminv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-sminv.ll
@@ -1,11 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
; RUN: llc < %s -global-isel=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define signext i8 @test_vminv_s8(<8 x i8> %a1) {
-; CHECK: test_vminv_s8
-; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminv_s8:
+; CHECK: sminv.8b b0, v0
+; CHECK-NEXT: smov.b w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
%0 = trunc i32 %vminv.i to i8
@@ -13,10 +14,10 @@ entry:
}
define signext i16 @test_vminv_s16(<4 x i16> %a1) {
-; CHECK: test_vminv_s16
-; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminv_s16:
+; CHECK: sminv.4h h0, v0
+; CHECK-NEXT: smov.h w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
%0 = trunc i32 %vminv.i to i16
@@ -24,21 +25,21 @@ entry:
}
define i32 @test_vminv_s32(<2 x i32> %a1) {
-; CHECK: test_vminv_s32
+; CHECK-LABEL: test_vminv_s32:
+; CHECK: sminp.2s v0, v0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
; 2 x i32 is not supported by the ISA, thus, this is a special case
-; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
ret i32 %vminv.i
}
define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
-; CHECK: test_vminvq_s8
-; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminvq_s8:
+; CHECK: sminv.16b b0, v0
+; CHECK-NEXT: smov.b w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
%0 = trunc i32 %vminv.i to i8
@@ -46,10 +47,10 @@ entry:
}
define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
-; CHECK: test_vminvq_s16
-; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminvq_s16:
+; CHECK: sminv.8h h0, v0
+; CHECK-NEXT: smov.h w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
%0 = trunc i32 %vminv.i to i16
@@ -57,10 +58,10 @@ entry:
}
define i32 @test_vminvq_s32(<4 x i32> %a1) {
-; CHECK: test_vminvq_s32
-; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
-; CHECK-NEXT: fmov w0, [[REGNUM]]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminvq_s32:
+; CHECK: sminv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)
ret i32 %vminv.i
@@ -68,9 +69,9 @@ entry:
define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
; CHECK-LABEL: test_vminv_s8_used_by_laneop:
-; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.8b b1, v1
+; CHECK-NEXT: mov.b v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -80,9 +81,9 @@ entry:
define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: test_vminv_s16_used_by_laneop:
-; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.4h h1, v1
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -92,9 +93,9 @@ entry:
define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
; CHECK-LABEL: test_vminv_s32_used_by_laneop:
-; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminp.2s v1, v1, v1
+; CHECK-NEXT: mov.s v0[1], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
@@ -103,9 +104,9 @@ entry:
define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
-; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.16b b1, v1
+; CHECK-NEXT: mov.b v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -115,9 +116,9 @@ entry:
define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
-; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.8h h1, v1
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -127,9 +128,9 @@ entry:
define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
-; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.4s s1, v1
+; CHECK-NEXT: mov.s v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
diff --git a/llvm/test/CodeGen/AArch64/arm64-this-return.ll b/llvm/test/CodeGen/AArch64/arm64-this-return.ll
index 7dd47acbc6f88..ed2fb4d296adc 100644
--- a/llvm/test/CodeGen/AArch64/arm64-this-return.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-this-return.ll
@@ -1,6 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=1 -stop-after=irtranslator | FileCheck %s --check-prefix=GISEL-MIR
%struct.A = type { i8 }
@@ -20,23 +18,19 @@ declare ptr @B_ctor_complete_nothisret(ptr, i32)
define ptr @C_ctor_base(ptr returned %this, i32 %x) {
; GISEL-MIR-LABEL: name: C_ctor_base
; GISEL-MIR: bb.1.entry:
- ; GISEL-MIR: liveins: $w1, $x0
- ; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: BL @A_ctor_base, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0
- ; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
- ; GISEL-MIR: TCRETURNdi @B_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
+ ; GISEL-MIR-NEXT: liveins: $w1, $x0
+ ; GISEL-MIR-NEXT: {{ $}}
+ ; GISEL-MIR-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; GISEL-MIR-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: BL @A_ctor_base, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0
+ ; GISEL-MIR-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $w1 = COPY [[COPY1]](i32)
+ ; GISEL-MIR-NEXT: TCRETURNdi @B_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
entry:
-; CHECK-LABEL: C_ctor_base:
-; CHECK-NOT: mov {{x[0-9]+}}, x0
-; CHECK: bl {{_?A_ctor_base}}
-; CHECK-NOT: mov x0, {{x[0-9]+}}
-; CHECK: b {{_?B_ctor_base}}
%call = tail call ptr @A_ctor_base(ptr returned %this)
%call2 = tail call ptr @B_ctor_base(ptr returned %this, i32 %x)
ret ptr %this
@@ -45,28 +39,24 @@ entry:
define ptr @C_ctor_base_nothisret(ptr %this, i32 %x) {
; GISEL-MIR-LABEL: name: C_ctor_base_nothisret
; GISEL-MIR: bb.1.entry:
- ; GISEL-MIR: liveins: $w1, $x0
- ; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: BL @A_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $x0
- ; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
- ; GISEL-MIR: BL @B_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
- ; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: RET_ReallyLR implicit $x0
+ ; GISEL-MIR-NEXT: liveins: $w1, $x0
+ ; GISEL-MIR-NEXT: {{ $}}
+ ; GISEL-MIR-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; GISEL-MIR-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: BL @A_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $x0
+ ; GISEL-MIR-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $w1 = COPY [[COPY1]](i32)
+ ; GISEL-MIR-NEXT: BL @B_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
+ ; GISEL-MIR-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: RET_ReallyLR implicit $x0
entry:
-; CHECK-LABEL: C_ctor_base_nothisret:
-; CHECK: mov [[SAVETHIS:x[0-9]+]], x0
-; CHECK: bl {{_?A_ctor_base_nothisret}}
-; CHECK: mov x0, [[SAVETHIS]]
-; CHECK-NOT: b {{_?B_ctor_base_nothisret}}
%call = tail call ptr @A_ctor_base_nothisret(ptr %this)
%call2 = tail call ptr @B_ctor_base_nothisret(ptr %this, i32 %x)
ret ptr %this
@@ -75,15 +65,14 @@ entry:
define ptr @C_ctor_complete(ptr %this, i32 %x) {
; GISEL-MIR-LABEL: name: C_ctor_complete
; GISEL-MIR: bb.1.entry:
- ; GISEL-MIR: liveins: $w1, $x0
- ; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
- ; GISEL-MIR: TCRETURNdi @C_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
+ ; GISEL-MIR-NEXT: liveins: $w1, $x0
+ ; GISEL-MIR-NEXT: {{ $}}
+ ; GISEL-MIR-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $w1 = COPY [[COPY1]](i32)
+ ; GISEL-MIR-NEXT: TCRETURNdi @C_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
entry:
-; CHECK-LABEL: C_ctor_complete:
-; CHECK: b {{_?C_ctor_base}}
%call = tail call ptr @C_ctor_base(ptr returned %this, i32 %x)
ret ptr %this
}
@@ -91,20 +80,19 @@ entry:
define ptr @C_ctor_complete_nothisret(ptr %this, i32 %x) {
; GISEL-MIR-LABEL: name: C_ctor_complete_nothisret
; GISEL-MIR: bb.1.entry:
- ; GISEL-MIR: liveins: $w1, $x0
- ; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
- ; GISEL-MIR: BL @C_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
- ; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: RET_ReallyLR implicit $x0
+ ; GISEL-MIR-NEXT: liveins: $w1, $x0
+ ; GISEL-MIR-NEXT: {{ $}}
+ ; GISEL-MIR-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; GISEL-MIR-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $w1 = COPY [[COPY1]](i32)
+ ; GISEL-MIR-NEXT: BL @C_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
+ ; GISEL-MIR-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: RET_ReallyLR implicit $x0
entry:
-; CHECK-LABEL: C_ctor_complete_nothisret:
-; CHECK-NOT: b {{_?C_ctor_base_nothisret}}
%call = tail call ptr @C_ctor_base_nothisret(ptr %this, i32 %x)
ret ptr %this
}
@@ -112,24 +100,20 @@ entry:
define ptr @D_ctor_base(ptr %this, i32 %x) {
; GISEL-MIR-LABEL: name: D_ctor_base
; GISEL-MIR: bb.1.entry:
- ; GISEL-MIR: liveins: $w1, $x0
- ; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
- ; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
- ; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
- ; GISEL-MIR: TCRETURNdi @B_ctor_complete, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
+ ; GISEL-MIR-NEXT: liveins: $w1, $x0
+ ; GISEL-MIR-NEXT: {{ $}}
+ ; GISEL-MIR-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; GISEL-MIR-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $w1 = COPY [[COPY1]](i32)
+ ; GISEL-MIR-NEXT: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
+ ; GISEL-MIR-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $w1 = COPY [[COPY1]](i32)
+ ; GISEL-MIR-NEXT: TCRETURNdi @B_ctor_complete, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
entry:
-; CHECK-LABEL: D_ctor_base:
-; CHECK-NOT: mov {{x[0-9]+}}, x0
-; CHECK: bl {{_?B_ctor_complete}}
-; CHECK-NOT: mov x0, {{x[0-9]+}}
-; CHECK: b {{_?B_ctor_complete}}
%call = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
%call2 = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
ret ptr %this
@@ -138,28 +122,27 @@ entry:
define ptr @E_ctor_base(ptr %this, i32 %x) {
; GISEL-MIR-LABEL: name: E_ctor_base
; GISEL-MIR: bb.1.entry:
- ; GISEL-MIR: liveins: $w1, $x0
- ; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
- ; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
- ; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
- ; GISEL-MIR: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; GISEL-MIR: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: $x0 = COPY [[PTR_ADD]](p0)
- ; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
- ; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
- ; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; GISEL-MIR: [[COPY3:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; GISEL-MIR: $x0 = COPY [[COPY]](p0)
- ; GISEL-MIR: RET_ReallyLR implicit $x0
+ ; GISEL-MIR-NEXT: liveins: $w1, $x0
+ ; GISEL-MIR-NEXT: {{ $}}
+ ; GISEL-MIR-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; GISEL-MIR-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; GISEL-MIR-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: $w1 = COPY [[COPY1]](i32)
+ ; GISEL-MIR-NEXT: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
+ ; GISEL-MIR-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; GISEL-MIR-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
+ ; GISEL-MIR-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: $x0 = COPY [[PTR_ADD]](p0)
+ ; GISEL-MIR-NEXT: $w1 = COPY [[COPY1]](i32)
+ ; GISEL-MIR-NEXT: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
+ ; GISEL-MIR-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
+ ; GISEL-MIR-NEXT: $x0 = COPY [[COPY]](p0)
+ ; GISEL-MIR-NEXT: RET_ReallyLR implicit $x0
entry:
-; CHECK-LABEL: E_ctor_base:
-; CHECK-NOT: b {{_?B_ctor_complete}}
%call = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
%b2 = getelementptr inbounds %struct.E, ptr %this, i32 0, i32 1
%call2 = tail call ptr @B_ctor_complete(ptr returned %b2, i32 %x)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vaddv.ll b/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
index d60b6d7097308..6d6484a584d81 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
; CHECK-LABEL: test_vaddv_s8:
@@ -451,3 +451,6 @@ declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
declare float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)
declare float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)
declare double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/bf16-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
index c965d11ffc2e0..f5b0fbc2ccf30 100644
--- a/llvm/test/CodeGen/AArch64/bf16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
@@ -3,82 +3,6 @@
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=CHECK,CHECK-BF16,CHECK-SD
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+bf16,+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-BF16,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for test_fadd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fsub
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fmul
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fmadd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fdiv
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_frem
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_call
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_call_flipped
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_tailcall_flipped
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_select_cc
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_select_cc_f32_f16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_une
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_ueq
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_ugt
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_uge
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_ult
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_ule
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_uno
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_one
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_oeq
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_ogt
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_oge
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_olt
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_ole
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_ord
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fccmp
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_br_cc
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fptosi_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fptosi_i64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fptoui_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fptoui_i64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uitofp_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uitofp_i64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sitofp_i32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sitofp_i64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uitofp_i32_fadd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sitofp_i32_fadd
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fptrunc_float
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fptrunc_double
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fpext_float
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fpext_double
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrt
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_powi
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sin
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_cos
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_tan
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_acos
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_asin
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_atan
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_atan2
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_cosh
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sinh
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_tanh
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_pow
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_exp
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_exp2
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_log
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_log10
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_log2
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fma
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fabs
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_minnum
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_maxnum
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_copysign
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_f32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_f64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_extended
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_floor
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_ceil
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_trunc
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_rint
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_nearbyint
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_round
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_roundeven
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_fmuladd
-
define bfloat @test_fadd(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-LABEL: test_fadd:
; CHECK-CVT: // %bb.0:
@@ -97,15 +21,25 @@ define bfloat @test_fadd(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_fadd:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fadd s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_fadd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fadd s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fadd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fadd s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = fadd bfloat %a, %b
ret bfloat %r
}
@@ -128,15 +62,25 @@ define bfloat @test_fsub(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_fsub:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fsub s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_fsub:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fsub s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fsub:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fsub s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = fsub bfloat %a, %b
ret bfloat %r
}
@@ -159,15 +103,25 @@ define bfloat @test_fmul(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_fmul:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fmul s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_fmul:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fmul s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fmul:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fmul s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = fmul bfloat %a, %b
ret bfloat %r
}
@@ -200,17 +154,32 @@ define bfloat @test_fmadd(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_fmadd:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: shll v2.4s, v2.4h, #16
-; CHECK-BF16-NEXT: fmadd s0, s0, s1, s2
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_fmadd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: shll v2.4s, v2.4h, #16
+; CHECK-SD-NEXT: fmadd s0, s0, s1, s2
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fmadd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fmul s0, s0, s1
+; CHECK-GI-NEXT: shll v1.4s, v2.4h, #16
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: fadd s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%mul = fmul fast bfloat %a, %b
%r = fadd fast bfloat %mul, %c
ret bfloat %r
@@ -234,15 +203,25 @@ define bfloat @test_fdiv(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_fdiv:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fdiv s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_fdiv:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fdiv s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fdiv:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fdiv s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = fdiv bfloat %a, %b
ret bfloat %r
}
@@ -269,19 +248,33 @@ define bfloat @test_frem(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_frem:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1
-; CHECK-BF16-NEXT: bl fmodf
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_frem:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-SD-NEXT: // kill: def $s1 killed $s1 killed $q1
+; CHECK-SD-NEXT: bl fmodf
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_frem:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: // kill: def $s1 killed $s1 killed $q1
+; CHECK-GI-NEXT: bl fmodf
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
%r = frem bfloat %a, %b
ret bfloat %r
}
@@ -405,12 +398,18 @@ define bfloat @test_select_cc(bfloat %a, bfloat %b, bfloat %c, bfloat %d) #0 {
;
; CHECK-GI-LABEL: test_select_cc:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: // kill: def $h3 killed $h3 def $d3
; CHECK-GI-NEXT: // kill: def $h2 killed $h2 def $d2
-; CHECK-GI-NEXT: shll v3.4s, v3.4h, #16
+; CHECK-GI-NEXT: // kill: def $h3 killed $h3 def $d3
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $s0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $s1
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: shll v2.4s, v2.4h, #16
+; CHECK-GI-NEXT: shll v3.4s, v3.4h, #16
; CHECK-GI-NEXT: fcmp s2, s3
-; CHECK-GI-NEXT: fcsel h0, h0, h1, ne
+; CHECK-GI-NEXT: csel w8, w8, w9, ne
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-GI-NEXT: ret
%cc = fcmp une bfloat %c, %d
%r = select i1 %cc, bfloat %a, bfloat %b
@@ -418,15 +417,35 @@ define bfloat @test_select_cc(bfloat %a, bfloat %b, bfloat %c, bfloat %d) #0 {
}
define float @test_select_cc_f32_f16(float %a, float %b, bfloat %c, bfloat %d) #0 {
-; CHECK-LABEL: test_select_cc_f32_f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h3 killed $h3 def $d3
-; CHECK-NEXT: // kill: def $h2 killed $h2 def $d2
-; CHECK-NEXT: shll v3.4s, v3.4h, #16
-; CHECK-NEXT: shll v2.4s, v2.4h, #16
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: fcsel s0, s0, s1, ne
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_select_cc_f32_f16:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h3 killed $h3 def $d3
+; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-CVT-NEXT: shll v3.4s, v3.4h, #16
+; CHECK-CVT-NEXT: shll v2.4s, v2.4h, #16
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: fcsel s0, s0, s1, ne
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_select_cc_f32_f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h3 killed $h3 def $d3
+; CHECK-SD-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-SD-NEXT: shll v3.4s, v3.4h, #16
+; CHECK-SD-NEXT: shll v2.4s, v2.4h, #16
+; CHECK-SD-NEXT: fcmp s2, s3
+; CHECK-SD-NEXT: fcsel s0, s0, s1, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_select_cc_f32_f16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-GI-NEXT: // kill: def $h3 killed $h3 def $d3
+; CHECK-GI-NEXT: shll v2.4s, v2.4h, #16
+; CHECK-GI-NEXT: shll v3.4s, v3.4h, #16
+; CHECK-GI-NEXT: fcmp s2, s3
+; CHECK-GI-NEXT: fcsel s0, s0, s1, ne
+; CHECK-GI-NEXT: ret
%cc = fcmp une bfloat %c, %d
%r = select i1 %cc, float %a, float %b
ret float %r
@@ -468,199 +487,485 @@ define bfloat @test_select_cc_f16_f32(bfloat %a, bfloat %b, float %c, float %d)
}
define i1 @test_fcmp_une(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_une:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, ne
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_une:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, ne
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_une:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_une:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, ne
+; CHECK-GI-NEXT: ret
%r = fcmp une bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_ueq(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_ueq:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w8, eq
-; CHECK-NEXT: csinc w0, w8, wzr, vc
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ueq:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w8, eq
+; CHECK-CVT-NEXT: csinc w0, w8, wzr, vc
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_ueq:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w8, eq
+; CHECK-SD-NEXT: csinc w0, w8, wzr, vc
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_ueq:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w8, eq
+; CHECK-GI-NEXT: cset w9, vs
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%r = fcmp ueq bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_ugt(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_ugt:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, hi
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ugt:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, hi
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_ugt:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_ugt:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, hi
+; CHECK-GI-NEXT: ret
%r = fcmp ugt bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_uge(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_uge:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, pl
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_uge:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, pl
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_uge:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, pl
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_uge:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, pl
+; CHECK-GI-NEXT: ret
%r = fcmp uge bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_ult(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_ult:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, lt
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ult:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, lt
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_ult:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_ult:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, lt
+; CHECK-GI-NEXT: ret
%r = fcmp ult bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_ule(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_ule:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, le
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ule:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, le
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_ule:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, le
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_ule:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, le
+; CHECK-GI-NEXT: ret
%r = fcmp ule bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_uno(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_uno:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, vs
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_uno:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, vs
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_uno:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, vs
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_uno:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, vs
+; CHECK-GI-NEXT: ret
%r = fcmp uno bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_one(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_one:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w8, mi
-; CHECK-NEXT: csinc w0, w8, wzr, le
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_one:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w8, mi
+; CHECK-CVT-NEXT: csinc w0, w8, wzr, le
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_one:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w8, mi
+; CHECK-SD-NEXT: csinc w0, w8, wzr, le
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_one:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w8, mi
+; CHECK-GI-NEXT: cset w9, gt
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%r = fcmp one bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_oeq(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_oeq:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, eq
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_oeq:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, eq
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_oeq:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, eq
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_oeq:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, eq
+; CHECK-GI-NEXT: ret
%r = fcmp oeq bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_ogt(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_ogt:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, gt
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ogt:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, gt
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_ogt:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_ogt:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, gt
+; CHECK-GI-NEXT: ret
%r = fcmp ogt bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_oge(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_oge:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, ge
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_oge:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, ge
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_oge:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, ge
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_oge:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, ge
+; CHECK-GI-NEXT: ret
%r = fcmp oge bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_olt(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_olt:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, mi
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_olt:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, mi
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_olt:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, mi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_olt:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, mi
+; CHECK-GI-NEXT: ret
%r = fcmp olt bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_ole(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_ole:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, ls
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ole:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, ls
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_ole:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, ls
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_ole:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
%r = fcmp ole bfloat %a, %b
ret i1 %r
}
define i1 @test_fcmp_ord(bfloat %a, bfloat %b) #0 {
-; CHECK-LABEL: test_fcmp_ord:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset w0, vc
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ord:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset w0, vc
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_fcmp_ord:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: cset w0, vc
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fcmp_ord:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: cset w0, vc
+; CHECK-GI-NEXT: ret
%r = fcmp ord bfloat %a, %b
ret i1 %r
}
@@ -700,11 +1005,14 @@ define void @test_fccmp(bfloat %in, ptr %out) {
; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
; CHECK-GI-NEXT: shll v2.4s, v0.4h, #16
; CHECK-GI-NEXT: movi v3.2s, #72, lsl #24
+; CHECK-GI-NEXT: shll v4.4s, v0.4h, #16
+; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: fcmp s2, s1
; CHECK-GI-NEXT: fmov h1, #5.00000000
-; CHECK-GI-NEXT: fccmp s2, s3, #4, mi
-; CHECK-GI-NEXT: fcsel h0, h0, h1, gt
-; CHECK-GI-NEXT: str h0, [x0]
+; CHECK-GI-NEXT: fccmp s4, s3, #4, mi
+; CHECK-GI-NEXT: fmov w9, s1
+; CHECK-GI-NEXT: csel w8, w8, w9, gt
+; CHECK-GI-NEXT: strh w8, [x0]
; CHECK-GI-NEXT: ret
%cmp1 = fcmp ogt bfloat %in, 0xR4800
%cmp2 = fcmp olt bfloat %in, 0xR4500
@@ -715,16 +1023,38 @@ define void @test_fccmp(bfloat %in, ptr %out) {
}
define void @test_br_cc(bfloat %a, bfloat %b, ptr %p1, ptr %p2) #0 {
-; CHECK-LABEL: test_br_cc:
-; CHECK: // %bb.0: // %common.ret
-; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csel x8, x0, x1, pl
-; CHECK-NEXT: str wzr, [x8]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_br_cc:
+; CHECK-CVT: // %bb.0: // %common.ret
+; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: csel x8, x0, x1, pl
+; CHECK-CVT-NEXT: str wzr, [x8]
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-SD-LABEL: test_br_cc:
+; CHECK-SD: // %bb.0: // %common.ret
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcmp s0, s1
+; CHECK-SD-NEXT: csel x8, x0, x1, pl
+; CHECK-SD-NEXT: str wzr, [x8]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_br_cc:
+; CHECK-GI: // %bb.0: // %common.ret
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fcmp s0, s1
+; CHECK-GI-NEXT: csel x8, x0, x1, pl
+; CHECK-GI-NEXT: str wzr, [x8]
+; CHECK-GI-NEXT: ret
%c = fcmp uge bfloat %a, %b
br i1 %c, label %then, label %else
then:
@@ -827,12 +1157,18 @@ define bfloat @test_uitofp_i32(i32 %a) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_uitofp_i32:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: ucvtf d0, w0
-; CHECK-BF16-NEXT: fcvtxn s0, d0
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_uitofp_i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ucvtf d0, w0
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_uitofp_i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ucvtf s0, w0
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = uitofp i32 %a to bfloat
ret bfloat %r
}
@@ -862,22 +1198,28 @@ define bfloat @test_uitofp_i64(i64 %a) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_uitofp_i64:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: lsr x8, x0, #53
-; CHECK-BF16-NEXT: and x9, x0, #0xfffffffffffff000
-; CHECK-BF16-NEXT: cmp x8, #0
-; CHECK-BF16-NEXT: csel x8, x9, x0, ne
-; CHECK-BF16-NEXT: ucvtf d0, x8
-; CHECK-BF16-NEXT: cset w8, ne
-; CHECK-BF16-NEXT: tst x0, #0xfff
-; CHECK-BF16-NEXT: csel w8, wzr, w8, eq
-; CHECK-BF16-NEXT: fmov x9, d0
-; CHECK-BF16-NEXT: orr x8, x9, x8
-; CHECK-BF16-NEXT: fmov d0, x8
-; CHECK-BF16-NEXT: fcvtxn s0, d0
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_uitofp_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsr x8, x0, #53
+; CHECK-SD-NEXT: and x9, x0, #0xfffffffffffff000
+; CHECK-SD-NEXT: cmp x8, #0
+; CHECK-SD-NEXT: csel x8, x9, x0, ne
+; CHECK-SD-NEXT: ucvtf d0, x8
+; CHECK-SD-NEXT: cset w8, ne
+; CHECK-SD-NEXT: tst x0, #0xfff
+; CHECK-SD-NEXT: csel w8, wzr, w8, eq
+; CHECK-SD-NEXT: fmov x9, d0
+; CHECK-SD-NEXT: orr x8, x9, x8
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_uitofp_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ucvtf s0, x0
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = uitofp i64 %a to bfloat
ret bfloat %r
}
@@ -897,12 +1239,18 @@ define bfloat @test_sitofp_i32(i32 %a) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_sitofp_i32:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: scvtf d0, w0
-; CHECK-BF16-NEXT: fcvtxn s0, d0
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_sitofp_i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: scvtf d0, w0
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sitofp_i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: scvtf s0, w0
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = sitofp i32 %a to bfloat
ret bfloat %r
}
@@ -936,26 +1284,32 @@ define bfloat @test_sitofp_i64(i64 %a) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_sitofp_i64:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: cmp x0, #0
-; CHECK-BF16-NEXT: cneg x8, x0, mi
-; CHECK-BF16-NEXT: lsr x9, x8, #53
-; CHECK-BF16-NEXT: and x10, x8, #0xfffffffffffff000
-; CHECK-BF16-NEXT: cmp x9, #0
-; CHECK-BF16-NEXT: csel x9, x10, x8, ne
-; CHECK-BF16-NEXT: and x10, x0, #0x8000000000000000
-; CHECK-BF16-NEXT: cset w11, ne
-; CHECK-BF16-NEXT: scvtf d0, x9
-; CHECK-BF16-NEXT: tst x8, #0xfff
-; CHECK-BF16-NEXT: fmov x9, d0
-; CHECK-BF16-NEXT: orr x8, x9, x10
-; CHECK-BF16-NEXT: csel w9, wzr, w11, eq
-; CHECK-BF16-NEXT: orr x8, x8, x9
-; CHECK-BF16-NEXT: fmov d0, x8
-; CHECK-BF16-NEXT: fcvtxn s0, d0
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_sitofp_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmp x0, #0
+; CHECK-SD-NEXT: cneg x8, x0, mi
+; CHECK-SD-NEXT: lsr x9, x8, #53
+; CHECK-SD-NEXT: and x10, x8, #0xfffffffffffff000
+; CHECK-SD-NEXT: cmp x9, #0
+; CHECK-SD-NEXT: csel x9, x10, x8, ne
+; CHECK-SD-NEXT: and x10, x0, #0x8000000000000000
+; CHECK-SD-NEXT: cset w11, ne
+; CHECK-SD-NEXT: scvtf d0, x9
+; CHECK-SD-NEXT: tst x8, #0xfff
+; CHECK-SD-NEXT: fmov x9, d0
+; CHECK-SD-NEXT: orr x8, x9, x10
+; CHECK-SD-NEXT: csel w9, wzr, w11, eq
+; CHECK-SD-NEXT: orr x8, x8, x9
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sitofp_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: scvtf s0, x0
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = sitofp i64 %a to bfloat
ret bfloat %r
}
@@ -985,17 +1339,28 @@ define bfloat @test_uitofp_i32_fadd(i32 %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_uitofp_i32_fadd:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: ucvtf d1, w0
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fcvtxn s1, d1
-; CHECK-BF16-NEXT: bfcvt h1, s1
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: fadd s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_uitofp_i32_fadd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ucvtf d1, w0
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcvtxn s1, d1
+; CHECK-SD-NEXT: bfcvt h1, s1
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: fadd s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_uitofp_i32_fadd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ucvtf s1, w0
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: bfcvt h1, s1
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fadd s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%c = uitofp i32 %a to bfloat
%r = fadd bfloat %b, %c
ret bfloat %r
@@ -1026,17 +1391,28 @@ define bfloat @test_sitofp_i32_fadd(i32 %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_sitofp_i32_fadd:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: scvtf d1, w0
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fcvtxn s1, d1
-; CHECK-BF16-NEXT: bfcvt h1, s1
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: fadd s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_sitofp_i32_fadd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: scvtf d1, w0
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fcvtxn s1, d1
+; CHECK-SD-NEXT: bfcvt h1, s1
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: fadd s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_sitofp_i32_fadd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: scvtf s1, w0
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: bfcvt h1, s1
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fadd s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%c = sitofp i32 %a to bfloat
%r = fadd bfloat %b, %c
ret bfloat %r
@@ -1413,19 +1789,33 @@ define bfloat @test_atan2(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_atan2:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1
-; CHECK-BF16-NEXT: bl atan2f
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_atan2:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-SD-NEXT: // kill: def $s1 killed $s1 killed $q1
+; CHECK-SD-NEXT: bl atan2f
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_atan2:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: // kill: def $s1 killed $s1 killed $q1
+; CHECK-GI-NEXT: bl atan2f
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
%r = call bfloat @llvm.atan2.bf16(bfloat %a, bfloat %b)
ret bfloat %r
}
@@ -1551,19 +1941,33 @@ define bfloat @test_pow(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_pow:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1
-; CHECK-BF16-NEXT: bl powf
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_pow:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-SD-NEXT: // kill: def $s1 killed $s1 killed $q1
+; CHECK-SD-NEXT: bl powf
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_pow:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: // kill: def $s1 killed $s1 killed $q1
+; CHECK-GI-NEXT: bl powf
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
%r = call bfloat @llvm.pow.bf16(bfloat %a, bfloat %b)
ret bfloat %r
}
@@ -1753,17 +2157,29 @@ define bfloat @test_fma(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_fma:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v2.4s, v2.4h, #16
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fmadd s0, s0, s1, s2
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_fma:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v2.4s, v2.4h, #16
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fmadd s0, s0, s1, s2
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fma:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: shll v2.4s, v2.4h, #16
+; CHECK-GI-NEXT: fmadd s0, s0, s1, s2
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
ret bfloat %r
}
@@ -1799,15 +2215,25 @@ define bfloat @test_minnum(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_minnum:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fminnm s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_minnum:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fminnm s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_minnum:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fminnm s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = call bfloat @llvm.minnum.bf16(bfloat %a, bfloat %b)
ret bfloat %r
}
@@ -1830,15 +2256,25 @@ define bfloat @test_maxnum(bfloat %a, bfloat %b) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_maxnum:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fmaxnm s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_maxnum:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fmaxnm s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_maxnum:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fmaxnm s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = call bfloat @llvm.maxnum.bf16(bfloat %a, bfloat %b)
ret bfloat %r
}
@@ -1871,11 +2307,11 @@ define bfloat @test_copysign(bfloat %a, bfloat %b) #0 {
;
; CHECK-GI-LABEL: test_copysign:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mvni v2.8h, #128, lsl #8
-; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $q0
-; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $q1
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-GI-NEXT: mvni v2.4h, #128, lsl #8
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 killed $d0
; CHECK-GI-NEXT: ret
%r = call bfloat @llvm.copysign.bf16(bfloat %a, bfloat %b)
ret bfloat %r
@@ -1908,10 +2344,10 @@ define bfloat @test_copysign_f32(bfloat %a, float %b) #0 {
; CHECK-GI-LABEL: test_copysign_f32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: bfcvt h1, s1
-; CHECK-GI-NEXT: mvni v2.8h, #128, lsl #8
-; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $q0
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-GI-NEXT: mvni v2.4h, #128, lsl #8
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 killed $d0
; CHECK-GI-NEXT: ret
%tb = fptrunc float %b to bfloat
%r = call bfloat @llvm.copysign.bf16(bfloat %a, bfloat %tb)
@@ -1945,11 +2381,11 @@ define bfloat @test_copysign_f64(bfloat %a, double %b) #0 {
; CHECK-GI-LABEL: test_copysign_f64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fcvtxn s1, d1
-; CHECK-GI-NEXT: mvni v2.8h, #128, lsl #8
-; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $q0
+; CHECK-GI-NEXT: mvni v2.4h, #128, lsl #8
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
; CHECK-GI-NEXT: bfcvt h1, s1
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 killed $d0
; CHECK-GI-NEXT: ret
%tb = fptrunc double %b to bfloat
%r = call bfloat @llvm.copysign.bf16(bfloat %a, bfloat %tb)
@@ -1987,10 +2423,10 @@ define float @test_copysign_extended(bfloat %a, bfloat %b) #0 {
;
; CHECK-GI-LABEL: test_copysign_extended:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mvni v2.8h, #128, lsl #8
-; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $q0
-; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $q1
-; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: mvni v2.4h, #128, lsl #8
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-GI-NEXT: ret
@@ -2216,20 +2652,35 @@ define bfloat @test_fmuladd(bfloat %a, bfloat %b, bfloat %c) #0 {
; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
; CHECK-CVT-NEXT: ret
;
-; CHECK-BF16-LABEL: test_fmuladd:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fmul s0, s0, s1
-; CHECK-BF16-NEXT: shll v1.4s, v2.4h, #16
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: fadd s0, s0, s1
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-SD-LABEL: test_fmuladd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-SD-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fmul s0, s0, s1
+; CHECK-SD-NEXT: shll v1.4s, v2.4h, #16
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-SD-NEXT: fadd s0, s0, s1
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_fmuladd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-GI-NEXT: // kill: def $h2 killed $h2 def $d2
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-GI-NEXT: fmul s0, s0, s1
+; CHECK-GI-NEXT: shll v1.4s, v2.4h, #16
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-GI-NEXT: fadd s0, s0, s1
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
%r = call bfloat @llvm.fmuladd.bf16(bfloat %a, bfloat %b, bfloat %c)
ret bfloat %r
}
diff --git a/llvm/test/CodeGen/AArch64/bitcast-extend.ll b/llvm/test/CodeGen/AArch64/bitcast-extend.ll
index 741dcf3ad4c2f..0d9607a6c9527 100644
--- a/llvm/test/CodeGen/AArch64/bitcast-extend.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast-extend.ll
@@ -2,10 +2,6 @@
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for load_zext_i8_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for load_zext_i16_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for load_zext_i32_v4bf16
-
define <4 x i16> @z_i32_v4i16(i32 %x) {
; CHECK-SD-LABEL: z_i32_v4i16:
; CHECK-SD: // %bb.0:
@@ -575,11 +571,16 @@ define <2 x float> @load_zext_i32_v2f32(ptr %p) {
}
define <1 x double> @load_zext_i8_v1f64(ptr %p) {
-; CHECK-LABEL: load_zext_i8_v1f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: load_zext_i8_v1f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldrb w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: load_zext_i8_v1f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr b0, [x0]
+; CHECK-GI-NEXT: ret
%l = load i8, ptr %p
%z = zext i8 %l to i64
%b = bitcast i64 %z to <1 x double>
@@ -587,11 +588,16 @@ define <1 x double> @load_zext_i8_v1f64(ptr %p) {
}
define <1 x double> @load_zext_i16_v1f64(ptr %p) {
-; CHECK-LABEL: load_zext_i16_v1f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldrh w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: load_zext_i16_v1f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldrh w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: load_zext_i16_v1f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr h0, [x0]
+; CHECK-GI-NEXT: ret
%l = load i16, ptr %p
%z = zext i16 %l to i64
%b = bitcast i64 %z to <1 x double>
@@ -599,11 +605,16 @@ define <1 x double> @load_zext_i16_v1f64(ptr %p) {
}
define <1 x double> @load_zext_i32_v1f64(ptr %p) {
-; CHECK-LABEL: load_zext_i32_v1f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: load_zext_i32_v1f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: load_zext_i32_v1f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr s0, [x0]
+; CHECK-GI-NEXT: ret
%l = load i32, ptr %p
%z = zext i32 %l to i64
%b = bitcast i64 %z to <1 x double>
diff --git a/llvm/test/CodeGen/AArch64/bitcast.ll b/llvm/test/CodeGen/AArch64/bitcast.ll
index 002e6cd509bec..0f02e1c1f067b 100644
--- a/llvm/test/CodeGen/AArch64/bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast.ll
@@ -498,10 +498,6 @@ define <4 x i64> @bitcast_v8i32_v4i64(<8 x i32> %a, <8 x i32> %b){
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-GI-NEXT: add v1.4s, v1.4s, v3.4s
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov x9, v1.d[1]
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
; CHECK-GI-NEXT: ret
%c = add <8 x i32> %a, %b
%d = bitcast <8 x i32> %c to <4 x i64>
@@ -557,10 +553,6 @@ define <4 x i64> @bitcast_v16i16_v4i64(<16 x i16> %a, <16 x i16> %b){
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: add v0.8h, v0.8h, v2.8h
; CHECK-GI-NEXT: add v1.8h, v1.8h, v3.8h
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov x9, v1.d[1]
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
; CHECK-GI-NEXT: ret
%c = add <16 x i16> %a, %b
%d = bitcast <16 x i16> %c to <4 x i64>
@@ -599,14 +591,6 @@ define <8 x i64> @bitcast_v16i32_v8i64(<16 x i32> %a, <16 x i32> %b){
; CHECK-GI-NEXT: add v1.4s, v1.4s, v5.4s
; CHECK-GI-NEXT: add v2.4s, v2.4s, v6.4s
; CHECK-GI-NEXT: add v3.4s, v3.4s, v7.4s
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov x9, v1.d[1]
-; CHECK-GI-NEXT: mov x10, v2.d[1]
-; CHECK-GI-NEXT: mov x11, v3.d[1]
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
-; CHECK-GI-NEXT: mov v2.d[1], x10
-; CHECK-GI-NEXT: mov v3.d[1], x11
; CHECK-GI-NEXT: ret
%c = add <16 x i32> %a, %b
%d = bitcast <16 x i32> %c to <8 x i64>
diff --git a/llvm/test/CodeGen/AArch64/concat-vector.ll b/llvm/test/CodeGen/AArch64/concat-vector.ll
index e6f27b95d92c8..c4472ca330b6e 100644
--- a/llvm/test/CodeGen/AArch64/concat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/concat-vector.ll
@@ -125,9 +125,9 @@ define <4 x half> @concat9(<2 x half> %A, <2 x half> %B) {
;
; CHECK-GI-LABEL: concat9:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fmov w8, s1
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%v4half= shufflevector <2 x half> %A, <2 x half> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
diff --git a/llvm/test/CodeGen/AArch64/ctlz.ll b/llvm/test/CodeGen/AArch64/ctlz.ll
index b1b869ec9e1ff..6642c92458584 100644
--- a/llvm/test/CodeGen/AArch64/ctlz.ll
+++ b/llvm/test/CodeGen/AArch64/ctlz.ll
@@ -99,8 +99,7 @@ define void @v4i8(ptr %p1) {
; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]
; CHECK-GI-NEXT: mov v2.b[3], v0.b[0]
; CHECK-GI-NEXT: clz v0.8b, v2.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/ctpop.ll b/llvm/test/CodeGen/AArch64/ctpop.ll
index 9c59f1b233b5d..e51e40e34ae09 100644
--- a/llvm/test/CodeGen/AArch64/ctpop.ll
+++ b/llvm/test/CodeGen/AArch64/ctpop.ll
@@ -97,8 +97,7 @@ define void @v4i8(ptr %p1) {
; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]
; CHECK-GI-NEXT: mov v2.b[3], v0.b[0]
; CHECK-GI-NEXT: cnt v0.8b, v2.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/cttz.ll b/llvm/test/CodeGen/AArch64/cttz.ll
index c9181b4c312d1..a883d254d797a 100644
--- a/llvm/test/CodeGen/AArch64/cttz.ll
+++ b/llvm/test/CodeGen/AArch64/cttz.ll
@@ -136,8 +136,7 @@ define void @v4i8(ptr %p1) {
; CHECK-GI-NEXT: and v0.8b, v2.8b, v0.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: cnt v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index d360a9da7d966..2c76de454a39a 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -843,19 +843,19 @@ define <3 x double> @v3f64_double(<3 x double> %a, <3 x double> %b, <3 x double>
; CHECK-GI-NEXT: // kill: def $d6 killed $d6 def $q6
; CHECK-GI-NEXT: // kill: def $d7 killed $d7 def $q7
; CHECK-GI-NEXT: fcmp d2, d5
-; CHECK-GI-NEXT: ldr x8, [sp]
+; CHECK-GI-NEXT: ldr x9, [sp]
; CHECK-GI-NEXT: ldr x10, [sp, #24]
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]
; CHECK-GI-NEXT: mov v6.d[1], v7.d[0]
; CHECK-GI-NEXT: ldp d1, d4, [sp, #8]
-; CHECK-GI-NEXT: cset w9, mi
-; CHECK-GI-NEXT: sbfx x9, x9, #0, #1
+; CHECK-GI-NEXT: cset w8, mi
+; CHECK-GI-NEXT: sbfx x8, x8, #0, #1
; CHECK-GI-NEXT: fcmgt v0.2d, v3.2d, v0.2d
; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]
-; CHECK-GI-NEXT: and x8, x8, x9
-; CHECK-GI-NEXT: bic x9, x10, x9
-; CHECK-GI-NEXT: orr x8, x8, x9
+; CHECK-GI-NEXT: and x9, x9, x8
+; CHECK-GI-NEXT: bic x8, x10, x8
+; CHECK-GI-NEXT: orr x8, x9, x8
; CHECK-GI-NEXT: fmov d2, x8
; CHECK-GI-NEXT: bsl v0.16b, v6.16b, v1.16b
; CHECK-GI-NEXT: mov d1, v0.d[1]
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index b6cbe9eb46389..099a5732992d5 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -968,35 +968,44 @@ define i32 @test_signed_f128_i32(fp128 %f) {
;
; CHECK-GI-LABEL: test_signed_f128_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: sub sp, sp, #64
+; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: .cfi_offset w30, -16
+; CHECK-GI-NEXT: .cfi_offset b8, -24
+; CHECK-GI-NEXT: .cfi_offset b9, -32
+; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI30_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x9, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x9, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: fcsel d10, d0, d1, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: adrp x8, .LCPI30_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: movk x8, #16413, lsl #48
-; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -1004,10 +1013,11 @@ define i32 @test_signed_f128_i32(fp128 %f) {
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel w0, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-GI-NEXT: add sp, sp, #48
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call i32 @llvm.fptosi.sat.i32.f128(fp128 %f)
ret i32 %x
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 2417205759767..f97fae9dff039 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -517,35 +517,44 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v1f128_v1i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: sub sp, sp, #64
+; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: .cfi_offset w30, -16
+; CHECK-GI-NEXT: .cfi_offset b8, -24
+; CHECK-GI-NEXT: .cfi_offset b9, -32
+; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI14_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x9, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x9, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: fcsel d10, d0, d1, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: adrp x8, .LCPI14_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: movk x8, #16413, lsl #48
-; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -553,11 +562,12 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: add sp, sp, #48
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f)
ret <1 x i32> %x
@@ -631,42 +641,51 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #112
-; CHECK-GI-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: adrp x8, .LCPI15_2
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fmov d10, x8
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d11, d0, d10, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI15_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
@@ -676,37 +695,41 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d10, d0, d10, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w21
+; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #64] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #112
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -799,43 +822,54 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: stp x30, x23, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #160
+; CHECK-GI-NEXT: str d12, [sp, #80] // 8-byte Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x21, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI16_1
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: .cfi_offset b12, -80
+; CHECK-GI-NEXT: adrp x8, .LCPI16_2
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: str q2, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d11, d0, d9, gt
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI16_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI16_0
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: fcsel d1, d11, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -844,22 +878,25 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x23, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d12
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
@@ -869,37 +906,42 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w23, wzr, w19, ne
+; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d9, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d9, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w21
+; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldr d12, [sp, #80] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov v0.s[1], w23
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.s[1], w21
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #96] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -1014,44 +1056,55 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #160
-; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp x24, x23, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
+; CHECK-GI-NEXT: sub sp, sp, #176
+; CHECK-GI-NEXT: str d12, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #104] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #120] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #136] // 8-byte Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 176
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w24, -48
-; CHECK-GI-NEXT: .cfi_offset w30, -64
-; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: .cfi_offset w30, -40
+; CHECK-GI-NEXT: .cfi_offset b8, -48
+; CHECK-GI-NEXT: .cfi_offset b9, -56
+; CHECK-GI-NEXT: .cfi_offset b10, -64
+; CHECK-GI-NEXT: .cfi_offset b11, -72
+; CHECK-GI-NEXT: .cfi_offset b12, -80
+; CHECK-GI-NEXT: adrp x8, .LCPI17_2
; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: stp q1, q3, [sp, #64] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d11, d0, d9, gt
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI17_0
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: fcsel d1, d11, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -1061,22 +1114,25 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x23, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d12
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
@@ -1086,21 +1142,24 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w23, wzr, w19, ne
+; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q4, q1, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x24, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x24
+; CHECK-GI-NEXT: mov d0, v4.d[1]
+; CHECK-GI-NEXT: fcsel d11, d4, d8, gt
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d12
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x24, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
@@ -1109,39 +1168,44 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w24, wzr, w19, ne
+; CHECK-GI-NEXT: csel w22, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d9, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d9, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w21
+; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #136] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #128] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov v0.s[1], w23
-; CHECK-GI-NEXT: mov v0.s[2], w24
-; CHECK-GI-NEXT: ldp x24, x23, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #120] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d12, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: mov v0.s[1], w21
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #104] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.s[2], w22
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: add sp, sp, #160
+; CHECK-GI-NEXT: add sp, sp, #176
; CHECK-GI-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x
@@ -5093,17 +5157,21 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #112
-; CHECK-GI-NEXT: stp x30, x23, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: str d12, [sp, #64] // 8-byte Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #72] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #88] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #104] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: .cfi_offset b9, -40
+; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: .cfi_offset b11, -56
+; CHECK-GI-NEXT: .cfi_offset b12, -64
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
@@ -5111,25 +5179,35 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4594234569871327232 // =0xc03e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
+; CHECK-GI-NEXT: mov x8, #8521215115264 // =0x7c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fmov d10, x8
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d11, d0, d10, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov x22, #-1125899906842624 // =0xfffc000000000000
+; CHECK-GI-NEXT: mov x8, #280925220896768 // =0xff8000000000
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x23, #4629137466983448575 // =0x403dffffffffffff
-; CHECK-GI-NEXT: csel x8, x19, x22, mi
+; CHECK-GI-NEXT: movk x8, #17391, lsl #48
+; CHECK-GI-NEXT: fmov d12, x8
+; CHECK-GI-NEXT: mov x8, #-264432546480129 // =0xffff0f7fffffffff
+; CHECK-GI-NEXT: movk x8, #17360, lsl #48
+; CHECK-GI-NEXT: fcsel d0, d9, d12, mi
+; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x23, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfdi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
@@ -5139,36 +5217,41 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x21, xzr, x19, ne
+; CHECK-GI-NEXT: csel x20, xzr, x19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d8, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: fmov x8, d8
+; CHECK-GI-NEXT: fcsel d10, d0, d10, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, x22, mi
+; CHECK-GI-NEXT: fcsel d0, d8, d12, mi
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x23, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfdi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov d0, x21
+; CHECK-GI-NEXT: fmov d0, x20
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldr x30, [sp, #104] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #88] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d12, [sp, #64] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #72] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: add sp, sp, #112
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
index 0ad09d416ce68..9c9f91ec26008 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
@@ -784,35 +784,42 @@ define i32 @test_unsigned_f128_i32(fp128 %f) {
; CHECK-GI-LABEL: test_unsigned_f128_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
-; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset b8, -16
+; CHECK-GI-NEXT: .cfi_offset b9, -24
+; CHECK-GI-NEXT: .cfi_offset b10, -32
+; CHECK-GI-NEXT: adrp x8, .LCPI30_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: adrp x8, .LCPI30_0
+; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
+; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
+; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: movk x8, #16414, lsl #48
-; CHECK-GI-NEXT: csel x8, x20, x8, mi
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: b __fixunstfsi
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index ecca1165753bf..eabe580d7f6d5 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -474,38 +474,45 @@ define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-GI-LABEL: test_unsigned_v1f128_v1i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
-; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset b8, -16
+; CHECK-GI-NEXT: .cfi_offset b9, -24
+; CHECK-GI-NEXT: .cfi_offset b10, -32
+; CHECK-GI-NEXT: adrp x8, .LCPI14_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: adrp x8, .LCPI14_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: movk x8, #16414, lsl #48
-; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-GI-NEXT: fmov s0, w0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f128.v1i32(<1 x fp128> %f)
@@ -565,64 +572,72 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-LABEL: test_unsigned_v2f128_v2i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: str x30, [sp, #48] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: .cfi_offset w30, -16
+; CHECK-GI-NEXT: .cfi_offset b8, -24
+; CHECK-GI-NEXT: .cfi_offset b9, -32
+; CHECK-GI-NEXT: .cfi_offset b10, -40
+; CHECK-GI-NEXT: .cfi_offset b11, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI15_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x21, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x21, #16414, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI15_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x22
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x22, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #48] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: add sp, sp, #96
@@ -696,87 +711,100 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #112
-; CHECK-GI-NEXT: stp x30, x23, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI16_1
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: adrp x8, .LCPI16_2
; CHECK-GI-NEXT: stp q1, q0, [sp] // 32-byte Folded Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
; CHECK-GI-NEXT: stp q1, q2, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI16_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x21, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x21, #16414, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI16_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q3, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x22
+; CHECK-GI-NEXT: mov d0, v3.d[1]
+; CHECK-GI-NEXT: fcsel d10, d3, d8, gt
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x22, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x22
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x22, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w0
-; CHECK-GI-NEXT: add sp, sp, #112
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -866,111 +894,125 @@ define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-LABEL: test_unsigned_v4f128_v4i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #144
-; CHECK-GI-NEXT: str x30, [sp, #80] // 8-byte Spill
-; CHECK-GI-NEXT: stp x24, x23, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x21, [sp, #112] // 16-byte Folded Spill
; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w24, -48
-; CHECK-GI-NEXT: .cfi_offset w30, -64
-; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: adrp x8, .LCPI17_2
; CHECK-GI-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: str q3, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16414, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI17_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x21, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x21
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x21, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x21
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x21, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w21, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q4, q1, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x23
-; CHECK-GI-NEXT: csel x24, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x24
+; CHECK-GI-NEXT: mov d0, v4.d[1]
+; CHECK-GI-NEXT: fcsel d10, d4, d8, gt
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x23, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x24, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x24, x23, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #80] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
; CHECK-GI-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w21
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w0
; CHECK-GI-NEXT: add sp, sp, #144
; CHECK-GI-NEXT: ret
@@ -4140,65 +4182,76 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp x30, x23, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -16
+; CHECK-GI-NEXT: .cfi_offset b8, -24
+; CHECK-GI-NEXT: .cfi_offset b9, -32
+; CHECK-GI-NEXT: .cfi_offset b10, -40
+; CHECK-GI-NEXT: .cfi_offset b11, -48
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov x21, #-562949953421312 // =0xfffe000000000000
+; CHECK-GI-NEXT: mov x8, #281200098803712 // =0xffc000000000
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #4629418941960159231 // =0x403effffffffffff
-; CHECK-GI-NEXT: csel x8, x19, x21, mi
+; CHECK-GI-NEXT: movk x8, #17391, lsl #48
+; CHECK-GI-NEXT: fmov d11, x8
+; CHECK-GI-NEXT: mov x8, #-264157668573185 // =0xffff0fbfffffffff
+; CHECK-GI-NEXT: movk x8, #17360, lsl #48
+; CHECK-GI-NEXT: fcsel d0, d9, d11, mi
+; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d8, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d8
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d11, mi
+; CHECK-GI-NEXT: fcsel d1, d8, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: fmov d0, x19
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.d[1], x0
; CHECK-GI-NEXT: add sp, sp, #96
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll
index 9325c8c685560..317551de00ef7 100644
--- a/llvm/test/CodeGen/AArch64/insertextract.ll
+++ b/llvm/test/CodeGen/AArch64/insertextract.ll
@@ -1390,7 +1390,7 @@ define <2 x i128> @insert_v2i128_c(<2 x i128> %a, i128 %b, i32 %c) {
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset w29, -16
; CHECK-GI-NEXT: adds x8, x0, x0
-; CHECK-GI-NEXT: mov v2.d[0], x4
+; CHECK-GI-NEXT: fmov d2, x4
; CHECK-GI-NEXT: adc x9, x1, x1
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: adds x8, x2, x2
@@ -2887,18 +2887,20 @@ define i128 @extract_v2i128_c(<2 x i128> %a, i32 %c) {
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset w29, -16
; CHECK-GI-NEXT: adds x8, x0, x0
+; CHECK-GI-NEXT: mov x10, sp
; CHECK-GI-NEXT: adc x9, x1, x1
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: adds x8, x2, x2
; CHECK-GI-NEXT: mov v1.d[0], x8
; CHECK-GI-NEXT: adc x8, x3, x3
; CHECK-GI-NEXT: mov v0.d[1], x9
-; CHECK-GI-NEXT: mov x9, sp
+; CHECK-GI-NEXT: mov w9, #16 // =0x10
; CHECK-GI-NEXT: mov v1.d[1], x8
; CHECK-GI-NEXT: mov w8, w4
; CHECK-GI-NEXT: and x8, x8, #0x1
+; CHECK-GI-NEXT: umaddl x8, w8, w9, x10
; CHECK-GI-NEXT: stp q0, q1, [sp]
-; CHECK-GI-NEXT: ldr q0, [x9, x8, lsl #4]
+; CHECK-GI-NEXT: ldr q0, [x8]
; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: fmov x0, d0
; CHECK-GI-NEXT: fmov x1, d1
diff --git a/llvm/test/CodeGen/AArch64/itofp-bf16.ll b/llvm/test/CodeGen/AArch64/itofp-bf16.ll
index 0d3ae559449a4..1d4f594c896a8 100644
--- a/llvm/test/CodeGen/AArch64/itofp-bf16.ll
+++ b/llvm/test/CodeGen/AArch64/itofp-bf16.ll
@@ -1,161 +1,100 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-NOFP16
-; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
-; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP16
-; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
-
-; CHECK-GI: warning: Instruction selection used fallback path for stofp_i64_bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_i64_bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_i32_bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_i32_bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_i16_bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_i16_bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_i8_bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_i8_bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v2i64_v2bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v2i64_v2bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v3i64_v3bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v3i64_v3bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v4i64_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v4i64_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v8i64_v8bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v8i64_v8bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v16i64_v16bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v16i64_v16bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v32i64_v32bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v32i64_v32bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v2i32_v2bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v2i32_v2bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v3i32_v3bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v3i32_v3bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v4i32_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v4i32_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v8i32_v8bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v8i32_v8bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v16i32_v16bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v16i32_v16bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v32i32_v32bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v32i32_v32bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v2i16_v2bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v2i16_v2bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v3i16_v3bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v3i16_v3bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v4i16_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v4i16_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v8i16_v8bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v8i16_v8bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v16i16_v16bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v16i16_v16bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v32i16_v32bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v32i16_v32bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v2i8_v2bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v2i8_v2bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v3i8_v3bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v3i8_v3bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v4i8_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v4i8_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v8i8_v8bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v8i8_v8bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v16i8_v16bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v16i8_v16bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v32i8_v32bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v32i8_v32bf16
+; RUN: llc -mtriple=aarch64 -mattr=+bf16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-NOFP16
+; RUN: llc -mtriple=aarch64 -mattr=+fullfp16,+bf16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
+; RUN: llc -mtriple=aarch64 -mattr=+bf16 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP16
+; RUN: llc -mtriple=aarch64 -mattr=+fullfp16,+bf16 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
define bfloat @stofp_i64_bf16(i64 %a) {
-; CHECK-LABEL: stofp_i64_bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: and x11, x0, #0x8000000000000000
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: cneg x9, x0, mi
-; CHECK-NEXT: lsr x10, x9, #53
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: and x10, x9, #0xfffffffffffff000
-; CHECK-NEXT: csel x10, x10, x9, ne
-; CHECK-NEXT: scvtf d0, x10
-; CHECK-NEXT: cset w10, ne
-; CHECK-NEXT: tst x9, #0xfff
-; CHECK-NEXT: csel w10, wzr, w10, eq
-; CHECK-NEXT: fmov x9, d0
-; CHECK-NEXT: orr x9, x9, x11
-; CHECK-NEXT: orr x9, x9, x10
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fcvtxn s0, d0
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w10, w9, #16, #1
-; CHECK-NEXT: add w8, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_i64_bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: cmp x0, #0
+; CHECK-SD-NEXT: cneg x8, x0, mi
+; CHECK-SD-NEXT: lsr x9, x8, #53
+; CHECK-SD-NEXT: and x10, x8, #0xfffffffffffff000
+; CHECK-SD-NEXT: cmp x9, #0
+; CHECK-SD-NEXT: csel x9, x10, x8, ne
+; CHECK-SD-NEXT: and x10, x0, #0x8000000000000000
+; CHECK-SD-NEXT: cset w11, ne
+; CHECK-SD-NEXT: scvtf d0, x9
+; CHECK-SD-NEXT: tst x8, #0xfff
+; CHECK-SD-NEXT: fmov x9, d0
+; CHECK-SD-NEXT: orr x8, x9, x10
+; CHECK-SD-NEXT: csel w9, wzr, w11, eq
+; CHECK-SD-NEXT: orr x8, x8, x9
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_i64_bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: scvtf s0, x0
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp i64 %a to bfloat
ret bfloat %c
}
define bfloat @utofp_i64_bf16(i64 %a) {
-; CHECK-LABEL: utofp_i64_bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: lsr x9, x0, #53
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: and x9, x0, #0xfffffffffffff000
-; CHECK-NEXT: csel x9, x9, x0, ne
-; CHECK-NEXT: ucvtf d0, x9
-; CHECK-NEXT: cset w9, ne
-; CHECK-NEXT: tst x0, #0xfff
-; CHECK-NEXT: csel w9, wzr, w9, eq
-; CHECK-NEXT: fmov x10, d0
-; CHECK-NEXT: orr x9, x10, x9
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fcvtxn s0, d0
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w10, w9, #16, #1
-; CHECK-NEXT: add w8, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_i64_bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: lsr x8, x0, #53
+; CHECK-SD-NEXT: and x9, x0, #0xfffffffffffff000
+; CHECK-SD-NEXT: cmp x8, #0
+; CHECK-SD-NEXT: csel x8, x9, x0, ne
+; CHECK-SD-NEXT: ucvtf d0, x8
+; CHECK-SD-NEXT: cset w8, ne
+; CHECK-SD-NEXT: tst x0, #0xfff
+; CHECK-SD-NEXT: csel w8, wzr, w8, eq
+; CHECK-SD-NEXT: fmov x9, d0
+; CHECK-SD-NEXT: orr x8, x9, x8
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_i64_bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ucvtf s0, x0
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp i64 %a to bfloat
ret bfloat %c
}
define bfloat @stofp_i32_bf16(i32 %a) {
-; CHECK-LABEL: stofp_i32_bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: scvtf d0, w0
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: fcvtxn s0, d0
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w10, w9, #16, #1
-; CHECK-NEXT: add w8, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_i32_bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: scvtf d0, w0
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_i32_bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: scvtf s0, w0
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp i32 %a to bfloat
ret bfloat %c
}
define bfloat @utofp_i32_bf16(i32 %a) {
-; CHECK-LABEL: utofp_i32_bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ucvtf d0, w0
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: fcvtxn s0, d0
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w10, w9, #16, #1
-; CHECK-NEXT: add w8, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_i32_bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ucvtf d0, w0
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: bfcvt h0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_i32_bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ucvtf s0, w0
+; CHECK-GI-NEXT: bfcvt h0, s0
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp i32 %a to bfloat
ret bfloat %c
@@ -164,16 +103,9 @@ entry:
define bfloat @stofp_i16_bf16(i16 %a) {
; CHECK-LABEL: stofp_i16_bf16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sxth w9, w0
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: scvtf s0, w9
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w10, w9, #16, #1
-; CHECK-NEXT: add w8, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: sxth w8, w0
+; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: bfcvt h0, s0
; CHECK-NEXT: ret
entry:
%c = sitofp i16 %a to bfloat
@@ -183,16 +115,9 @@ entry:
define bfloat @utofp_i16_bf16(i16 %a) {
; CHECK-LABEL: utofp_i16_bf16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: and w9, w0, #0xffff
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: ucvtf s0, w9
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w10, w9, #16, #1
-; CHECK-NEXT: add w8, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: and w8, w0, #0xffff
+; CHECK-NEXT: ucvtf s0, w8
+; CHECK-NEXT: bfcvt h0, s0
; CHECK-NEXT: ret
entry:
%c = uitofp i16 %a to bfloat
@@ -202,16 +127,9 @@ entry:
define bfloat @stofp_i8_bf16(i8 %a) {
; CHECK-LABEL: stofp_i8_bf16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sxtb w9, w0
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: scvtf s0, w9
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w10, w9, #16, #1
-; CHECK-NEXT: add w8, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: sxtb w8, w0
+; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: bfcvt h0, s0
; CHECK-NEXT: ret
entry:
%c = sitofp i8 %a to bfloat
@@ -221,16 +139,9 @@ entry:
define bfloat @utofp_i8_bf16(i8 %a) {
; CHECK-LABEL: utofp_i8_bf16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: and w9, w0, #0xff
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: ucvtf s0, w9
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w10, w9, #16, #1
-; CHECK-NEXT: add w8, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: and w8, w0, #0xff
+; CHECK-NEXT: ucvtf s0, w8
+; CHECK-NEXT: bfcvt h0, s0
; CHECK-NEXT: ret
entry:
%c = uitofp i8 %a to bfloat
@@ -238,842 +149,1050 @@ entry:
}
define <2 x bfloat> @stofp_v2i64_v2bf16(<2 x i64> %a) {
-; CHECK-LABEL: stofp_v2i64_v2bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x9, v0.d[1]
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: cneg x10, x9, mi
-; CHECK-NEXT: and x9, x9, #0x8000000000000000
-; CHECK-NEXT: lsr x11, x10, #53
-; CHECK-NEXT: and x12, x10, #0xfffffffffffff000
-; CHECK-NEXT: cmp x11, #0
-; CHECK-NEXT: csel x11, x12, x10, ne
-; CHECK-NEXT: cset w12, ne
-; CHECK-NEXT: tst x10, #0xfff
-; CHECK-NEXT: fmov x10, d0
-; CHECK-NEXT: csel w12, wzr, w12, eq
-; CHECK-NEXT: scvtf d0, x11
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: cneg x13, x10, mi
-; CHECK-NEXT: and x10, x10, #0x8000000000000000
-; CHECK-NEXT: lsr x14, x13, #53
-; CHECK-NEXT: cmp x14, #0
-; CHECK-NEXT: and x14, x13, #0xfffffffffffff000
-; CHECK-NEXT: csel x11, x14, x13, ne
-; CHECK-NEXT: cset w14, ne
-; CHECK-NEXT: tst x13, #0xfff
-; CHECK-NEXT: scvtf d1, x11
-; CHECK-NEXT: fmov x11, d0
-; CHECK-NEXT: orr x9, x11, x9
-; CHECK-NEXT: csel w11, wzr, w14, eq
-; CHECK-NEXT: fmov x13, d1
-; CHECK-NEXT: orr x9, x9, x12
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: orr x10, x13, x10
-; CHECK-NEXT: orr x10, x10, x11
-; CHECK-NEXT: fcvtxn s0, d0
-; CHECK-NEXT: fmov d1, x10
-; CHECK-NEXT: fcvtxn s1, d1
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w11, w9, #16, #1
-; CHECK-NEXT: add w9, w9, w8
-; CHECK-NEXT: fmov w10, s1
-; CHECK-NEXT: add w9, w11, w9
-; CHECK-NEXT: lsr w9, w9, #16
-; CHECK-NEXT: ubfx w12, w10, #16, #1
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: add w8, w12, w8
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v2i64_v2bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x8, v0.d[1]
+; CHECK-SD-NEXT: cmp x8, #0
+; CHECK-SD-NEXT: cneg x9, x8, mi
+; CHECK-SD-NEXT: and x8, x8, #0x8000000000000000
+; CHECK-SD-NEXT: lsr x10, x9, #53
+; CHECK-SD-NEXT: and x11, x9, #0xfffffffffffff000
+; CHECK-SD-NEXT: cmp x10, #0
+; CHECK-SD-NEXT: csel x10, x11, x9, ne
+; CHECK-SD-NEXT: cset w11, ne
+; CHECK-SD-NEXT: tst x9, #0xfff
+; CHECK-SD-NEXT: fmov x9, d0
+; CHECK-SD-NEXT: csel w11, wzr, w11, eq
+; CHECK-SD-NEXT: scvtf d0, x10
+; CHECK-SD-NEXT: cmp x9, #0
+; CHECK-SD-NEXT: cneg x12, x9, mi
+; CHECK-SD-NEXT: and x9, x9, #0x8000000000000000
+; CHECK-SD-NEXT: lsr x13, x12, #53
+; CHECK-SD-NEXT: cmp x13, #0
+; CHECK-SD-NEXT: and x13, x12, #0xfffffffffffff000
+; CHECK-SD-NEXT: csel x10, x13, x12, ne
+; CHECK-SD-NEXT: cset w13, ne
+; CHECK-SD-NEXT: tst x12, #0xfff
+; CHECK-SD-NEXT: scvtf d1, x10
+; CHECK-SD-NEXT: fmov x10, d0
+; CHECK-SD-NEXT: orr x8, x10, x8
+; CHECK-SD-NEXT: csel w10, wzr, w13, eq
+; CHECK-SD-NEXT: fmov x12, d1
+; CHECK-SD-NEXT: orr x8, x8, x11
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: orr x9, x12, x9
+; CHECK-SD-NEXT: orr x9, x9, x10
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: fcvtxn s1, d1
+; CHECK-SD-NEXT: bfcvt h2, s0
+; CHECK-SD-NEXT: bfcvt h0, s1
+; CHECK-SD-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v2i64_v2bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: scvtf s0, x9
+; CHECK-GI-NEXT: scvtf s1, x8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <2 x i64> %a to <2 x bfloat>
ret <2 x bfloat> %c
}
define <2 x bfloat> @utofp_v2i64_v2bf16(<2 x i64> %a) {
-; CHECK-LABEL: utofp_v2i64_v2bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x9, v0.d[1]
-; CHECK-NEXT: fmov x11, d0
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: lsr x10, x9, #53
-; CHECK-NEXT: and x12, x9, #0xfffffffffffff000
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: lsr x10, x11, #53
-; CHECK-NEXT: csel x12, x12, x9, ne
-; CHECK-NEXT: cset w13, ne
-; CHECK-NEXT: tst x9, #0xfff
-; CHECK-NEXT: csel w9, wzr, w13, eq
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: and x10, x11, #0xfffffffffffff000
-; CHECK-NEXT: csel x10, x10, x11, ne
-; CHECK-NEXT: ucvtf d0, x12
-; CHECK-NEXT: ucvtf d1, x10
-; CHECK-NEXT: cset w10, ne
-; CHECK-NEXT: tst x11, #0xfff
-; CHECK-NEXT: csel w10, wzr, w10, eq
-; CHECK-NEXT: fmov x11, d0
-; CHECK-NEXT: fmov x12, d1
-; CHECK-NEXT: orr x9, x11, x9
-; CHECK-NEXT: orr x10, x12, x10
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fmov d1, x10
-; CHECK-NEXT: fcvtxn s0, d0
-; CHECK-NEXT: fcvtxn s1, d1
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: fmov w10, s1
-; CHECK-NEXT: ubfx w11, w9, #16, #1
-; CHECK-NEXT: add w9, w9, w8
-; CHECK-NEXT: ubfx w12, w10, #16, #1
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: add w9, w11, w9
-; CHECK-NEXT: add w8, w12, w8
-; CHECK-NEXT: lsr w9, w9, #16
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v2i64_v2bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x8, v0.d[1]
+; CHECK-SD-NEXT: fmov x10, d0
+; CHECK-SD-NEXT: lsr x9, x8, #53
+; CHECK-SD-NEXT: and x11, x8, #0xfffffffffffff000
+; CHECK-SD-NEXT: cmp x9, #0
+; CHECK-SD-NEXT: lsr x9, x10, #53
+; CHECK-SD-NEXT: csel x11, x11, x8, ne
+; CHECK-SD-NEXT: cset w12, ne
+; CHECK-SD-NEXT: tst x8, #0xfff
+; CHECK-SD-NEXT: csel w8, wzr, w12, eq
+; CHECK-SD-NEXT: cmp x9, #0
+; CHECK-SD-NEXT: and x9, x10, #0xfffffffffffff000
+; CHECK-SD-NEXT: csel x9, x9, x10, ne
+; CHECK-SD-NEXT: ucvtf d0, x11
+; CHECK-SD-NEXT: ucvtf d1, x9
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst x10, #0xfff
+; CHECK-SD-NEXT: csel w9, wzr, w9, eq
+; CHECK-SD-NEXT: fmov x10, d0
+; CHECK-SD-NEXT: fmov x11, d1
+; CHECK-SD-NEXT: orr x8, x10, x8
+; CHECK-SD-NEXT: orr x9, x11, x9
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: fcvtxn s0, d0
+; CHECK-SD-NEXT: fcvtxn s1, d1
+; CHECK-SD-NEXT: bfcvt h2, s0
+; CHECK-SD-NEXT: bfcvt h0, s1
+; CHECK-SD-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v2i64_v2bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: ucvtf s0, x9
+; CHECK-GI-NEXT: ucvtf s1, x8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <2 x i64> %a to <2 x bfloat>
ret <2 x bfloat> %c
}
define <3 x bfloat> @stofp_v3i64_v3bf16(<3 x i64> %a) {
-; CHECK-LABEL: stofp_v3i64_v3bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: movi v3.2d, #0000000000000000
-; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NEXT: scvtf s0, x8
-; CHECK-NEXT: fmov x8, d1
-; CHECK-NEXT: scvtf s1, x8
-; CHECK-NEXT: fmov x8, d2
-; CHECK-NEXT: mov v3.s[0], v0.s[0]
-; CHECK-NEXT: scvtf s0, x8
-; CHECK-NEXT: mov v3.s[1], v1.s[0]
-; CHECK-NEXT: movi v1.4s, #127, msl #8
-; CHECK-NEXT: mov v3.s[2], v0.s[0]
-; CHECK-NEXT: movi v0.4s, #1
-; CHECK-NEXT: ushr v2.4s, v3.4s, #16
-; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
-; CHECK-NEXT: fcmeq v2.4s, v3.4s, v3.4s
-; CHECK-NEXT: orr v3.4s, #64, lsl #16
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: bif v0.16b, v3.16b, v2.16b
-; CHECK-NEXT: shrn v0.4h, v0.4s, #16
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v3i64_v3bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: movi v3.2d, #0000000000000000
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-SD-NEXT: scvtf s0, x8
+; CHECK-SD-NEXT: fmov x8, d1
+; CHECK-SD-NEXT: scvtf s1, x8
+; CHECK-SD-NEXT: fmov x8, d2
+; CHECK-SD-NEXT: mov v3.s[0], v0.s[0]
+; CHECK-SD-NEXT: scvtf s0, x8
+; CHECK-SD-NEXT: mov v3.s[1], v1.s[0]
+; CHECK-SD-NEXT: mov v3.s[2], v0.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v3.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v3i64_v3bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: scvtf s0, x8
+; CHECK-GI-NEXT: scvtf s1, x9
+; CHECK-GI-NEXT: fmov x8, d2
+; CHECK-GI-NEXT: scvtf s2, x8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: movi d1, #0000000000000000
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <3 x i64> %a to <3 x bfloat>
ret <3 x bfloat> %c
}
define <3 x bfloat> @utofp_v3i64_v3bf16(<3 x i64> %a) {
-; CHECK-LABEL: utofp_v3i64_v3bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: movi v3.2d, #0000000000000000
-; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NEXT: ucvtf s0, x8
-; CHECK-NEXT: fmov x8, d1
-; CHECK-NEXT: ucvtf s1, x8
-; CHECK-NEXT: fmov x8, d2
-; CHECK-NEXT: mov v3.s[0], v0.s[0]
-; CHECK-NEXT: ucvtf s0, x8
-; CHECK-NEXT: mov v3.s[1], v1.s[0]
-; CHECK-NEXT: movi v1.4s, #127, msl #8
-; CHECK-NEXT: mov v3.s[2], v0.s[0]
-; CHECK-NEXT: movi v0.4s, #1
-; CHECK-NEXT: ushr v2.4s, v3.4s, #16
-; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
-; CHECK-NEXT: fcmeq v2.4s, v3.4s, v3.4s
-; CHECK-NEXT: orr v3.4s, #64, lsl #16
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: bif v0.16b, v3.16b, v2.16b
-; CHECK-NEXT: shrn v0.4h, v0.4s, #16
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v3i64_v3bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: movi v3.2d, #0000000000000000
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-SD-NEXT: ucvtf s0, x8
+; CHECK-SD-NEXT: fmov x8, d1
+; CHECK-SD-NEXT: ucvtf s1, x8
+; CHECK-SD-NEXT: fmov x8, d2
+; CHECK-SD-NEXT: mov v3.s[0], v0.s[0]
+; CHECK-SD-NEXT: ucvtf s0, x8
+; CHECK-SD-NEXT: mov v3.s[1], v1.s[0]
+; CHECK-SD-NEXT: mov v3.s[2], v0.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v3.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v3i64_v3bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: ucvtf s0, x8
+; CHECK-GI-NEXT: ucvtf s1, x9
+; CHECK-GI-NEXT: fmov x8, d2
+; CHECK-GI-NEXT: ucvtf s2, x8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: movi d1, #0000000000000000
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <3 x i64> %a to <3 x bfloat>
ret <3 x bfloat> %c
}
define <4 x bfloat> @stofp_v4i64_v4bf16(<4 x i64> %a) {
-; CHECK-LABEL: stofp_v4i64_v4bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, v0.d[1]
-; CHECK-NEXT: fmov x9, d0
-; CHECK-NEXT: scvtf s2, x9
-; CHECK-NEXT: mov x9, v1.d[1]
-; CHECK-NEXT: scvtf s0, x8
-; CHECK-NEXT: fmov x8, d1
-; CHECK-NEXT: scvtf s1, x8
-; CHECK-NEXT: mov v2.s[1], v0.s[0]
-; CHECK-NEXT: scvtf s0, x9
-; CHECK-NEXT: mov v2.s[2], v1.s[0]
-; CHECK-NEXT: movi v1.4s, #127, msl #8
-; CHECK-NEXT: mov v2.s[3], v0.s[0]
-; CHECK-NEXT: movi v0.4s, #1
-; CHECK-NEXT: ushr v3.4s, v2.4s, #16
-; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v3.16b, v0.16b
-; CHECK-NEXT: fcmeq v3.4s, v2.4s, v2.4s
-; CHECK-NEXT: orr v2.4s, #64, lsl #16
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: bif v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: shrn v0.4h, v0.4s, #16
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v4i64_v4bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x8, v0.d[1]
+; CHECK-SD-NEXT: fmov x9, d0
+; CHECK-SD-NEXT: scvtf s2, x9
+; CHECK-SD-NEXT: mov x9, v1.d[1]
+; CHECK-SD-NEXT: scvtf s0, x8
+; CHECK-SD-NEXT: fmov x8, d1
+; CHECK-SD-NEXT: mov v2.s[1], v0.s[0]
+; CHECK-SD-NEXT: scvtf s0, x8
+; CHECK-SD-NEXT: mov v2.s[2], v0.s[0]
+; CHECK-SD-NEXT: scvtf s0, x9
+; CHECK-SD-NEXT: mov v2.s[3], v0.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v4i64_v4bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: scvtf s0, x9
+; CHECK-GI-NEXT: mov x9, v1.d[1]
+; CHECK-GI-NEXT: scvtf s2, x8
+; CHECK-GI-NEXT: fmov x8, d1
+; CHECK-GI-NEXT: scvtf s1, x8
+; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]
+; CHECK-GI-NEXT: scvtf s2, x9
+; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v2.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <4 x i64> %a to <4 x bfloat>
ret <4 x bfloat> %c
}
define <4 x bfloat> @utofp_v4i64_v4bf16(<4 x i64> %a) {
-; CHECK-LABEL: utofp_v4i64_v4bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, v0.d[1]
-; CHECK-NEXT: fmov x9, d0
-; CHECK-NEXT: ucvtf s2, x9
-; CHECK-NEXT: mov x9, v1.d[1]
-; CHECK-NEXT: ucvtf s0, x8
-; CHECK-NEXT: fmov x8, d1
-; CHECK-NEXT: ucvtf s1, x8
-; CHECK-NEXT: mov v2.s[1], v0.s[0]
-; CHECK-NEXT: ucvtf s0, x9
-; CHECK-NEXT: mov v2.s[2], v1.s[0]
-; CHECK-NEXT: movi v1.4s, #127, msl #8
-; CHECK-NEXT: mov v2.s[3], v0.s[0]
-; CHECK-NEXT: movi v0.4s, #1
-; CHECK-NEXT: ushr v3.4s, v2.4s, #16
-; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v3.16b, v0.16b
-; CHECK-NEXT: fcmeq v3.4s, v2.4s, v2.4s
-; CHECK-NEXT: orr v2.4s, #64, lsl #16
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: bif v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: shrn v0.4h, v0.4s, #16
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v4i64_v4bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x8, v0.d[1]
+; CHECK-SD-NEXT: fmov x9, d0
+; CHECK-SD-NEXT: ucvtf s2, x9
+; CHECK-SD-NEXT: mov x9, v1.d[1]
+; CHECK-SD-NEXT: ucvtf s0, x8
+; CHECK-SD-NEXT: fmov x8, d1
+; CHECK-SD-NEXT: mov v2.s[1], v0.s[0]
+; CHECK-SD-NEXT: ucvtf s0, x8
+; CHECK-SD-NEXT: mov v2.s[2], v0.s[0]
+; CHECK-SD-NEXT: ucvtf s0, x9
+; CHECK-SD-NEXT: mov v2.s[3], v0.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v4i64_v4bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: ucvtf s0, x9
+; CHECK-GI-NEXT: mov x9, v1.d[1]
+; CHECK-GI-NEXT: ucvtf s2, x8
+; CHECK-GI-NEXT: fmov x8, d1
+; CHECK-GI-NEXT: ucvtf s1, x8
+; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]
+; CHECK-GI-NEXT: ucvtf s2, x9
+; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v2.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <4 x i64> %a to <4 x bfloat>
ret <4 x bfloat> %c
}
define <8 x bfloat> @stofp_v8i64_v8bf16(<8 x i64> %a) {
-; CHECK-LABEL: stofp_v8i64_v8bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov x10, d2
-; CHECK-NEXT: mov x8, v2.d[1]
-; CHECK-NEXT: mov x9, v0.d[1]
-; CHECK-NEXT: scvtf s2, x10
-; CHECK-NEXT: fmov x10, d0
-; CHECK-NEXT: scvtf s0, x8
-; CHECK-NEXT: scvtf s5, x9
-; CHECK-NEXT: fmov x9, d3
-; CHECK-NEXT: mov x8, v3.d[1]
-; CHECK-NEXT: scvtf s4, x10
-; CHECK-NEXT: fmov x10, d1
-; CHECK-NEXT: scvtf s3, x9
-; CHECK-NEXT: mov x9, v1.d[1]
-; CHECK-NEXT: mov v2.s[1], v0.s[0]
-; CHECK-NEXT: scvtf s0, x10
-; CHECK-NEXT: scvtf s1, x8
-; CHECK-NEXT: mov v4.s[1], v5.s[0]
-; CHECK-NEXT: mov v2.s[2], v3.s[0]
-; CHECK-NEXT: scvtf s3, x9
-; CHECK-NEXT: mov v4.s[2], v0.s[0]
-; CHECK-NEXT: movi v0.4s, #1
-; CHECK-NEXT: mov v2.s[3], v1.s[0]
-; CHECK-NEXT: movi v1.4s, #127, msl #8
-; CHECK-NEXT: mov v4.s[3], v3.s[0]
-; CHECK-NEXT: ushr v3.4s, v2.4s, #16
-; CHECK-NEXT: add v6.4s, v2.4s, v1.4s
-; CHECK-NEXT: ushr v5.4s, v4.4s, #16
-; CHECK-NEXT: add v1.4s, v4.4s, v1.4s
-; CHECK-NEXT: and v3.16b, v3.16b, v0.16b
-; CHECK-NEXT: and v0.16b, v5.16b, v0.16b
-; CHECK-NEXT: fcmeq v5.4s, v2.4s, v2.4s
-; CHECK-NEXT: orr v2.4s, #64, lsl #16
-; CHECK-NEXT: add v3.4s, v3.4s, v6.4s
-; CHECK-NEXT: fcmeq v6.4s, v4.4s, v4.4s
-; CHECK-NEXT: orr v4.4s, #64, lsl #16
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: mov v1.16b, v5.16b
-; CHECK-NEXT: bif v0.16b, v4.16b, v6.16b
-; CHECK-NEXT: bsl v1.16b, v3.16b, v2.16b
-; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v8i64_v8bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x9, v0.d[1]
+; CHECK-SD-NEXT: fmov x10, d0
+; CHECK-SD-NEXT: mov x8, v2.d[1]
+; CHECK-SD-NEXT: scvtf s4, x10
+; CHECK-SD-NEXT: fmov x10, d1
+; CHECK-SD-NEXT: scvtf s0, x9
+; CHECK-SD-NEXT: fmov x9, d2
+; CHECK-SD-NEXT: scvtf s2, x8
+; CHECK-SD-NEXT: mov x8, v1.d[1]
+; CHECK-SD-NEXT: scvtf s1, x9
+; CHECK-SD-NEXT: fmov x9, d3
+; CHECK-SD-NEXT: mov v4.s[1], v0.s[0]
+; CHECK-SD-NEXT: scvtf s0, x10
+; CHECK-SD-NEXT: mov x10, v3.d[1]
+; CHECK-SD-NEXT: scvtf s3, x9
+; CHECK-SD-NEXT: mov v1.s[1], v2.s[0]
+; CHECK-SD-NEXT: scvtf s2, x8
+; CHECK-SD-NEXT: mov v4.s[2], v0.s[0]
+; CHECK-SD-NEXT: scvtf s0, x10
+; CHECK-SD-NEXT: mov v1.s[2], v3.s[0]
+; CHECK-SD-NEXT: mov v4.s[3], v2.s[0]
+; CHECK-SD-NEXT: mov v1.s[3], v0.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v4.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v8i64_v8bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov x10, v1.d[1]
+; CHECK-GI-NEXT: scvtf s0, x9
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: scvtf s4, x8
+; CHECK-GI-NEXT: mov x8, v2.d[1]
+; CHECK-GI-NEXT: scvtf s1, x9
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: scvtf s5, x8
+; CHECK-GI-NEXT: mov v0.s[1], v4.s[0]
+; CHECK-GI-NEXT: scvtf s4, x10
+; CHECK-GI-NEXT: scvtf s2, x9
+; CHECK-GI-NEXT: fmov x9, d3
+; CHECK-GI-NEXT: mov x8, v3.d[1]
+; CHECK-GI-NEXT: scvtf s3, x9
+; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
+; CHECK-GI-NEXT: mov v2.s[1], v5.s[0]
+; CHECK-GI-NEXT: scvtf s1, x8
+; CHECK-GI-NEXT: mov v0.s[3], v4.s[0]
+; CHECK-GI-NEXT: mov v2.s[2], v3.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: mov v2.s[3], v1.s[0]
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <8 x i64> %a to <8 x bfloat>
ret <8 x bfloat> %c
}
define <8 x bfloat> @utofp_v8i64_v8bf16(<8 x i64> %a) {
-; CHECK-LABEL: utofp_v8i64_v8bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov x10, d2
-; CHECK-NEXT: mov x8, v2.d[1]
-; CHECK-NEXT: mov x9, v0.d[1]
-; CHECK-NEXT: ucvtf s2, x10
-; CHECK-NEXT: fmov x10, d0
-; CHECK-NEXT: ucvtf s0, x8
-; CHECK-NEXT: ucvtf s5, x9
-; CHECK-NEXT: fmov x9, d3
-; CHECK-NEXT: mov x8, v3.d[1]
-; CHECK-NEXT: ucvtf s4, x10
-; CHECK-NEXT: fmov x10, d1
-; CHECK-NEXT: ucvtf s3, x9
-; CHECK-NEXT: mov x9, v1.d[1]
-; CHECK-NEXT: mov v2.s[1], v0.s[0]
-; CHECK-NEXT: ucvtf s0, x10
-; CHECK-NEXT: ucvtf s1, x8
-; CHECK-NEXT: mov v4.s[1], v5.s[0]
-; CHECK-NEXT: mov v2.s[2], v3.s[0]
-; CHECK-NEXT: ucvtf s3, x9
-; CHECK-NEXT: mov v4.s[2], v0.s[0]
-; CHECK-NEXT: movi v0.4s, #1
-; CHECK-NEXT: mov v2.s[3], v1.s[0]
-; CHECK-NEXT: movi v1.4s, #127, msl #8
-; CHECK-NEXT: mov v4.s[3], v3.s[0]
-; CHECK-NEXT: ushr v3.4s, v2.4s, #16
-; CHECK-NEXT: add v6.4s, v2.4s, v1.4s
-; CHECK-NEXT: ushr v5.4s, v4.4s, #16
-; CHECK-NEXT: add v1.4s, v4.4s, v1.4s
-; CHECK-NEXT: and v3.16b, v3.16b, v0.16b
-; CHECK-NEXT: and v0.16b, v5.16b, v0.16b
-; CHECK-NEXT: fcmeq v5.4s, v2.4s, v2.4s
-; CHECK-NEXT: orr v2.4s, #64, lsl #16
-; CHECK-NEXT: add v3.4s, v3.4s, v6.4s
-; CHECK-NEXT: fcmeq v6.4s, v4.4s, v4.4s
-; CHECK-NEXT: orr v4.4s, #64, lsl #16
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: mov v1.16b, v5.16b
-; CHECK-NEXT: bif v0.16b, v4.16b, v6.16b
-; CHECK-NEXT: bsl v1.16b, v3.16b, v2.16b
-; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v8i64_v8bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x9, v0.d[1]
+; CHECK-SD-NEXT: fmov x10, d0
+; CHECK-SD-NEXT: mov x8, v2.d[1]
+; CHECK-SD-NEXT: ucvtf s4, x10
+; CHECK-SD-NEXT: fmov x10, d1
+; CHECK-SD-NEXT: ucvtf s0, x9
+; CHECK-SD-NEXT: fmov x9, d2
+; CHECK-SD-NEXT: ucvtf s2, x8
+; CHECK-SD-NEXT: mov x8, v1.d[1]
+; CHECK-SD-NEXT: ucvtf s1, x9
+; CHECK-SD-NEXT: fmov x9, d3
+; CHECK-SD-NEXT: mov v4.s[1], v0.s[0]
+; CHECK-SD-NEXT: ucvtf s0, x10
+; CHECK-SD-NEXT: mov x10, v3.d[1]
+; CHECK-SD-NEXT: ucvtf s3, x9
+; CHECK-SD-NEXT: mov v1.s[1], v2.s[0]
+; CHECK-SD-NEXT: ucvtf s2, x8
+; CHECK-SD-NEXT: mov v4.s[2], v0.s[0]
+; CHECK-SD-NEXT: ucvtf s0, x10
+; CHECK-SD-NEXT: mov v1.s[2], v3.s[0]
+; CHECK-SD-NEXT: mov v4.s[3], v2.s[0]
+; CHECK-SD-NEXT: mov v1.s[3], v0.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v4.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v8i64_v8bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov x10, v1.d[1]
+; CHECK-GI-NEXT: ucvtf s0, x9
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: ucvtf s4, x8
+; CHECK-GI-NEXT: mov x8, v2.d[1]
+; CHECK-GI-NEXT: ucvtf s1, x9
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: ucvtf s5, x8
+; CHECK-GI-NEXT: mov v0.s[1], v4.s[0]
+; CHECK-GI-NEXT: ucvtf s4, x10
+; CHECK-GI-NEXT: ucvtf s2, x9
+; CHECK-GI-NEXT: fmov x9, d3
+; CHECK-GI-NEXT: mov x8, v3.d[1]
+; CHECK-GI-NEXT: ucvtf s3, x9
+; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
+; CHECK-GI-NEXT: mov v2.s[1], v5.s[0]
+; CHECK-GI-NEXT: ucvtf s1, x8
+; CHECK-GI-NEXT: mov v0.s[3], v4.s[0]
+; CHECK-GI-NEXT: mov v2.s[2], v3.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: mov v2.s[3], v1.s[0]
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <8 x i64> %a to <8 x bfloat>
ret <8 x bfloat> %c
}
define <16 x bfloat> @stofp_v16i64_v16bf16(<16 x i64> %a) {
-; CHECK-LABEL: stofp_v16i64_v16bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, v2.d[1]
-; CHECK-NEXT: fmov x11, d0
-; CHECK-NEXT: mov x9, v0.d[1]
-; CHECK-NEXT: fmov x10, d2
-; CHECK-NEXT: mov x12, v6.d[1]
-; CHECK-NEXT: scvtf s2, x11
-; CHECK-NEXT: fmov x11, d3
-; CHECK-NEXT: scvtf s16, x8
-; CHECK-NEXT: fmov x8, d6
-; CHECK-NEXT: scvtf s0, x10
-; CHECK-NEXT: mov x10, v4.d[1]
-; CHECK-NEXT: scvtf s17, x9
-; CHECK-NEXT: mov x9, v3.d[1]
-; CHECK-NEXT: scvtf s6, x12
-; CHECK-NEXT: fmov x12, d4
-; CHECK-NEXT: scvtf s4, x11
-; CHECK-NEXT: scvtf s3, x8
-; CHECK-NEXT: fmov x11, d7
-; CHECK-NEXT: mov x8, v1.d[1]
-; CHECK-NEXT: mov v0.s[1], v16.s[0]
-; CHECK-NEXT: scvtf s18, x10
-; CHECK-NEXT: scvtf s19, x12
-; CHECK-NEXT: fmov x10, d1
-; CHECK-NEXT: mov v2.s[1], v17.s[0]
-; CHECK-NEXT: mov x12, v5.d[1]
-; CHECK-NEXT: mov v3.s[1], v6.s[0]
-; CHECK-NEXT: scvtf s6, x11
-; CHECK-NEXT: fmov x11, d5
-; CHECK-NEXT: scvtf s1, x10
-; CHECK-NEXT: mov x10, v7.d[1]
-; CHECK-NEXT: scvtf s7, x9
-; CHECK-NEXT: mov v19.s[1], v18.s[0]
-; CHECK-NEXT: scvtf s16, x8
-; CHECK-NEXT: mov v0.s[2], v4.s[0]
-; CHECK-NEXT: scvtf s5, x11
-; CHECK-NEXT: mov v3.s[2], v6.s[0]
-; CHECK-NEXT: scvtf s4, x10
-; CHECK-NEXT: mov v2.s[2], v1.s[0]
-; CHECK-NEXT: scvtf s1, x12
-; CHECK-NEXT: mov v0.s[3], v7.s[0]
-; CHECK-NEXT: mov v19.s[2], v5.s[0]
-; CHECK-NEXT: mov v2.s[3], v16.s[0]
-; CHECK-NEXT: mov v3.s[3], v4.s[0]
-; CHECK-NEXT: movi v4.4s, #127, msl #8
-; CHECK-NEXT: ushr v5.4s, v0.4s, #16
-; CHECK-NEXT: mov v19.s[3], v1.s[0]
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ushr v6.4s, v2.4s, #16
-; CHECK-NEXT: ushr v7.4s, v3.4s, #16
-; CHECK-NEXT: add v17.4s, v0.4s, v4.4s
-; CHECK-NEXT: add v18.4s, v2.4s, v4.4s
-; CHECK-NEXT: add v20.4s, v3.4s, v4.4s
-; CHECK-NEXT: ushr v16.4s, v19.4s, #16
-; CHECK-NEXT: and v5.16b, v5.16b, v1.16b
-; CHECK-NEXT: add v4.4s, v19.4s, v4.4s
-; CHECK-NEXT: and v6.16b, v6.16b, v1.16b
-; CHECK-NEXT: and v7.16b, v7.16b, v1.16b
-; CHECK-NEXT: and v1.16b, v16.16b, v1.16b
-; CHECK-NEXT: add v5.4s, v5.4s, v17.4s
-; CHECK-NEXT: fcmeq v16.4s, v0.4s, v0.4s
-; CHECK-NEXT: add v6.4s, v6.4s, v18.4s
-; CHECK-NEXT: fcmeq v17.4s, v2.4s, v2.4s
-; CHECK-NEXT: fcmeq v18.4s, v3.4s, v3.4s
-; CHECK-NEXT: orr v0.4s, #64, lsl #16
-; CHECK-NEXT: add v7.4s, v7.4s, v20.4s
-; CHECK-NEXT: orr v2.4s, #64, lsl #16
-; CHECK-NEXT: add v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: fcmeq v4.4s, v19.4s, v19.4s
-; CHECK-NEXT: orr v3.4s, #64, lsl #16
-; CHECK-NEXT: orr v19.4s, #64, lsl #16
-; CHECK-NEXT: bit v0.16b, v5.16b, v16.16b
-; CHECK-NEXT: bit v2.16b, v6.16b, v17.16b
-; CHECK-NEXT: bit v3.16b, v7.16b, v18.16b
-; CHECK-NEXT: bif v1.16b, v19.16b, v4.16b
-; CHECK-NEXT: uzp2 v0.8h, v2.8h, v0.8h
-; CHECK-NEXT: uzp2 v1.8h, v1.8h, v3.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v16i64_v16bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov x12, d0
+; CHECK-SD-NEXT: mov x8, v0.d[1]
+; CHECK-SD-NEXT: mov x9, v4.d[1]
+; CHECK-SD-NEXT: mov x10, v2.d[1]
+; CHECK-SD-NEXT: fmov x11, d2
+; CHECK-SD-NEXT: mov x13, v1.d[1]
+; CHECK-SD-NEXT: scvtf s0, x12
+; CHECK-SD-NEXT: fmov x12, d4
+; CHECK-SD-NEXT: scvtf s2, x8
+; CHECK-SD-NEXT: mov x8, v6.d[1]
+; CHECK-SD-NEXT: scvtf s16, x9
+; CHECK-SD-NEXT: fmov x9, d1
+; CHECK-SD-NEXT: scvtf s1, x10
+; CHECK-SD-NEXT: fmov x10, d5
+; CHECK-SD-NEXT: scvtf s4, x12
+; CHECK-SD-NEXT: fmov x12, d6
+; CHECK-SD-NEXT: scvtf s6, x11
+; CHECK-SD-NEXT: mov x11, v5.d[1]
+; CHECK-SD-NEXT: scvtf s5, x9
+; CHECK-SD-NEXT: mov v0.s[1], v2.s[0]
+; CHECK-SD-NEXT: scvtf s2, x10
+; CHECK-SD-NEXT: scvtf s17, x12
+; CHECK-SD-NEXT: fmov x9, d3
+; CHECK-SD-NEXT: fmov x12, d7
+; CHECK-SD-NEXT: mov v4.s[1], v16.s[0]
+; CHECK-SD-NEXT: scvtf s16, x8
+; CHECK-SD-NEXT: mov x8, v3.d[1]
+; CHECK-SD-NEXT: mov x10, v7.d[1]
+; CHECK-SD-NEXT: mov v6.s[1], v1.s[0]
+; CHECK-SD-NEXT: scvtf s7, x11
+; CHECK-SD-NEXT: scvtf s3, x9
+; CHECK-SD-NEXT: scvtf s1, x12
+; CHECK-SD-NEXT: mov v0.s[2], v5.s[0]
+; CHECK-SD-NEXT: scvtf s5, x13
+; CHECK-SD-NEXT: mov v17.s[1], v16.s[0]
+; CHECK-SD-NEXT: mov v4.s[2], v2.s[0]
+; CHECK-SD-NEXT: scvtf s2, x8
+; CHECK-SD-NEXT: mov v6.s[2], v3.s[0]
+; CHECK-SD-NEXT: mov v0.s[3], v5.s[0]
+; CHECK-SD-NEXT: mov v17.s[2], v1.s[0]
+; CHECK-SD-NEXT: scvtf s1, x10
+; CHECK-SD-NEXT: mov v4.s[3], v7.s[0]
+; CHECK-SD-NEXT: mov v6.s[3], v2.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: mov v17.s[3], v1.s[0]
+; CHECK-SD-NEXT: bfcvtn v1.4h, v4.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v6.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v17.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v16i64_v16bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x10, d0
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov x9, v4.d[1]
+; CHECK-GI-NEXT: fmov x11, d1
+; CHECK-GI-NEXT: fmov x13, d2
+; CHECK-GI-NEXT: mov x12, v2.d[1]
+; CHECK-GI-NEXT: scvtf s0, x10
+; CHECK-GI-NEXT: fmov x10, d4
+; CHECK-GI-NEXT: scvtf s16, x8
+; CHECK-GI-NEXT: scvtf s17, x9
+; CHECK-GI-NEXT: mov x8, v6.d[1]
+; CHECK-GI-NEXT: mov x9, v1.d[1]
+; CHECK-GI-NEXT: scvtf s1, x11
+; CHECK-GI-NEXT: scvtf s4, x13
+; CHECK-GI-NEXT: scvtf s2, x10
+; CHECK-GI-NEXT: fmov x11, d5
+; CHECK-GI-NEXT: fmov x13, d6
+; CHECK-GI-NEXT: mov x10, v5.d[1]
+; CHECK-GI-NEXT: scvtf s6, x12
+; CHECK-GI-NEXT: scvtf s19, x8
+; CHECK-GI-NEXT: mov v0.s[1], v16.s[0]
+; CHECK-GI-NEXT: mov x8, v3.d[1]
+; CHECK-GI-NEXT: scvtf s18, x11
+; CHECK-GI-NEXT: scvtf s5, x13
+; CHECK-GI-NEXT: scvtf s16, x9
+; CHECK-GI-NEXT: mov v2.s[1], v17.s[0]
+; CHECK-GI-NEXT: fmov x9, d3
+; CHECK-GI-NEXT: fmov x11, d7
+; CHECK-GI-NEXT: mov v4.s[1], v6.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
+; CHECK-GI-NEXT: scvtf s1, x8
+; CHECK-GI-NEXT: scvtf s3, x9
+; CHECK-GI-NEXT: mov x9, v7.d[1]
+; CHECK-GI-NEXT: scvtf s7, x10
+; CHECK-GI-NEXT: scvtf s17, x11
+; CHECK-GI-NEXT: mov v2.s[2], v18.s[0]
+; CHECK-GI-NEXT: mov v5.s[1], v19.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v16.s[0]
+; CHECK-GI-NEXT: scvtf s6, x9
+; CHECK-GI-NEXT: mov v4.s[2], v3.s[0]
+; CHECK-GI-NEXT: mov v2.s[3], v7.s[0]
+; CHECK-GI-NEXT: mov v5.s[2], v17.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: mov v4.s[3], v1.s[0]
+; CHECK-GI-NEXT: mov v5.s[3], v6.s[0]
+; CHECK-GI-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <16 x i64> %a to <16 x bfloat>
ret <16 x bfloat> %c
}
define <16 x bfloat> @utofp_v16i64_v16bf16(<16 x i64> %a) {
-; CHECK-LABEL: utofp_v16i64_v16bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, v2.d[1]
-; CHECK-NEXT: fmov x11, d0
-; CHECK-NEXT: mov x9, v0.d[1]
-; CHECK-NEXT: fmov x10, d2
-; CHECK-NEXT: mov x12, v6.d[1]
-; CHECK-NEXT: ucvtf s2, x11
-; CHECK-NEXT: fmov x11, d3
-; CHECK-NEXT: ucvtf s16, x8
-; CHECK-NEXT: fmov x8, d6
-; CHECK-NEXT: ucvtf s0, x10
-; CHECK-NEXT: mov x10, v4.d[1]
-; CHECK-NEXT: ucvtf s17, x9
-; CHECK-NEXT: mov x9, v3.d[1]
-; CHECK-NEXT: ucvtf s6, x12
-; CHECK-NEXT: fmov x12, d4
-; CHECK-NEXT: ucvtf s4, x11
-; CHECK-NEXT: ucvtf s3, x8
-; CHECK-NEXT: fmov x11, d7
-; CHECK-NEXT: mov x8, v1.d[1]
-; CHECK-NEXT: mov v0.s[1], v16.s[0]
-; CHECK-NEXT: ucvtf s18, x10
-; CHECK-NEXT: ucvtf s19, x12
-; CHECK-NEXT: fmov x10, d1
-; CHECK-NEXT: mov v2.s[1], v17.s[0]
-; CHECK-NEXT: mov x12, v5.d[1]
-; CHECK-NEXT: mov v3.s[1], v6.s[0]
-; CHECK-NEXT: ucvtf s6, x11
-; CHECK-NEXT: fmov x11, d5
-; CHECK-NEXT: ucvtf s1, x10
-; CHECK-NEXT: mov x10, v7.d[1]
-; CHECK-NEXT: ucvtf s7, x9
-; CHECK-NEXT: mov v19.s[1], v18.s[0]
-; CHECK-NEXT: ucvtf s16, x8
-; CHECK-NEXT: mov v0.s[2], v4.s[0]
-; CHECK-NEXT: ucvtf s5, x11
-; CHECK-NEXT: mov v3.s[2], v6.s[0]
-; CHECK-NEXT: ucvtf s4, x10
-; CHECK-NEXT: mov v2.s[2], v1.s[0]
-; CHECK-NEXT: ucvtf s1, x12
-; CHECK-NEXT: mov v0.s[3], v7.s[0]
-; CHECK-NEXT: mov v19.s[2], v5.s[0]
-; CHECK-NEXT: mov v2.s[3], v16.s[0]
-; CHECK-NEXT: mov v3.s[3], v4.s[0]
-; CHECK-NEXT: movi v4.4s, #127, msl #8
-; CHECK-NEXT: ushr v5.4s, v0.4s, #16
-; CHECK-NEXT: mov v19.s[3], v1.s[0]
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ushr v6.4s, v2.4s, #16
-; CHECK-NEXT: ushr v7.4s, v3.4s, #16
-; CHECK-NEXT: add v17.4s, v0.4s, v4.4s
-; CHECK-NEXT: add v18.4s, v2.4s, v4.4s
-; CHECK-NEXT: add v20.4s, v3.4s, v4.4s
-; CHECK-NEXT: ushr v16.4s, v19.4s, #16
-; CHECK-NEXT: and v5.16b, v5.16b, v1.16b
-; CHECK-NEXT: add v4.4s, v19.4s, v4.4s
-; CHECK-NEXT: and v6.16b, v6.16b, v1.16b
-; CHECK-NEXT: and v7.16b, v7.16b, v1.16b
-; CHECK-NEXT: and v1.16b, v16.16b, v1.16b
-; CHECK-NEXT: add v5.4s, v5.4s, v17.4s
-; CHECK-NEXT: fcmeq v16.4s, v0.4s, v0.4s
-; CHECK-NEXT: add v6.4s, v6.4s, v18.4s
-; CHECK-NEXT: fcmeq v17.4s, v2.4s, v2.4s
-; CHECK-NEXT: fcmeq v18.4s, v3.4s, v3.4s
-; CHECK-NEXT: orr v0.4s, #64, lsl #16
-; CHECK-NEXT: add v7.4s, v7.4s, v20.4s
-; CHECK-NEXT: orr v2.4s, #64, lsl #16
-; CHECK-NEXT: add v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: fcmeq v4.4s, v19.4s, v19.4s
-; CHECK-NEXT: orr v3.4s, #64, lsl #16
-; CHECK-NEXT: orr v19.4s, #64, lsl #16
-; CHECK-NEXT: bit v0.16b, v5.16b, v16.16b
-; CHECK-NEXT: bit v2.16b, v6.16b, v17.16b
-; CHECK-NEXT: bit v3.16b, v7.16b, v18.16b
-; CHECK-NEXT: bif v1.16b, v19.16b, v4.16b
-; CHECK-NEXT: uzp2 v0.8h, v2.8h, v0.8h
-; CHECK-NEXT: uzp2 v1.8h, v1.8h, v3.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v16i64_v16bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov x12, d0
+; CHECK-SD-NEXT: mov x8, v0.d[1]
+; CHECK-SD-NEXT: mov x9, v4.d[1]
+; CHECK-SD-NEXT: mov x10, v2.d[1]
+; CHECK-SD-NEXT: fmov x11, d2
+; CHECK-SD-NEXT: mov x13, v1.d[1]
+; CHECK-SD-NEXT: ucvtf s0, x12
+; CHECK-SD-NEXT: fmov x12, d4
+; CHECK-SD-NEXT: ucvtf s2, x8
+; CHECK-SD-NEXT: mov x8, v6.d[1]
+; CHECK-SD-NEXT: ucvtf s16, x9
+; CHECK-SD-NEXT: fmov x9, d1
+; CHECK-SD-NEXT: ucvtf s1, x10
+; CHECK-SD-NEXT: fmov x10, d5
+; CHECK-SD-NEXT: ucvtf s4, x12
+; CHECK-SD-NEXT: fmov x12, d6
+; CHECK-SD-NEXT: ucvtf s6, x11
+; CHECK-SD-NEXT: mov x11, v5.d[1]
+; CHECK-SD-NEXT: ucvtf s5, x9
+; CHECK-SD-NEXT: mov v0.s[1], v2.s[0]
+; CHECK-SD-NEXT: ucvtf s2, x10
+; CHECK-SD-NEXT: ucvtf s17, x12
+; CHECK-SD-NEXT: fmov x9, d3
+; CHECK-SD-NEXT: fmov x12, d7
+; CHECK-SD-NEXT: mov v4.s[1], v16.s[0]
+; CHECK-SD-NEXT: ucvtf s16, x8
+; CHECK-SD-NEXT: mov x8, v3.d[1]
+; CHECK-SD-NEXT: mov x10, v7.d[1]
+; CHECK-SD-NEXT: mov v6.s[1], v1.s[0]
+; CHECK-SD-NEXT: ucvtf s7, x11
+; CHECK-SD-NEXT: ucvtf s3, x9
+; CHECK-SD-NEXT: ucvtf s1, x12
+; CHECK-SD-NEXT: mov v0.s[2], v5.s[0]
+; CHECK-SD-NEXT: ucvtf s5, x13
+; CHECK-SD-NEXT: mov v17.s[1], v16.s[0]
+; CHECK-SD-NEXT: mov v4.s[2], v2.s[0]
+; CHECK-SD-NEXT: ucvtf s2, x8
+; CHECK-SD-NEXT: mov v6.s[2], v3.s[0]
+; CHECK-SD-NEXT: mov v0.s[3], v5.s[0]
+; CHECK-SD-NEXT: mov v17.s[2], v1.s[0]
+; CHECK-SD-NEXT: ucvtf s1, x10
+; CHECK-SD-NEXT: mov v4.s[3], v7.s[0]
+; CHECK-SD-NEXT: mov v6.s[3], v2.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: mov v17.s[3], v1.s[0]
+; CHECK-SD-NEXT: bfcvtn v1.4h, v4.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v6.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v17.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v16i64_v16bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x10, d0
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov x9, v4.d[1]
+; CHECK-GI-NEXT: fmov x11, d1
+; CHECK-GI-NEXT: fmov x13, d2
+; CHECK-GI-NEXT: mov x12, v2.d[1]
+; CHECK-GI-NEXT: ucvtf s0, x10
+; CHECK-GI-NEXT: fmov x10, d4
+; CHECK-GI-NEXT: ucvtf s16, x8
+; CHECK-GI-NEXT: ucvtf s17, x9
+; CHECK-GI-NEXT: mov x8, v6.d[1]
+; CHECK-GI-NEXT: mov x9, v1.d[1]
+; CHECK-GI-NEXT: ucvtf s1, x11
+; CHECK-GI-NEXT: ucvtf s4, x13
+; CHECK-GI-NEXT: ucvtf s2, x10
+; CHECK-GI-NEXT: fmov x11, d5
+; CHECK-GI-NEXT: fmov x13, d6
+; CHECK-GI-NEXT: mov x10, v5.d[1]
+; CHECK-GI-NEXT: ucvtf s6, x12
+; CHECK-GI-NEXT: ucvtf s19, x8
+; CHECK-GI-NEXT: mov v0.s[1], v16.s[0]
+; CHECK-GI-NEXT: mov x8, v3.d[1]
+; CHECK-GI-NEXT: ucvtf s18, x11
+; CHECK-GI-NEXT: ucvtf s5, x13
+; CHECK-GI-NEXT: ucvtf s16, x9
+; CHECK-GI-NEXT: mov v2.s[1], v17.s[0]
+; CHECK-GI-NEXT: fmov x9, d3
+; CHECK-GI-NEXT: fmov x11, d7
+; CHECK-GI-NEXT: mov v4.s[1], v6.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
+; CHECK-GI-NEXT: ucvtf s1, x8
+; CHECK-GI-NEXT: ucvtf s3, x9
+; CHECK-GI-NEXT: mov x9, v7.d[1]
+; CHECK-GI-NEXT: ucvtf s7, x10
+; CHECK-GI-NEXT: ucvtf s17, x11
+; CHECK-GI-NEXT: mov v2.s[2], v18.s[0]
+; CHECK-GI-NEXT: mov v5.s[1], v19.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v16.s[0]
+; CHECK-GI-NEXT: ucvtf s6, x9
+; CHECK-GI-NEXT: mov v4.s[2], v3.s[0]
+; CHECK-GI-NEXT: mov v2.s[3], v7.s[0]
+; CHECK-GI-NEXT: mov v5.s[2], v17.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: mov v4.s[3], v1.s[0]
+; CHECK-GI-NEXT: mov v5.s[3], v6.s[0]
+; CHECK-GI-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <16 x i64> %a to <16 x bfloat>
ret <16 x bfloat> %c
}
define <32 x bfloat> @stofp_v32i64_v32bf16(<32 x i64> %a) {
-; CHECK-LABEL: stofp_v32i64_v32bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x8, x9, [sp, #32]
-; CHECK-NEXT: mov x13, v2.d[1]
-; CHECK-NEXT: ldp x10, x12, [sp, #96]
-; CHECK-NEXT: fmov x14, d3
-; CHECK-NEXT: movi v17.4s, #1
-; CHECK-NEXT: scvtf s18, x9
-; CHECK-NEXT: scvtf s16, x8
-; CHECK-NEXT: ldp x8, x9, [sp, #48]
-; CHECK-NEXT: scvtf s23, x12
-; CHECK-NEXT: scvtf s20, x10
-; CHECK-NEXT: mov x10, v0.d[1]
-; CHECK-NEXT: scvtf s27, x13
-; CHECK-NEXT: scvtf s21, x8
-; CHECK-NEXT: ldp x8, x11, [sp]
-; CHECK-NEXT: mov v16.s[1], v18.s[0]
-; CHECK-NEXT: scvtf s24, x9
-; CHECK-NEXT: movi v18.4s, #127, msl #8
-; CHECK-NEXT: mov v20.s[1], v23.s[0]
-; CHECK-NEXT: scvtf s22, x11
-; CHECK-NEXT: ldp x11, x12, [sp, #16]
-; CHECK-NEXT: scvtf s19, x8
-; CHECK-NEXT: mov x8, v3.d[1]
-; CHECK-NEXT: mov v16.s[2], v21.s[0]
-; CHECK-NEXT: scvtf s25, x11
-; CHECK-NEXT: ldp x9, x11, [sp, #112]
-; CHECK-NEXT: mov v19.s[1], v22.s[0]
-; CHECK-NEXT: scvtf s22, x12
-; CHECK-NEXT: scvtf s26, x9
-; CHECK-NEXT: ldp x9, x12, [sp, #64]
-; CHECK-NEXT: scvtf s23, x11
-; CHECK-NEXT: mov v16.s[3], v24.s[0]
-; CHECK-NEXT: fmov x11, d2
-; CHECK-NEXT: scvtf s24, x12
-; CHECK-NEXT: scvtf s2, x9
-; CHECK-NEXT: mov x9, v6.d[1]
-; CHECK-NEXT: ldp x12, x13, [sp, #80]
-; CHECK-NEXT: scvtf s21, x11
-; CHECK-NEXT: mov x11, v4.d[1]
-; CHECK-NEXT: mov v19.s[2], v25.s[0]
-; CHECK-NEXT: mov v20.s[2], v26.s[0]
-; CHECK-NEXT: ushr v25.4s, v16.4s, #16
-; CHECK-NEXT: scvtf s26, x14
-; CHECK-NEXT: scvtf s3, x12
-; CHECK-NEXT: mov v2.s[1], v24.s[0]
-; CHECK-NEXT: scvtf s24, x10
-; CHECK-NEXT: fmov x10, d6
-; CHECK-NEXT: fmov x12, d0
-; CHECK-NEXT: scvtf s6, x9
-; CHECK-NEXT: mov v21.s[1], v27.s[0]
-; CHECK-NEXT: scvtf s27, x11
-; CHECK-NEXT: fmov x11, d7
-; CHECK-NEXT: mov v19.s[3], v22.s[0]
-; CHECK-NEXT: mov v20.s[3], v23.s[0]
-; CHECK-NEXT: add v22.4s, v16.4s, v18.4s
-; CHECK-NEXT: mov v2.s[2], v3.s[0]
-; CHECK-NEXT: scvtf s3, x10
-; CHECK-NEXT: fmov x10, d4
-; CHECK-NEXT: scvtf s0, x12
-; CHECK-NEXT: and v23.16b, v25.16b, v17.16b
-; CHECK-NEXT: mov x9, v1.d[1]
-; CHECK-NEXT: fmov x12, d5
-; CHECK-NEXT: mov v21.s[2], v26.s[0]
-; CHECK-NEXT: scvtf s25, x13
-; CHECK-NEXT: scvtf s4, x10
-; CHECK-NEXT: fmov x10, d1
-; CHECK-NEXT: add v26.4s, v20.4s, v18.4s
-; CHECK-NEXT: mov v3.s[1], v6.s[0]
-; CHECK-NEXT: scvtf s6, x11
-; CHECK-NEXT: mov x11, v5.d[1]
-; CHECK-NEXT: scvtf s5, x8
-; CHECK-NEXT: mov v0.s[1], v24.s[0]
-; CHECK-NEXT: add v22.4s, v23.4s, v22.4s
-; CHECK-NEXT: scvtf s1, x10
-; CHECK-NEXT: mov x10, v7.d[1]
-; CHECK-NEXT: scvtf s7, x12
-; CHECK-NEXT: mov v4.s[1], v27.s[0]
-; CHECK-NEXT: ushr v23.4s, v19.4s, #16
-; CHECK-NEXT: mov v2.s[3], v25.s[0]
-; CHECK-NEXT: mov v3.s[2], v6.s[0]
-; CHECK-NEXT: add v25.4s, v19.4s, v18.4s
-; CHECK-NEXT: ushr v24.4s, v20.4s, #16
-; CHECK-NEXT: mov v21.s[3], v5.s[0]
-; CHECK-NEXT: scvtf s5, x11
-; CHECK-NEXT: fcmeq v29.4s, v20.4s, v20.4s
-; CHECK-NEXT: scvtf s6, x10
-; CHECK-NEXT: and v23.16b, v23.16b, v17.16b
-; CHECK-NEXT: mov v0.s[2], v1.s[0]
-; CHECK-NEXT: scvtf s1, x9
-; CHECK-NEXT: mov v4.s[2], v7.s[0]
-; CHECK-NEXT: and v24.16b, v24.16b, v17.16b
-; CHECK-NEXT: fcmeq v7.4s, v16.4s, v16.4s
-; CHECK-NEXT: orr v16.4s, #64, lsl #16
-; CHECK-NEXT: fcmeq v31.4s, v2.4s, v2.4s
-; CHECK-NEXT: add v27.4s, v21.4s, v18.4s
-; CHECK-NEXT: orr v20.4s, #64, lsl #16
-; CHECK-NEXT: mov v3.s[3], v6.s[0]
-; CHECK-NEXT: add v6.4s, v23.4s, v25.4s
-; CHECK-NEXT: ushr v23.4s, v21.4s, #16
-; CHECK-NEXT: mov v0.s[3], v1.s[0]
-; CHECK-NEXT: mov v4.s[3], v5.s[0]
-; CHECK-NEXT: ushr v1.4s, v2.4s, #16
-; CHECK-NEXT: add v24.4s, v24.4s, v26.4s
-; CHECK-NEXT: add v25.4s, v2.4s, v18.4s
-; CHECK-NEXT: fcmeq v5.4s, v19.4s, v19.4s
-; CHECK-NEXT: and v23.16b, v23.16b, v17.16b
-; CHECK-NEXT: orr v19.4s, #64, lsl #16
-; CHECK-NEXT: orr v2.4s, #64, lsl #16
-; CHECK-NEXT: ushr v28.4s, v3.4s, #16
-; CHECK-NEXT: and v1.16b, v1.16b, v17.16b
-; CHECK-NEXT: bsl v7.16b, v22.16b, v16.16b
-; CHECK-NEXT: ushr v26.4s, v0.4s, #16
-; CHECK-NEXT: ushr v30.4s, v4.4s, #16
-; CHECK-NEXT: add v23.4s, v23.4s, v27.4s
-; CHECK-NEXT: bsl v5.16b, v6.16b, v19.16b
-; CHECK-NEXT: mov v6.16b, v29.16b
-; CHECK-NEXT: and v27.16b, v28.16b, v17.16b
-; CHECK-NEXT: add v28.4s, v3.4s, v18.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v25.4s
-; CHECK-NEXT: and v25.16b, v26.16b, v17.16b
-; CHECK-NEXT: add v26.4s, v0.4s, v18.4s
-; CHECK-NEXT: and v17.16b, v30.16b, v17.16b
-; CHECK-NEXT: add v18.4s, v4.4s, v18.4s
-; CHECK-NEXT: fcmeq v30.4s, v21.4s, v21.4s
-; CHECK-NEXT: orr v21.4s, #64, lsl #16
-; CHECK-NEXT: add v27.4s, v27.4s, v28.4s
-; CHECK-NEXT: fcmeq v28.4s, v3.4s, v3.4s
-; CHECK-NEXT: orr v3.4s, #64, lsl #16
-; CHECK-NEXT: add v25.4s, v25.4s, v26.4s
-; CHECK-NEXT: fcmeq v26.4s, v0.4s, v0.4s
-; CHECK-NEXT: orr v0.4s, #64, lsl #16
-; CHECK-NEXT: add v17.4s, v17.4s, v18.4s
-; CHECK-NEXT: fcmeq v18.4s, v4.4s, v4.4s
-; CHECK-NEXT: orr v4.4s, #64, lsl #16
-; CHECK-NEXT: mov v16.16b, v30.16b
-; CHECK-NEXT: bsl v6.16b, v24.16b, v20.16b
-; CHECK-NEXT: bif v1.16b, v2.16b, v31.16b
-; CHECK-NEXT: mov v19.16b, v28.16b
-; CHECK-NEXT: uzp2 v2.8h, v5.8h, v7.8h
-; CHECK-NEXT: bit v0.16b, v25.16b, v26.16b
-; CHECK-NEXT: bsl v16.16b, v23.16b, v21.16b
-; CHECK-NEXT: bit v4.16b, v17.16b, v18.16b
-; CHECK-NEXT: bsl v19.16b, v27.16b, v3.16b
-; CHECK-NEXT: uzp2 v3.8h, v1.8h, v6.8h
-; CHECK-NEXT: uzp2 v0.8h, v0.8h, v16.8h
-; CHECK-NEXT: uzp2 v1.8h, v4.8h, v19.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v32i64_v32bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x8, x9, [sp, #32]
+; CHECK-SD-NEXT: mov x14, v2.d[1]
+; CHECK-SD-NEXT: ldp x10, x11, [sp]
+; CHECK-SD-NEXT: ldp x12, x13, [sp, #96]
+; CHECK-SD-NEXT: scvtf s18, x9
+; CHECK-SD-NEXT: scvtf s16, x8
+; CHECK-SD-NEXT: ldp x8, x9, [sp, #64]
+; CHECK-SD-NEXT: scvtf s17, x10
+; CHECK-SD-NEXT: scvtf s19, x11
+; CHECK-SD-NEXT: scvtf s21, x13
+; CHECK-SD-NEXT: mov x13, v4.d[1]
+; CHECK-SD-NEXT: scvtf s20, x9
+; CHECK-SD-NEXT: ldp x10, x9, [sp, #16]
+; CHECK-SD-NEXT: mov v16.s[1], v18.s[0]
+; CHECK-SD-NEXT: scvtf s18, x8
+; CHECK-SD-NEXT: mov v17.s[1], v19.s[0]
+; CHECK-SD-NEXT: scvtf s19, x12
+; CHECK-SD-NEXT: mov x12, v0.d[1]
+; CHECK-SD-NEXT: scvtf s22, x10
+; CHECK-SD-NEXT: ldp x11, x10, [sp, #80]
+; CHECK-SD-NEXT: ldp x15, x8, [sp, #48]
+; CHECK-SD-NEXT: mov v18.s[1], v20.s[0]
+; CHECK-SD-NEXT: scvtf s23, x11
+; CHECK-SD-NEXT: fmov x11, d2
+; CHECK-SD-NEXT: mov v19.s[1], v21.s[0]
+; CHECK-SD-NEXT: mov v17.s[2], v22.s[0]
+; CHECK-SD-NEXT: scvtf s22, x14
+; CHECK-SD-NEXT: fmov x14, d1
+; CHECK-SD-NEXT: scvtf s2, x15
+; CHECK-SD-NEXT: scvtf s20, x11
+; CHECK-SD-NEXT: fmov x11, d0
+; CHECK-SD-NEXT: scvtf s0, x12
+; CHECK-SD-NEXT: fmov x12, d4
+; CHECK-SD-NEXT: mov v18.s[2], v23.s[0]
+; CHECK-SD-NEXT: scvtf s23, x9
+; CHECK-SD-NEXT: mov x9, v6.d[1]
+; CHECK-SD-NEXT: scvtf s21, x11
+; CHECK-SD-NEXT: mov x11, v1.d[1]
+; CHECK-SD-NEXT: scvtf s1, x13
+; CHECK-SD-NEXT: scvtf s4, x12
+; CHECK-SD-NEXT: fmov x12, d6
+; CHECK-SD-NEXT: mov v20.s[1], v22.s[0]
+; CHECK-SD-NEXT: mov x13, v5.d[1]
+; CHECK-SD-NEXT: mov v16.s[2], v2.s[0]
+; CHECK-SD-NEXT: mov v17.s[3], v23.s[0]
+; CHECK-SD-NEXT: scvtf s6, x9
+; CHECK-SD-NEXT: scvtf s2, x8
+; CHECK-SD-NEXT: mov v21.s[1], v0.s[0]
+; CHECK-SD-NEXT: scvtf s0, x14
+; CHECK-SD-NEXT: scvtf s22, x12
+; CHECK-SD-NEXT: fmov x14, d5
+; CHECK-SD-NEXT: mov v4.s[1], v1.s[0]
+; CHECK-SD-NEXT: ldp x9, x12, [sp, #112]
+; CHECK-SD-NEXT: mov v16.s[3], v2.s[0]
+; CHECK-SD-NEXT: bfcvtn v2.4h, v17.4s
+; CHECK-SD-NEXT: scvtf s1, x14
+; CHECK-SD-NEXT: fmov x14, d3
+; CHECK-SD-NEXT: mov v22.s[1], v6.s[0]
+; CHECK-SD-NEXT: scvtf s6, x11
+; CHECK-SD-NEXT: fmov x11, d7
+; CHECK-SD-NEXT: scvtf s5, x9
+; CHECK-SD-NEXT: mov x9, v3.d[1]
+; CHECK-SD-NEXT: scvtf s3, x10
+; CHECK-SD-NEXT: mov v21.s[2], v0.s[0]
+; CHECK-SD-NEXT: scvtf s0, x14
+; CHECK-SD-NEXT: mov x10, v7.d[1]
+; CHECK-SD-NEXT: bfcvtn2 v2.8h, v16.4s
+; CHECK-SD-NEXT: scvtf s7, x11
+; CHECK-SD-NEXT: mov v4.s[2], v1.s[0]
+; CHECK-SD-NEXT: scvtf s1, x13
+; CHECK-SD-NEXT: mov v19.s[2], v5.s[0]
+; CHECK-SD-NEXT: mov v18.s[3], v3.s[0]
+; CHECK-SD-NEXT: mov v21.s[3], v6.s[0]
+; CHECK-SD-NEXT: scvtf s3, x9
+; CHECK-SD-NEXT: mov v20.s[2], v0.s[0]
+; CHECK-SD-NEXT: scvtf s0, x12
+; CHECK-SD-NEXT: mov v22.s[2], v7.s[0]
+; CHECK-SD-NEXT: mov v4.s[3], v1.s[0]
+; CHECK-SD-NEXT: scvtf s1, x10
+; CHECK-SD-NEXT: mov v19.s[3], v0.s[0]
+; CHECK-SD-NEXT: mov v20.s[3], v3.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v21.4s
+; CHECK-SD-NEXT: bfcvtn v3.4h, v18.4s
+; CHECK-SD-NEXT: mov v22.s[3], v1.s[0]
+; CHECK-SD-NEXT: bfcvtn v1.4h, v4.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v20.4s
+; CHECK-SD-NEXT: bfcvtn2 v3.8h, v19.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v22.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v32i64_v32bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d10, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset b8, -8
+; CHECK-GI-NEXT: .cfi_offset b9, -16
+; CHECK-GI-NEXT: .cfi_offset b10, -32
+; CHECK-GI-NEXT: mov x9, v1.d[1]
+; CHECK-GI-NEXT: fmov x10, d0
+; CHECK-GI-NEXT: mov x11, v2.d[1]
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: ldp q26, q23, [sp, #32]
+; CHECK-GI-NEXT: fmov x12, d4
+; CHECK-GI-NEXT: mov x13, v6.d[1]
+; CHECK-GI-NEXT: scvtf s0, x10
+; CHECK-GI-NEXT: fmov x10, d1
+; CHECK-GI-NEXT: scvtf s1, x9
+; CHECK-GI-NEXT: mov x9, v4.d[1]
+; CHECK-GI-NEXT: scvtf s20, x11
+; CHECK-GI-NEXT: fmov x11, d3
+; CHECK-GI-NEXT: ldp q30, q27, [sp, #96]
+; CHECK-GI-NEXT: scvtf s18, x10
+; CHECK-GI-NEXT: mov x10, v5.d[1]
+; CHECK-GI-NEXT: scvtf s28, x8
+; CHECK-GI-NEXT: fmov x8, d2
+; CHECK-GI-NEXT: ldp q24, q22, [sp, #64]
+; CHECK-GI-NEXT: scvtf s19, x11
+; CHECK-GI-NEXT: fmov x11, d5
+; CHECK-GI-NEXT: scvtf s2, x12
+; CHECK-GI-NEXT: scvtf s8, x9
+; CHECK-GI-NEXT: ldp q31, q17, [sp, #128]
+; CHECK-GI-NEXT: fmov x9, d6
+; CHECK-GI-NEXT: fmov x12, d7
+; CHECK-GI-NEXT: scvtf s16, x8
+; CHECK-GI-NEXT: mov x8, v3.d[1]
+; CHECK-GI-NEXT: scvtf s21, x11
+; CHECK-GI-NEXT: scvtf s3, x10
+; CHECK-GI-NEXT: mov x10, v26.d[1]
+; CHECK-GI-NEXT: mov x11, v23.d[1]
+; CHECK-GI-NEXT: scvtf s25, x13
+; CHECK-GI-NEXT: scvtf s4, x9
+; CHECK-GI-NEXT: mov x9, v7.d[1]
+; CHECK-GI-NEXT: fmov x13, d26
+; CHECK-GI-NEXT: scvtf s7, x12
+; CHECK-GI-NEXT: mov x12, v30.d[1]
+; CHECK-GI-NEXT: mov x14, v24.d[1]
+; CHECK-GI-NEXT: mov v0.s[1], v28.s[0]
+; CHECK-GI-NEXT: mov v2.s[1], v8.s[0]
+; CHECK-GI-NEXT: mov v16.s[1], v20.s[0]
+; CHECK-GI-NEXT: scvtf s5, x13
+; CHECK-GI-NEXT: scvtf s10, x10
+; CHECK-GI-NEXT: fmov x10, d23
+; CHECK-GI-NEXT: fmov x13, d24
+; CHECK-GI-NEXT: scvtf s23, x11
+; CHECK-GI-NEXT: fmov x11, d30
+; CHECK-GI-NEXT: scvtf s9, x12
+; CHECK-GI-NEXT: fmov x12, d22
+; CHECK-GI-NEXT: scvtf s29, x14
+; CHECK-GI-NEXT: fmov x14, d27
+; CHECK-GI-NEXT: scvtf s26, x10
+; CHECK-GI-NEXT: mov x10, v22.d[1]
+; CHECK-GI-NEXT: scvtf s6, x13
+; CHECK-GI-NEXT: mov x13, v31.d[1]
+; CHECK-GI-NEXT: scvtf s24, x11
+; CHECK-GI-NEXT: mov x11, v27.d[1]
+; CHECK-GI-NEXT: scvtf s27, x12
+; CHECK-GI-NEXT: fmov x12, d31
+; CHECK-GI-NEXT: scvtf s30, x14
+; CHECK-GI-NEXT: mov v5.s[1], v10.s[0]
+; CHECK-GI-NEXT: mov v4.s[1], v25.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v18.s[0]
+; CHECK-GI-NEXT: mov v2.s[2], v21.s[0]
+; CHECK-GI-NEXT: scvtf s18, x8
+; CHECK-GI-NEXT: scvtf s22, x12
+; CHECK-GI-NEXT: scvtf s31, x13
+; CHECK-GI-NEXT: mov v24.s[1], v9.s[0]
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: fmov x12, d17
+; CHECK-GI-NEXT: scvtf s28, x11
+; CHECK-GI-NEXT: mov x11, v17.d[1]
+; CHECK-GI-NEXT: mov v6.s[1], v29.s[0]
+; CHECK-GI-NEXT: mov v5.s[2], v26.s[0]
+; CHECK-GI-NEXT: scvtf s20, x9
+; CHECK-GI-NEXT: scvtf s21, x10
+; CHECK-GI-NEXT: scvtf s17, x12
+; CHECK-GI-NEXT: mov v22.s[1], v31.s[0]
+; CHECK-GI-NEXT: mov v24.s[2], v30.s[0]
+; CHECK-GI-NEXT: mov v16.s[2], v19.s[0]
+; CHECK-GI-NEXT: mov v4.s[2], v7.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-GI-NEXT: scvtf s25, x11
+; CHECK-GI-NEXT: mov v6.s[2], v27.s[0]
+; CHECK-GI-NEXT: mov v2.s[3], v3.s[0]
+; CHECK-GI-NEXT: mov v5.s[3], v23.s[0]
+; CHECK-GI-NEXT: mov v22.s[2], v17.s[0]
+; CHECK-GI-NEXT: mov v24.s[3], v28.s[0]
+; CHECK-GI-NEXT: mov v16.s[3], v18.s[0]
+; CHECK-GI-NEXT: mov v4.s[3], v20.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: mov v6.s[3], v21.s[0]
+; CHECK-GI-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn v2.4h, v5.4s
+; CHECK-GI-NEXT: mov v22.s[3], v25.s[0]
+; CHECK-GI-NEXT: bfcvtn v3.4h, v24.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v16.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v2.8h, v6.4s
+; CHECK-GI-NEXT: bfcvtn2 v3.8h, v22.4s
+; CHECK-GI-NEXT: ldr d10, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <32 x i64> %a to <32 x bfloat>
ret <32 x bfloat> %c
}
define <32 x bfloat> @utofp_v32i64_v32bf16(<32 x i64> %a) {
-; CHECK-LABEL: utofp_v32i64_v32bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldp x8, x9, [sp, #32]
-; CHECK-NEXT: mov x13, v2.d[1]
-; CHECK-NEXT: ldp x10, x12, [sp, #96]
-; CHECK-NEXT: fmov x14, d3
-; CHECK-NEXT: movi v17.4s, #1
-; CHECK-NEXT: ucvtf s18, x9
-; CHECK-NEXT: ucvtf s16, x8
-; CHECK-NEXT: ldp x8, x9, [sp, #48]
-; CHECK-NEXT: ucvtf s23, x12
-; CHECK-NEXT: ucvtf s20, x10
-; CHECK-NEXT: mov x10, v0.d[1]
-; CHECK-NEXT: ucvtf s27, x13
-; CHECK-NEXT: ucvtf s21, x8
-; CHECK-NEXT: ldp x8, x11, [sp]
-; CHECK-NEXT: mov v16.s[1], v18.s[0]
-; CHECK-NEXT: ucvtf s24, x9
-; CHECK-NEXT: movi v18.4s, #127, msl #8
-; CHECK-NEXT: mov v20.s[1], v23.s[0]
-; CHECK-NEXT: ucvtf s22, x11
-; CHECK-NEXT: ldp x11, x12, [sp, #16]
-; CHECK-NEXT: ucvtf s19, x8
-; CHECK-NEXT: mov x8, v3.d[1]
-; CHECK-NEXT: mov v16.s[2], v21.s[0]
-; CHECK-NEXT: ucvtf s25, x11
-; CHECK-NEXT: ldp x9, x11, [sp, #112]
-; CHECK-NEXT: mov v19.s[1], v22.s[0]
-; CHECK-NEXT: ucvtf s22, x12
-; CHECK-NEXT: ucvtf s26, x9
-; CHECK-NEXT: ldp x9, x12, [sp, #64]
-; CHECK-NEXT: ucvtf s23, x11
-; CHECK-NEXT: mov v16.s[3], v24.s[0]
-; CHECK-NEXT: fmov x11, d2
-; CHECK-NEXT: ucvtf s24, x12
-; CHECK-NEXT: ucvtf s2, x9
-; CHECK-NEXT: mov x9, v6.d[1]
-; CHECK-NEXT: ldp x12, x13, [sp, #80]
-; CHECK-NEXT: ucvtf s21, x11
-; CHECK-NEXT: mov x11, v4.d[1]
-; CHECK-NEXT: mov v19.s[2], v25.s[0]
-; CHECK-NEXT: mov v20.s[2], v26.s[0]
-; CHECK-NEXT: ushr v25.4s, v16.4s, #16
-; CHECK-NEXT: ucvtf s26, x14
-; CHECK-NEXT: ucvtf s3, x12
-; CHECK-NEXT: mov v2.s[1], v24.s[0]
-; CHECK-NEXT: ucvtf s24, x10
-; CHECK-NEXT: fmov x10, d6
-; CHECK-NEXT: fmov x12, d0
-; CHECK-NEXT: ucvtf s6, x9
-; CHECK-NEXT: mov v21.s[1], v27.s[0]
-; CHECK-NEXT: ucvtf s27, x11
-; CHECK-NEXT: fmov x11, d7
-; CHECK-NEXT: mov v19.s[3], v22.s[0]
-; CHECK-NEXT: mov v20.s[3], v23.s[0]
-; CHECK-NEXT: add v22.4s, v16.4s, v18.4s
-; CHECK-NEXT: mov v2.s[2], v3.s[0]
-; CHECK-NEXT: ucvtf s3, x10
-; CHECK-NEXT: fmov x10, d4
-; CHECK-NEXT: ucvtf s0, x12
-; CHECK-NEXT: and v23.16b, v25.16b, v17.16b
-; CHECK-NEXT: mov x9, v1.d[1]
-; CHECK-NEXT: fmov x12, d5
-; CHECK-NEXT: mov v21.s[2], v26.s[0]
-; CHECK-NEXT: ucvtf s25, x13
-; CHECK-NEXT: ucvtf s4, x10
-; CHECK-NEXT: fmov x10, d1
-; CHECK-NEXT: add v26.4s, v20.4s, v18.4s
-; CHECK-NEXT: mov v3.s[1], v6.s[0]
-; CHECK-NEXT: ucvtf s6, x11
-; CHECK-NEXT: mov x11, v5.d[1]
-; CHECK-NEXT: ucvtf s5, x8
-; CHECK-NEXT: mov v0.s[1], v24.s[0]
-; CHECK-NEXT: add v22.4s, v23.4s, v22.4s
-; CHECK-NEXT: ucvtf s1, x10
-; CHECK-NEXT: mov x10, v7.d[1]
-; CHECK-NEXT: ucvtf s7, x12
-; CHECK-NEXT: mov v4.s[1], v27.s[0]
-; CHECK-NEXT: ushr v23.4s, v19.4s, #16
-; CHECK-NEXT: mov v2.s[3], v25.s[0]
-; CHECK-NEXT: mov v3.s[2], v6.s[0]
-; CHECK-NEXT: add v25.4s, v19.4s, v18.4s
-; CHECK-NEXT: ushr v24.4s, v20.4s, #16
-; CHECK-NEXT: mov v21.s[3], v5.s[0]
-; CHECK-NEXT: ucvtf s5, x11
-; CHECK-NEXT: fcmeq v29.4s, v20.4s, v20.4s
-; CHECK-NEXT: ucvtf s6, x10
-; CHECK-NEXT: and v23.16b, v23.16b, v17.16b
-; CHECK-NEXT: mov v0.s[2], v1.s[0]
-; CHECK-NEXT: ucvtf s1, x9
-; CHECK-NEXT: mov v4.s[2], v7.s[0]
-; CHECK-NEXT: and v24.16b, v24.16b, v17.16b
-; CHECK-NEXT: fcmeq v7.4s, v16.4s, v16.4s
-; CHECK-NEXT: orr v16.4s, #64, lsl #16
-; CHECK-NEXT: fcmeq v31.4s, v2.4s, v2.4s
-; CHECK-NEXT: add v27.4s, v21.4s, v18.4s
-; CHECK-NEXT: orr v20.4s, #64, lsl #16
-; CHECK-NEXT: mov v3.s[3], v6.s[0]
-; CHECK-NEXT: add v6.4s, v23.4s, v25.4s
-; CHECK-NEXT: ushr v23.4s, v21.4s, #16
-; CHECK-NEXT: mov v0.s[3], v1.s[0]
-; CHECK-NEXT: mov v4.s[3], v5.s[0]
-; CHECK-NEXT: ushr v1.4s, v2.4s, #16
-; CHECK-NEXT: add v24.4s, v24.4s, v26.4s
-; CHECK-NEXT: add v25.4s, v2.4s, v18.4s
-; CHECK-NEXT: fcmeq v5.4s, v19.4s, v19.4s
-; CHECK-NEXT: and v23.16b, v23.16b, v17.16b
-; CHECK-NEXT: orr v19.4s, #64, lsl #16
-; CHECK-NEXT: orr v2.4s, #64, lsl #16
-; CHECK-NEXT: ushr v28.4s, v3.4s, #16
-; CHECK-NEXT: and v1.16b, v1.16b, v17.16b
-; CHECK-NEXT: bsl v7.16b, v22.16b, v16.16b
-; CHECK-NEXT: ushr v26.4s, v0.4s, #16
-; CHECK-NEXT: ushr v30.4s, v4.4s, #16
-; CHECK-NEXT: add v23.4s, v23.4s, v27.4s
-; CHECK-NEXT: bsl v5.16b, v6.16b, v19.16b
-; CHECK-NEXT: mov v6.16b, v29.16b
-; CHECK-NEXT: and v27.16b, v28.16b, v17.16b
-; CHECK-NEXT: add v28.4s, v3.4s, v18.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v25.4s
-; CHECK-NEXT: and v25.16b, v26.16b, v17.16b
-; CHECK-NEXT: add v26.4s, v0.4s, v18.4s
-; CHECK-NEXT: and v17.16b, v30.16b, v17.16b
-; CHECK-NEXT: add v18.4s, v4.4s, v18.4s
-; CHECK-NEXT: fcmeq v30.4s, v21.4s, v21.4s
-; CHECK-NEXT: orr v21.4s, #64, lsl #16
-; CHECK-NEXT: add v27.4s, v27.4s, v28.4s
-; CHECK-NEXT: fcmeq v28.4s, v3.4s, v3.4s
-; CHECK-NEXT: orr v3.4s, #64, lsl #16
-; CHECK-NEXT: add v25.4s, v25.4s, v26.4s
-; CHECK-NEXT: fcmeq v26.4s, v0.4s, v0.4s
-; CHECK-NEXT: orr v0.4s, #64, lsl #16
-; CHECK-NEXT: add v17.4s, v17.4s, v18.4s
-; CHECK-NEXT: fcmeq v18.4s, v4.4s, v4.4s
-; CHECK-NEXT: orr v4.4s, #64, lsl #16
-; CHECK-NEXT: mov v16.16b, v30.16b
-; CHECK-NEXT: bsl v6.16b, v24.16b, v20.16b
-; CHECK-NEXT: bif v1.16b, v2.16b, v31.16b
-; CHECK-NEXT: mov v19.16b, v28.16b
-; CHECK-NEXT: uzp2 v2.8h, v5.8h, v7.8h
-; CHECK-NEXT: bit v0.16b, v25.16b, v26.16b
-; CHECK-NEXT: bsl v16.16b, v23.16b, v21.16b
-; CHECK-NEXT: bit v4.16b, v17.16b, v18.16b
-; CHECK-NEXT: bsl v19.16b, v27.16b, v3.16b
-; CHECK-NEXT: uzp2 v3.8h, v1.8h, v6.8h
-; CHECK-NEXT: uzp2 v0.8h, v0.8h, v16.8h
-; CHECK-NEXT: uzp2 v1.8h, v4.8h, v19.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v32i64_v32bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldp x8, x9, [sp, #32]
+; CHECK-SD-NEXT: mov x14, v2.d[1]
+; CHECK-SD-NEXT: ldp x10, x11, [sp]
+; CHECK-SD-NEXT: ldp x12, x13, [sp, #96]
+; CHECK-SD-NEXT: ucvtf s18, x9
+; CHECK-SD-NEXT: ucvtf s16, x8
+; CHECK-SD-NEXT: ldp x8, x9, [sp, #64]
+; CHECK-SD-NEXT: ucvtf s17, x10
+; CHECK-SD-NEXT: ucvtf s19, x11
+; CHECK-SD-NEXT: ucvtf s21, x13
+; CHECK-SD-NEXT: mov x13, v4.d[1]
+; CHECK-SD-NEXT: ucvtf s20, x9
+; CHECK-SD-NEXT: ldp x10, x9, [sp, #16]
+; CHECK-SD-NEXT: mov v16.s[1], v18.s[0]
+; CHECK-SD-NEXT: ucvtf s18, x8
+; CHECK-SD-NEXT: mov v17.s[1], v19.s[0]
+; CHECK-SD-NEXT: ucvtf s19, x12
+; CHECK-SD-NEXT: mov x12, v0.d[1]
+; CHECK-SD-NEXT: ucvtf s22, x10
+; CHECK-SD-NEXT: ldp x11, x10, [sp, #80]
+; CHECK-SD-NEXT: ldp x15, x8, [sp, #48]
+; CHECK-SD-NEXT: mov v18.s[1], v20.s[0]
+; CHECK-SD-NEXT: ucvtf s23, x11
+; CHECK-SD-NEXT: fmov x11, d2
+; CHECK-SD-NEXT: mov v19.s[1], v21.s[0]
+; CHECK-SD-NEXT: mov v17.s[2], v22.s[0]
+; CHECK-SD-NEXT: ucvtf s22, x14
+; CHECK-SD-NEXT: fmov x14, d1
+; CHECK-SD-NEXT: ucvtf s2, x15
+; CHECK-SD-NEXT: ucvtf s20, x11
+; CHECK-SD-NEXT: fmov x11, d0
+; CHECK-SD-NEXT: ucvtf s0, x12
+; CHECK-SD-NEXT: fmov x12, d4
+; CHECK-SD-NEXT: mov v18.s[2], v23.s[0]
+; CHECK-SD-NEXT: ucvtf s23, x9
+; CHECK-SD-NEXT: mov x9, v6.d[1]
+; CHECK-SD-NEXT: ucvtf s21, x11
+; CHECK-SD-NEXT: mov x11, v1.d[1]
+; CHECK-SD-NEXT: ucvtf s1, x13
+; CHECK-SD-NEXT: ucvtf s4, x12
+; CHECK-SD-NEXT: fmov x12, d6
+; CHECK-SD-NEXT: mov v20.s[1], v22.s[0]
+; CHECK-SD-NEXT: mov x13, v5.d[1]
+; CHECK-SD-NEXT: mov v16.s[2], v2.s[0]
+; CHECK-SD-NEXT: mov v17.s[3], v23.s[0]
+; CHECK-SD-NEXT: ucvtf s6, x9
+; CHECK-SD-NEXT: ucvtf s2, x8
+; CHECK-SD-NEXT: mov v21.s[1], v0.s[0]
+; CHECK-SD-NEXT: ucvtf s0, x14
+; CHECK-SD-NEXT: ucvtf s22, x12
+; CHECK-SD-NEXT: fmov x14, d5
+; CHECK-SD-NEXT: mov v4.s[1], v1.s[0]
+; CHECK-SD-NEXT: ldp x9, x12, [sp, #112]
+; CHECK-SD-NEXT: mov v16.s[3], v2.s[0]
+; CHECK-SD-NEXT: bfcvtn v2.4h, v17.4s
+; CHECK-SD-NEXT: ucvtf s1, x14
+; CHECK-SD-NEXT: fmov x14, d3
+; CHECK-SD-NEXT: mov v22.s[1], v6.s[0]
+; CHECK-SD-NEXT: ucvtf s6, x11
+; CHECK-SD-NEXT: fmov x11, d7
+; CHECK-SD-NEXT: ucvtf s5, x9
+; CHECK-SD-NEXT: mov x9, v3.d[1]
+; CHECK-SD-NEXT: ucvtf s3, x10
+; CHECK-SD-NEXT: mov v21.s[2], v0.s[0]
+; CHECK-SD-NEXT: ucvtf s0, x14
+; CHECK-SD-NEXT: mov x10, v7.d[1]
+; CHECK-SD-NEXT: bfcvtn2 v2.8h, v16.4s
+; CHECK-SD-NEXT: ucvtf s7, x11
+; CHECK-SD-NEXT: mov v4.s[2], v1.s[0]
+; CHECK-SD-NEXT: ucvtf s1, x13
+; CHECK-SD-NEXT: mov v19.s[2], v5.s[0]
+; CHECK-SD-NEXT: mov v18.s[3], v3.s[0]
+; CHECK-SD-NEXT: mov v21.s[3], v6.s[0]
+; CHECK-SD-NEXT: ucvtf s3, x9
+; CHECK-SD-NEXT: mov v20.s[2], v0.s[0]
+; CHECK-SD-NEXT: ucvtf s0, x12
+; CHECK-SD-NEXT: mov v22.s[2], v7.s[0]
+; CHECK-SD-NEXT: mov v4.s[3], v1.s[0]
+; CHECK-SD-NEXT: ucvtf s1, x10
+; CHECK-SD-NEXT: mov v19.s[3], v0.s[0]
+; CHECK-SD-NEXT: mov v20.s[3], v3.s[0]
+; CHECK-SD-NEXT: bfcvtn v0.4h, v21.4s
+; CHECK-SD-NEXT: bfcvtn v3.4h, v18.4s
+; CHECK-SD-NEXT: mov v22.s[3], v1.s[0]
+; CHECK-SD-NEXT: bfcvtn v1.4h, v4.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v20.4s
+; CHECK-SD-NEXT: bfcvtn2 v3.8h, v19.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v22.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v32i64_v32bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d10, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset b8, -8
+; CHECK-GI-NEXT: .cfi_offset b9, -16
+; CHECK-GI-NEXT: .cfi_offset b10, -32
+; CHECK-GI-NEXT: mov x9, v1.d[1]
+; CHECK-GI-NEXT: fmov x10, d0
+; CHECK-GI-NEXT: mov x11, v2.d[1]
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: ldp q26, q23, [sp, #32]
+; CHECK-GI-NEXT: fmov x12, d4
+; CHECK-GI-NEXT: mov x13, v6.d[1]
+; CHECK-GI-NEXT: ucvtf s0, x10
+; CHECK-GI-NEXT: fmov x10, d1
+; CHECK-GI-NEXT: ucvtf s1, x9
+; CHECK-GI-NEXT: mov x9, v4.d[1]
+; CHECK-GI-NEXT: ucvtf s20, x11
+; CHECK-GI-NEXT: fmov x11, d3
+; CHECK-GI-NEXT: ldp q30, q27, [sp, #96]
+; CHECK-GI-NEXT: ucvtf s18, x10
+; CHECK-GI-NEXT: mov x10, v5.d[1]
+; CHECK-GI-NEXT: ucvtf s28, x8
+; CHECK-GI-NEXT: fmov x8, d2
+; CHECK-GI-NEXT: ldp q24, q22, [sp, #64]
+; CHECK-GI-NEXT: ucvtf s19, x11
+; CHECK-GI-NEXT: fmov x11, d5
+; CHECK-GI-NEXT: ucvtf s2, x12
+; CHECK-GI-NEXT: ucvtf s8, x9
+; CHECK-GI-NEXT: ldp q31, q17, [sp, #128]
+; CHECK-GI-NEXT: fmov x9, d6
+; CHECK-GI-NEXT: fmov x12, d7
+; CHECK-GI-NEXT: ucvtf s16, x8
+; CHECK-GI-NEXT: mov x8, v3.d[1]
+; CHECK-GI-NEXT: ucvtf s21, x11
+; CHECK-GI-NEXT: ucvtf s3, x10
+; CHECK-GI-NEXT: mov x10, v26.d[1]
+; CHECK-GI-NEXT: mov x11, v23.d[1]
+; CHECK-GI-NEXT: ucvtf s25, x13
+; CHECK-GI-NEXT: ucvtf s4, x9
+; CHECK-GI-NEXT: mov x9, v7.d[1]
+; CHECK-GI-NEXT: fmov x13, d26
+; CHECK-GI-NEXT: ucvtf s7, x12
+; CHECK-GI-NEXT: mov x12, v30.d[1]
+; CHECK-GI-NEXT: mov x14, v24.d[1]
+; CHECK-GI-NEXT: mov v0.s[1], v28.s[0]
+; CHECK-GI-NEXT: mov v2.s[1], v8.s[0]
+; CHECK-GI-NEXT: mov v16.s[1], v20.s[0]
+; CHECK-GI-NEXT: ucvtf s5, x13
+; CHECK-GI-NEXT: ucvtf s10, x10
+; CHECK-GI-NEXT: fmov x10, d23
+; CHECK-GI-NEXT: fmov x13, d24
+; CHECK-GI-NEXT: ucvtf s23, x11
+; CHECK-GI-NEXT: fmov x11, d30
+; CHECK-GI-NEXT: ucvtf s9, x12
+; CHECK-GI-NEXT: fmov x12, d22
+; CHECK-GI-NEXT: ucvtf s29, x14
+; CHECK-GI-NEXT: fmov x14, d27
+; CHECK-GI-NEXT: ucvtf s26, x10
+; CHECK-GI-NEXT: mov x10, v22.d[1]
+; CHECK-GI-NEXT: ucvtf s6, x13
+; CHECK-GI-NEXT: mov x13, v31.d[1]
+; CHECK-GI-NEXT: ucvtf s24, x11
+; CHECK-GI-NEXT: mov x11, v27.d[1]
+; CHECK-GI-NEXT: ucvtf s27, x12
+; CHECK-GI-NEXT: fmov x12, d31
+; CHECK-GI-NEXT: ucvtf s30, x14
+; CHECK-GI-NEXT: mov v5.s[1], v10.s[0]
+; CHECK-GI-NEXT: mov v4.s[1], v25.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v18.s[0]
+; CHECK-GI-NEXT: mov v2.s[2], v21.s[0]
+; CHECK-GI-NEXT: ucvtf s18, x8
+; CHECK-GI-NEXT: ucvtf s22, x12
+; CHECK-GI-NEXT: ucvtf s31, x13
+; CHECK-GI-NEXT: mov v24.s[1], v9.s[0]
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: fmov x12, d17
+; CHECK-GI-NEXT: ucvtf s28, x11
+; CHECK-GI-NEXT: mov x11, v17.d[1]
+; CHECK-GI-NEXT: mov v6.s[1], v29.s[0]
+; CHECK-GI-NEXT: mov v5.s[2], v26.s[0]
+; CHECK-GI-NEXT: ucvtf s20, x9
+; CHECK-GI-NEXT: ucvtf s21, x10
+; CHECK-GI-NEXT: ucvtf s17, x12
+; CHECK-GI-NEXT: mov v22.s[1], v31.s[0]
+; CHECK-GI-NEXT: mov v24.s[2], v30.s[0]
+; CHECK-GI-NEXT: mov v16.s[2], v19.s[0]
+; CHECK-GI-NEXT: mov v4.s[2], v7.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-GI-NEXT: ucvtf s25, x11
+; CHECK-GI-NEXT: mov v6.s[2], v27.s[0]
+; CHECK-GI-NEXT: mov v2.s[3], v3.s[0]
+; CHECK-GI-NEXT: mov v5.s[3], v23.s[0]
+; CHECK-GI-NEXT: mov v22.s[2], v17.s[0]
+; CHECK-GI-NEXT: mov v24.s[3], v28.s[0]
+; CHECK-GI-NEXT: mov v16.s[3], v18.s[0]
+; CHECK-GI-NEXT: mov v4.s[3], v20.s[0]
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: mov v6.s[3], v21.s[0]
+; CHECK-GI-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn v2.4h, v5.4s
+; CHECK-GI-NEXT: mov v22.s[3], v25.s[0]
+; CHECK-GI-NEXT: bfcvtn v3.4h, v24.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v16.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v2.8h, v6.4s
+; CHECK-GI-NEXT: bfcvtn2 v3.8h, v22.4s
+; CHECK-GI-NEXT: ldr d10, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <32 x i64> %a to <32 x bfloat>
ret <32 x bfloat> %c
}
define <2 x bfloat> @stofp_v2i32_v2bf16(<2 x i32> %a) {
-; CHECK-LABEL: stofp_v2i32_v2bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v2i32_v2bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v2i32_v2bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: scvtf v0.2s, v0.2s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <2 x i32> %a to <2 x bfloat>
ret <2 x bfloat> %c
}
define <2 x bfloat> @utofp_v2i32_v2bf16(<2 x i32> %a) {
-; CHECK-LABEL: utofp_v2i32_v2bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v2i32_v2bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v2i32_v2bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ucvtf v0.2s, v0.2s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <2 x i32> %a to <2 x bfloat>
ret <2 x bfloat> %c
@@ -1083,12 +1202,7 @@ define <3 x bfloat> @stofp_v3i32_v3bf16(<3 x i32> %a) {
; CHECK-LABEL: stofp_v3i32_v3bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%c = sitofp <3 x i32> %a to <3 x bfloat>
@@ -1099,12 +1213,7 @@ define <3 x bfloat> @utofp_v3i32_v3bf16(<3 x i32> %a) {
; CHECK-LABEL: utofp_v3i32_v3bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%c = uitofp <3 x i32> %a to <3 x bfloat>
@@ -1115,12 +1224,7 @@ define <4 x bfloat> @stofp_v4i32_v4bf16(<4 x i32> %a) {
; CHECK-LABEL: stofp_v4i32_v4bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%c = sitofp <4 x i32> %a to <4 x bfloat>
@@ -1131,12 +1235,7 @@ define <4 x bfloat> @utofp_v4i32_v4bf16(<4 x i32> %a) {
; CHECK-LABEL: utofp_v4i32_v4bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%c = uitofp <4 x i32> %a to <4 x bfloat>
@@ -1147,17 +1246,9 @@ define <8 x bfloat> @stofp_v8i32_v8bf16(<8 x i32> %a) {
; CHECK-LABEL: stofp_v8i32_v8bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: scvtf v1.4s, v1.4s
-; CHECK-NEXT: movi v5.4s, #127, msl #8
-; CHECK-NEXT: ushr v3.4s, v0.4s, #16
-; CHECK-NEXT: ushr v4.4s, v1.4s, #16
-; CHECK-NEXT: and v3.16b, v3.16b, v2.16b
-; CHECK-NEXT: and v2.16b, v4.16b, v2.16b
-; CHECK-NEXT: add v0.4s, v3.4s, v0.4s
-; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v5.4s
-; CHECK-NEXT: addhn2 v0.8h, v1.4s, v5.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-NEXT: bfcvtn2 v0.8h, v1.4s
; CHECK-NEXT: ret
entry:
%c = sitofp <8 x i32> %a to <8 x bfloat>
@@ -1168,17 +1259,9 @@ define <8 x bfloat> @utofp_v8i32_v8bf16(<8 x i32> %a) {
; CHECK-LABEL: utofp_v8i32_v8bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: movi v2.4s, #1
; CHECK-NEXT: ucvtf v1.4s, v1.4s
-; CHECK-NEXT: movi v5.4s, #127, msl #8
-; CHECK-NEXT: ushr v3.4s, v0.4s, #16
-; CHECK-NEXT: ushr v4.4s, v1.4s, #16
-; CHECK-NEXT: and v3.16b, v3.16b, v2.16b
-; CHECK-NEXT: and v2.16b, v4.16b, v2.16b
-; CHECK-NEXT: add v0.4s, v3.4s, v0.4s
-; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v5.4s
-; CHECK-NEXT: addhn2 v0.8h, v1.4s, v5.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-NEXT: bfcvtn2 v0.8h, v1.4s
; CHECK-NEXT: ret
entry:
%c = uitofp <8 x i32> %a to <8 x bfloat>
@@ -1186,62 +1269,58 @@ entry:
}
define <16 x bfloat> @stofp_v16i32_v16bf16(<16 x i32> %a) {
-; CHECK-LABEL: stofp_v16i32_v16bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: scvtf v2.4s, v2.4s
-; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: scvtf v4.4s, v1.4s
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: scvtf v3.4s, v3.4s
-; CHECK-NEXT: movi v17.4s, #127, msl #8
-; CHECK-NEXT: ushr v5.4s, v0.4s, #16
-; CHECK-NEXT: ushr v6.4s, v2.4s, #16
-; CHECK-NEXT: ushr v7.4s, v4.4s, #16
-; CHECK-NEXT: ushr v16.4s, v3.4s, #16
-; CHECK-NEXT: and v5.16b, v5.16b, v1.16b
-; CHECK-NEXT: and v6.16b, v6.16b, v1.16b
-; CHECK-NEXT: add v0.4s, v5.4s, v0.4s
-; CHECK-NEXT: add v2.4s, v6.4s, v2.4s
-; CHECK-NEXT: and v5.16b, v7.16b, v1.16b
-; CHECK-NEXT: and v6.16b, v16.16b, v1.16b
-; CHECK-NEXT: addhn v0.4h, v0.4s, v17.4s
-; CHECK-NEXT: addhn v1.4h, v2.4s, v17.4s
-; CHECK-NEXT: add v2.4s, v5.4s, v4.4s
-; CHECK-NEXT: add v3.4s, v6.4s, v3.4s
-; CHECK-NEXT: addhn2 v0.8h, v2.4s, v17.4s
-; CHECK-NEXT: addhn2 v1.8h, v3.4s, v17.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v16i32_v16bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: scvtf v2.4s, v2.4s
+; CHECK-SD-NEXT: scvtf v4.4s, v1.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-SD-NEXT: scvtf v2.4s, v3.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v16i32_v16bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: scvtf v2.4s, v2.4s
+; CHECK-GI-NEXT: scvtf v4.4s, v1.4s
+; CHECK-GI-NEXT: scvtf v3.4s, v3.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v3.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <16 x i32> %a to <16 x bfloat>
ret <16 x bfloat> %c
}
define <16 x bfloat> @utofp_v16i32_v16bf16(<16 x i32> %a) {
-; CHECK-LABEL: utofp_v16i32_v16bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ucvtf v2.4s, v2.4s
-; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: ucvtf v4.4s, v1.4s
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ucvtf v3.4s, v3.4s
-; CHECK-NEXT: movi v17.4s, #127, msl #8
-; CHECK-NEXT: ushr v5.4s, v0.4s, #16
-; CHECK-NEXT: ushr v6.4s, v2.4s, #16
-; CHECK-NEXT: ushr v7.4s, v4.4s, #16
-; CHECK-NEXT: ushr v16.4s, v3.4s, #16
-; CHECK-NEXT: and v5.16b, v5.16b, v1.16b
-; CHECK-NEXT: and v6.16b, v6.16b, v1.16b
-; CHECK-NEXT: add v0.4s, v5.4s, v0.4s
-; CHECK-NEXT: add v2.4s, v6.4s, v2.4s
-; CHECK-NEXT: and v5.16b, v7.16b, v1.16b
-; CHECK-NEXT: and v6.16b, v16.16b, v1.16b
-; CHECK-NEXT: addhn v0.4h, v0.4s, v17.4s
-; CHECK-NEXT: addhn v1.4h, v2.4s, v17.4s
-; CHECK-NEXT: add v2.4s, v5.4s, v4.4s
-; CHECK-NEXT: add v3.4s, v6.4s, v3.4s
-; CHECK-NEXT: addhn2 v0.8h, v2.4s, v17.4s
-; CHECK-NEXT: addhn2 v1.8h, v3.4s, v17.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v16i32_v16bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: ucvtf v2.4s, v2.4s
+; CHECK-SD-NEXT: ucvtf v4.4s, v1.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-SD-NEXT: ucvtf v2.4s, v3.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v2.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v16i32_v16bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: ucvtf v2.4s, v2.4s
+; CHECK-GI-NEXT: ucvtf v4.4s, v1.4s
+; CHECK-GI-NEXT: ucvtf v3.4s, v3.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v3.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <16 x i32> %a to <16 x bfloat>
ret <16 x bfloat> %c
@@ -1254,44 +1333,18 @@ define <32 x bfloat> @stofp_v32i32_v32bf16(<32 x i32> %a) {
; CHECK-NEXT: scvtf v2.4s, v2.4s
; CHECK-NEXT: scvtf v4.4s, v4.4s
; CHECK-NEXT: scvtf v6.4s, v6.4s
-; CHECK-NEXT: movi v16.4s, #1
-; CHECK-NEXT: scvtf v1.4s, v1.4s
+; CHECK-NEXT: scvtf v16.4s, v1.4s
; CHECK-NEXT: scvtf v17.4s, v3.4s
; CHECK-NEXT: scvtf v5.4s, v5.4s
; CHECK-NEXT: scvtf v7.4s, v7.4s
-; CHECK-NEXT: movi v21.4s, #127, msl #8
-; CHECK-NEXT: ushr v3.4s, v0.4s, #16
-; CHECK-NEXT: ushr v18.4s, v2.4s, #16
-; CHECK-NEXT: ushr v19.4s, v4.4s, #16
-; CHECK-NEXT: ushr v20.4s, v6.4s, #16
-; CHECK-NEXT: ushr v22.4s, v1.4s, #16
-; CHECK-NEXT: ushr v23.4s, v17.4s, #16
-; CHECK-NEXT: ushr v24.4s, v5.4s, #16
-; CHECK-NEXT: ushr v25.4s, v7.4s, #16
-; CHECK-NEXT: and v3.16b, v3.16b, v16.16b
-; CHECK-NEXT: and v18.16b, v18.16b, v16.16b
-; CHECK-NEXT: and v19.16b, v19.16b, v16.16b
-; CHECK-NEXT: and v20.16b, v20.16b, v16.16b
-; CHECK-NEXT: add v0.4s, v3.4s, v0.4s
-; CHECK-NEXT: and v3.16b, v22.16b, v16.16b
-; CHECK-NEXT: add v2.4s, v18.4s, v2.4s
-; CHECK-NEXT: add v4.4s, v19.4s, v4.4s
-; CHECK-NEXT: add v6.4s, v20.4s, v6.4s
-; CHECK-NEXT: and v18.16b, v23.16b, v16.16b
-; CHECK-NEXT: and v19.16b, v24.16b, v16.16b
-; CHECK-NEXT: and v16.16b, v25.16b, v16.16b
-; CHECK-NEXT: add v20.4s, v3.4s, v1.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v21.4s
-; CHECK-NEXT: addhn v1.4h, v2.4s, v21.4s
-; CHECK-NEXT: addhn v2.4h, v4.4s, v21.4s
-; CHECK-NEXT: addhn v3.4h, v6.4s, v21.4s
-; CHECK-NEXT: add v4.4s, v18.4s, v17.4s
-; CHECK-NEXT: add v5.4s, v19.4s, v5.4s
-; CHECK-NEXT: add v6.4s, v16.4s, v7.4s
-; CHECK-NEXT: addhn2 v0.8h, v20.4s, v21.4s
-; CHECK-NEXT: addhn2 v1.8h, v4.4s, v21.4s
-; CHECK-NEXT: addhn2 v2.8h, v5.4s, v21.4s
-; CHECK-NEXT: addhn2 v3.8h, v6.4s, v21.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-NEXT: bfcvtn v2.4h, v4.4s
+; CHECK-NEXT: bfcvtn v3.4h, v6.4s
+; CHECK-NEXT: bfcvtn2 v0.8h, v16.4s
+; CHECK-NEXT: bfcvtn2 v1.8h, v17.4s
+; CHECK-NEXT: bfcvtn2 v2.8h, v5.4s
+; CHECK-NEXT: bfcvtn2 v3.8h, v7.4s
; CHECK-NEXT: ret
entry:
%c = sitofp <32 x i32> %a to <32 x bfloat>
@@ -1305,44 +1358,18 @@ define <32 x bfloat> @utofp_v32i32_v32bf16(<32 x i32> %a) {
; CHECK-NEXT: ucvtf v2.4s, v2.4s
; CHECK-NEXT: ucvtf v4.4s, v4.4s
; CHECK-NEXT: ucvtf v6.4s, v6.4s
-; CHECK-NEXT: movi v16.4s, #1
-; CHECK-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-NEXT: ucvtf v16.4s, v1.4s
; CHECK-NEXT: ucvtf v17.4s, v3.4s
; CHECK-NEXT: ucvtf v5.4s, v5.4s
; CHECK-NEXT: ucvtf v7.4s, v7.4s
-; CHECK-NEXT: movi v21.4s, #127, msl #8
-; CHECK-NEXT: ushr v3.4s, v0.4s, #16
-; CHECK-NEXT: ushr v18.4s, v2.4s, #16
-; CHECK-NEXT: ushr v19.4s, v4.4s, #16
-; CHECK-NEXT: ushr v20.4s, v6.4s, #16
-; CHECK-NEXT: ushr v22.4s, v1.4s, #16
-; CHECK-NEXT: ushr v23.4s, v17.4s, #16
-; CHECK-NEXT: ushr v24.4s, v5.4s, #16
-; CHECK-NEXT: ushr v25.4s, v7.4s, #16
-; CHECK-NEXT: and v3.16b, v3.16b, v16.16b
-; CHECK-NEXT: and v18.16b, v18.16b, v16.16b
-; CHECK-NEXT: and v19.16b, v19.16b, v16.16b
-; CHECK-NEXT: and v20.16b, v20.16b, v16.16b
-; CHECK-NEXT: add v0.4s, v3.4s, v0.4s
-; CHECK-NEXT: and v3.16b, v22.16b, v16.16b
-; CHECK-NEXT: add v2.4s, v18.4s, v2.4s
-; CHECK-NEXT: add v4.4s, v19.4s, v4.4s
-; CHECK-NEXT: add v6.4s, v20.4s, v6.4s
-; CHECK-NEXT: and v18.16b, v23.16b, v16.16b
-; CHECK-NEXT: and v19.16b, v24.16b, v16.16b
-; CHECK-NEXT: and v16.16b, v25.16b, v16.16b
-; CHECK-NEXT: add v20.4s, v3.4s, v1.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v21.4s
-; CHECK-NEXT: addhn v1.4h, v2.4s, v21.4s
-; CHECK-NEXT: addhn v2.4h, v4.4s, v21.4s
-; CHECK-NEXT: addhn v3.4h, v6.4s, v21.4s
-; CHECK-NEXT: add v4.4s, v18.4s, v17.4s
-; CHECK-NEXT: add v5.4s, v19.4s, v5.4s
-; CHECK-NEXT: add v6.4s, v16.4s, v7.4s
-; CHECK-NEXT: addhn2 v0.8h, v20.4s, v21.4s
-; CHECK-NEXT: addhn2 v1.8h, v4.4s, v21.4s
-; CHECK-NEXT: addhn2 v2.8h, v5.4s, v21.4s
-; CHECK-NEXT: addhn2 v3.8h, v6.4s, v21.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-NEXT: bfcvtn v2.4h, v4.4s
+; CHECK-NEXT: bfcvtn v3.4h, v6.4s
+; CHECK-NEXT: bfcvtn2 v0.8h, v16.4s
+; CHECK-NEXT: bfcvtn2 v1.8h, v17.4s
+; CHECK-NEXT: bfcvtn2 v2.8h, v5.4s
+; CHECK-NEXT: bfcvtn2 v3.8h, v7.4s
; CHECK-NEXT: ret
entry:
%c = uitofp <32 x i32> %a to <32 x bfloat>
@@ -1350,36 +1377,42 @@ entry:
}
define <2 x bfloat> @stofp_v2i16_v2bf16(<2 x i16> %a) {
-; CHECK-LABEL: stofp_v2i16_v2bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v2i16_v2bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v2i16_v2bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
+; CHECK-GI-NEXT: scvtf v0.2s, v0.2s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <2 x i16> %a to <2 x bfloat>
ret <2 x bfloat> %c
}
define <2 x bfloat> @utofp_v2i16_v2bf16(<2 x i16> %a) {
-; CHECK-LABEL: utofp_v2i16_v2bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v2i16_v2bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v2i16_v2bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ucvtf v0.2s, v0.2s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <2 x i16> %a to <2 x bfloat>
ret <2 x bfloat> %c
@@ -1389,13 +1422,8 @@ define <3 x bfloat> @stofp_v3i16_v3bf16(<3 x i16> %a) {
; CHECK-LABEL: stofp_v3i16_v3bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%c = sitofp <3 x i16> %a to <3 x bfloat>
@@ -1406,13 +1434,8 @@ define <3 x bfloat> @utofp_v3i16_v3bf16(<3 x i16> %a) {
; CHECK-LABEL: utofp_v3i16_v3bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%c = uitofp <3 x i16> %a to <3 x bfloat>
@@ -1423,13 +1446,8 @@ define <4 x bfloat> @stofp_v4i16_v4bf16(<4 x i16> %a) {
; CHECK-LABEL: stofp_v4i16_v4bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%c = sitofp <4 x i16> %a to <4 x bfloat>
@@ -1440,13 +1458,8 @@ define <4 x bfloat> @utofp_v4i16_v4bf16(<4 x i16> %a) {
; CHECK-LABEL: utofp_v4i16_v4bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
+; CHECK-NEXT: bfcvtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%c = uitofp <4 x i16> %a to <4 x bfloat>
@@ -1454,116 +1467,124 @@ entry:
}
define <8 x bfloat> @stofp_v8i16_v8bf16(<8 x i16> %a) {
-; CHECK-LABEL: stofp_v8i16_v8bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sshll v2.4s, v0.4h, #0
-; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: movi v4.4s, #127, msl #8
-; CHECK-NEXT: scvtf v2.4s, v2.4s
-; CHECK-NEXT: scvtf v3.4s, v0.4s
-; CHECK-NEXT: ushr v0.4s, v2.4s, #16
-; CHECK-NEXT: ushr v5.4s, v3.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v1.16b, v5.16b, v1.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v4.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: addhn v0.4h, v2.4s, v0.4s
-; CHECK-NEXT: addhn2 v0.8h, v3.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v8i16_v8bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: scvtf v1.4s, v1.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v1.4s
+; CHECK-SD-NEXT: scvtf v1.4s, v2.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v8i16_v8bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: scvtf v1.4s, v1.4s
+; CHECK-GI-NEXT: scvtf v2.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v1.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <8 x i16> %a to <8 x bfloat>
ret <8 x bfloat> %c
}
define <8 x bfloat> @utofp_v8i16_v8bf16(<8 x i16> %a) {
-; CHECK-LABEL: utofp_v8i16_v8bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ushll v2.4s, v0.4h, #0
-; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: movi v4.4s, #127, msl #8
-; CHECK-NEXT: ucvtf v2.4s, v2.4s
-; CHECK-NEXT: ucvtf v3.4s, v0.4s
-; CHECK-NEXT: ushr v0.4s, v2.4s, #16
-; CHECK-NEXT: ushr v5.4s, v3.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v1.16b, v5.16b, v1.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v4.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: addhn v0.4h, v2.4s, v0.4s
-; CHECK-NEXT: addhn2 v0.8h, v3.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v8i16_v8bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v1.4s
+; CHECK-SD-NEXT: ucvtf v1.4s, v2.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v8i16_v8bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-GI-NEXT: ucvtf v2.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v1.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <8 x i16> %a to <8 x bfloat>
ret <8 x bfloat> %c
}
define <16 x bfloat> @stofp_v16i16_v16bf16(<16 x i16> %a) {
-; CHECK-LABEL: stofp_v16i16_v16bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sshll v3.4s, v0.4h, #0
-; CHECK-NEXT: sshll v4.4s, v1.4h, #0
-; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: sshll2 v1.4s, v1.8h, #0
-; CHECK-NEXT: movi v2.4s, #1
-; CHECK-NEXT: movi v7.4s, #127, msl #8
-; CHECK-NEXT: scvtf v3.4s, v3.4s
-; CHECK-NEXT: scvtf v4.4s, v4.4s
-; CHECK-NEXT: scvtf v5.4s, v0.4s
-; CHECK-NEXT: scvtf v6.4s, v1.4s
-; CHECK-NEXT: ushr v0.4s, v3.4s, #16
-; CHECK-NEXT: ushr v1.4s, v4.4s, #16
-; CHECK-NEXT: ushr v16.4s, v5.4s, #16
-; CHECK-NEXT: ushr v17.4s, v6.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: and v16.16b, v16.16b, v2.16b
-; CHECK-NEXT: and v2.16b, v17.16b, v2.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v7.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v7.4s
-; CHECK-NEXT: add v2.4s, v2.4s, v7.4s
-; CHECK-NEXT: addhn v0.4h, v3.4s, v0.4s
-; CHECK-NEXT: addhn v1.4h, v4.4s, v1.4s
-; CHECK-NEXT: add v3.4s, v16.4s, v7.4s
-; CHECK-NEXT: addhn2 v0.8h, v5.4s, v3.4s
-; CHECK-NEXT: addhn2 v1.8h, v6.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v16i16_v16bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll v3.4s, v1.4h, #0
+; CHECK-SD-NEXT: sshll2 v4.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll2 v5.4s, v1.8h, #0
+; CHECK-SD-NEXT: scvtf v2.4s, v2.4s
+; CHECK-SD-NEXT: scvtf v3.4s, v3.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v2.4s
+; CHECK-SD-NEXT: scvtf v2.4s, v4.4s
+; CHECK-SD-NEXT: bfcvtn v1.4h, v3.4s
+; CHECK-SD-NEXT: scvtf v3.4s, v5.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v2.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v3.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v16i16_v16bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v1.4s, v1.8h, #0
+; CHECK-GI-NEXT: scvtf v2.4s, v2.4s
+; CHECK-GI-NEXT: scvtf v3.4s, v3.4s
+; CHECK-GI-NEXT: scvtf v4.4s, v0.4s
+; CHECK-GI-NEXT: scvtf v5.4s, v1.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn v1.4h, v3.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <16 x i16> %a to <16 x bfloat>
ret <16 x bfloat> %c
}
define <16 x bfloat> @utofp_v16i16_v16bf16(<16 x i16> %a) {
-; CHECK-LABEL: utofp_v16i16_v16bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ushll v3.4s, v0.4h, #0
-; CHECK-NEXT: ushll v4.4s, v1.4h, #0
-; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0
-; CHECK-NEXT: movi v2.4s, #1
-; CHECK-NEXT: movi v7.4s, #127, msl #8
-; CHECK-NEXT: ucvtf v3.4s, v3.4s
-; CHECK-NEXT: ucvtf v4.4s, v4.4s
-; CHECK-NEXT: ucvtf v5.4s, v0.4s
-; CHECK-NEXT: ucvtf v6.4s, v1.4s
-; CHECK-NEXT: ushr v0.4s, v3.4s, #16
-; CHECK-NEXT: ushr v1.4s, v4.4s, #16
-; CHECK-NEXT: ushr v16.4s, v5.4s, #16
-; CHECK-NEXT: ushr v17.4s, v6.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: and v16.16b, v16.16b, v2.16b
-; CHECK-NEXT: and v2.16b, v17.16b, v2.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v7.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v7.4s
-; CHECK-NEXT: add v2.4s, v2.4s, v7.4s
-; CHECK-NEXT: addhn v0.4h, v3.4s, v0.4s
-; CHECK-NEXT: addhn v1.4h, v4.4s, v1.4s
-; CHECK-NEXT: add v3.4s, v16.4s, v7.4s
-; CHECK-NEXT: addhn2 v0.8h, v5.4s, v3.4s
-; CHECK-NEXT: addhn2 v1.8h, v6.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v16i16_v16bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll v3.4s, v1.4h, #0
+; CHECK-SD-NEXT: ushll2 v4.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll2 v5.4s, v1.8h, #0
+; CHECK-SD-NEXT: ucvtf v2.4s, v2.4s
+; CHECK-SD-NEXT: ucvtf v3.4s, v3.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v2.4s
+; CHECK-SD-NEXT: ucvtf v2.4s, v4.4s
+; CHECK-SD-NEXT: bfcvtn v1.4h, v3.4s
+; CHECK-SD-NEXT: ucvtf v3.4s, v5.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v2.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v3.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v16i16_v16bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
+; CHECK-GI-NEXT: ucvtf v2.4s, v2.4s
+; CHECK-GI-NEXT: ucvtf v3.4s, v3.4s
+; CHECK-GI-NEXT: ucvtf v4.4s, v0.4s
+; CHECK-GI-NEXT: ucvtf v5.4s, v1.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn v1.4h, v3.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <16 x i16> %a to <16 x bfloat>
ret <16 x bfloat> %c
@@ -1572,56 +1593,30 @@ entry:
define <32 x bfloat> @stofp_v32i16_v32bf16(<32 x i16> %a) {
; CHECK-LABEL: stofp_v32i16_v32bf16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sshll v4.4s, v1.4h, #0
-; CHECK-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-NEXT: sshll v4.4s, v0.4h, #0
+; CHECK-NEXT: sshll v5.4s, v1.4h, #0
; CHECK-NEXT: sshll v6.4s, v2.4h, #0
; CHECK-NEXT: sshll v7.4s, v3.4h, #0
; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
; CHECK-NEXT: sshll2 v1.4s, v1.8h, #0
; CHECK-NEXT: sshll2 v2.4s, v2.8h, #0
; CHECK-NEXT: sshll2 v3.4s, v3.8h, #0
-; CHECK-NEXT: movi v16.4s, #1
-; CHECK-NEXT: scvtf v5.4s, v5.4s
; CHECK-NEXT: scvtf v4.4s, v4.4s
+; CHECK-NEXT: scvtf v5.4s, v5.4s
; CHECK-NEXT: scvtf v6.4s, v6.4s
; CHECK-NEXT: scvtf v7.4s, v7.4s
-; CHECK-NEXT: scvtf v17.4s, v0.4s
-; CHECK-NEXT: scvtf v18.4s, v1.4s
-; CHECK-NEXT: scvtf v19.4s, v2.4s
-; CHECK-NEXT: scvtf v20.4s, v3.4s
-; CHECK-NEXT: movi v21.4s, #127, msl #8
-; CHECK-NEXT: ushr v0.4s, v5.4s, #16
-; CHECK-NEXT: ushr v1.4s, v4.4s, #16
-; CHECK-NEXT: ushr v2.4s, v6.4s, #16
-; CHECK-NEXT: ushr v3.4s, v7.4s, #16
-; CHECK-NEXT: ushr v22.4s, v17.4s, #16
-; CHECK-NEXT: ushr v23.4s, v18.4s, #16
-; CHECK-NEXT: ushr v24.4s, v19.4s, #16
-; CHECK-NEXT: ushr v25.4s, v20.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v16.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v16.16b
-; CHECK-NEXT: and v2.16b, v2.16b, v16.16b
-; CHECK-NEXT: and v3.16b, v3.16b, v16.16b
-; CHECK-NEXT: and v22.16b, v22.16b, v16.16b
-; CHECK-NEXT: and v23.16b, v23.16b, v16.16b
-; CHECK-NEXT: and v24.16b, v24.16b, v16.16b
-; CHECK-NEXT: and v16.16b, v25.16b, v16.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v21.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v21.4s
-; CHECK-NEXT: add v2.4s, v2.4s, v21.4s
-; CHECK-NEXT: add v3.4s, v3.4s, v21.4s
-; CHECK-NEXT: addhn v0.4h, v5.4s, v0.4s
-; CHECK-NEXT: addhn v1.4h, v4.4s, v1.4s
-; CHECK-NEXT: addhn v2.4h, v6.4s, v2.4s
-; CHECK-NEXT: addhn v3.4h, v7.4s, v3.4s
-; CHECK-NEXT: add v4.4s, v22.4s, v21.4s
-; CHECK-NEXT: add v5.4s, v23.4s, v21.4s
-; CHECK-NEXT: add v6.4s, v24.4s, v21.4s
-; CHECK-NEXT: add v7.4s, v16.4s, v21.4s
-; CHECK-NEXT: addhn2 v0.8h, v17.4s, v4.4s
-; CHECK-NEXT: addhn2 v1.8h, v18.4s, v5.4s
-; CHECK-NEXT: addhn2 v2.8h, v19.4s, v6.4s
-; CHECK-NEXT: addhn2 v3.8h, v20.4s, v7.4s
+; CHECK-NEXT: scvtf v16.4s, v0.4s
+; CHECK-NEXT: scvtf v17.4s, v1.4s
+; CHECK-NEXT: scvtf v18.4s, v2.4s
+; CHECK-NEXT: scvtf v19.4s, v3.4s
+; CHECK-NEXT: bfcvtn v0.4h, v4.4s
+; CHECK-NEXT: bfcvtn v1.4h, v5.4s
+; CHECK-NEXT: bfcvtn v2.4h, v6.4s
+; CHECK-NEXT: bfcvtn v3.4h, v7.4s
+; CHECK-NEXT: bfcvtn2 v0.8h, v16.4s
+; CHECK-NEXT: bfcvtn2 v1.8h, v17.4s
+; CHECK-NEXT: bfcvtn2 v2.8h, v18.4s
+; CHECK-NEXT: bfcvtn2 v3.8h, v19.4s
; CHECK-NEXT: ret
entry:
%c = sitofp <32 x i16> %a to <32 x bfloat>
@@ -1631,56 +1626,30 @@ entry:
define <32 x bfloat> @utofp_v32i16_v32bf16(<32 x i16> %a) {
; CHECK-LABEL: utofp_v32i16_v32bf16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ushll v4.4s, v1.4h, #0
-; CHECK-NEXT: ushll v5.4s, v0.4h, #0
+; CHECK-NEXT: ushll v4.4s, v0.4h, #0
+; CHECK-NEXT: ushll v5.4s, v1.4h, #0
; CHECK-NEXT: ushll v6.4s, v2.4h, #0
; CHECK-NEXT: ushll v7.4s, v3.4h, #0
; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0
; CHECK-NEXT: ushll2 v2.4s, v2.8h, #0
; CHECK-NEXT: ushll2 v3.4s, v3.8h, #0
-; CHECK-NEXT: movi v16.4s, #1
-; CHECK-NEXT: ucvtf v5.4s, v5.4s
; CHECK-NEXT: ucvtf v4.4s, v4.4s
+; CHECK-NEXT: ucvtf v5.4s, v5.4s
; CHECK-NEXT: ucvtf v6.4s, v6.4s
; CHECK-NEXT: ucvtf v7.4s, v7.4s
-; CHECK-NEXT: ucvtf v17.4s, v0.4s
-; CHECK-NEXT: ucvtf v18.4s, v1.4s
-; CHECK-NEXT: ucvtf v19.4s, v2.4s
-; CHECK-NEXT: ucvtf v20.4s, v3.4s
-; CHECK-NEXT: movi v21.4s, #127, msl #8
-; CHECK-NEXT: ushr v0.4s, v5.4s, #16
-; CHECK-NEXT: ushr v1.4s, v4.4s, #16
-; CHECK-NEXT: ushr v2.4s, v6.4s, #16
-; CHECK-NEXT: ushr v3.4s, v7.4s, #16
-; CHECK-NEXT: ushr v22.4s, v17.4s, #16
-; CHECK-NEXT: ushr v23.4s, v18.4s, #16
-; CHECK-NEXT: ushr v24.4s, v19.4s, #16
-; CHECK-NEXT: ushr v25.4s, v20.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v16.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v16.16b
-; CHECK-NEXT: and v2.16b, v2.16b, v16.16b
-; CHECK-NEXT: and v3.16b, v3.16b, v16.16b
-; CHECK-NEXT: and v22.16b, v22.16b, v16.16b
-; CHECK-NEXT: and v23.16b, v23.16b, v16.16b
-; CHECK-NEXT: and v24.16b, v24.16b, v16.16b
-; CHECK-NEXT: and v16.16b, v25.16b, v16.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v21.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v21.4s
-; CHECK-NEXT: add v2.4s, v2.4s, v21.4s
-; CHECK-NEXT: add v3.4s, v3.4s, v21.4s
-; CHECK-NEXT: addhn v0.4h, v5.4s, v0.4s
-; CHECK-NEXT: addhn v1.4h, v4.4s, v1.4s
-; CHECK-NEXT: addhn v2.4h, v6.4s, v2.4s
-; CHECK-NEXT: addhn v3.4h, v7.4s, v3.4s
-; CHECK-NEXT: add v4.4s, v22.4s, v21.4s
-; CHECK-NEXT: add v5.4s, v23.4s, v21.4s
-; CHECK-NEXT: add v6.4s, v24.4s, v21.4s
-; CHECK-NEXT: add v7.4s, v16.4s, v21.4s
-; CHECK-NEXT: addhn2 v0.8h, v17.4s, v4.4s
-; CHECK-NEXT: addhn2 v1.8h, v18.4s, v5.4s
-; CHECK-NEXT: addhn2 v2.8h, v19.4s, v6.4s
-; CHECK-NEXT: addhn2 v3.8h, v20.4s, v7.4s
+; CHECK-NEXT: ucvtf v16.4s, v0.4s
+; CHECK-NEXT: ucvtf v17.4s, v1.4s
+; CHECK-NEXT: ucvtf v18.4s, v2.4s
+; CHECK-NEXT: ucvtf v19.4s, v3.4s
+; CHECK-NEXT: bfcvtn v0.4h, v4.4s
+; CHECK-NEXT: bfcvtn v1.4h, v5.4s
+; CHECK-NEXT: bfcvtn v2.4h, v6.4s
+; CHECK-NEXT: bfcvtn v3.4h, v7.4s
+; CHECK-NEXT: bfcvtn2 v0.8h, v16.4s
+; CHECK-NEXT: bfcvtn2 v1.8h, v17.4s
+; CHECK-NEXT: bfcvtn2 v2.8h, v18.4s
+; CHECK-NEXT: bfcvtn2 v3.8h, v19.4s
; CHECK-NEXT: ret
entry:
%c = uitofp <32 x i16> %a to <32 x bfloat>
@@ -1688,398 +1657,446 @@ entry:
}
define <2 x bfloat> @stofp_v2i8_v2bf16(<2 x i8> %a) {
-; CHECK-LABEL: stofp_v2i8_v2bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov w9, v0.s[1]
-; CHECK-NEXT: fmov w10, s0
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: sxtb w10, w10
-; CHECK-NEXT: sxtb w9, w9
-; CHECK-NEXT: scvtf s1, w10
-; CHECK-NEXT: scvtf s0, w9
-; CHECK-NEXT: fmov w10, s1
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w12, w10, #16, #1
-; CHECK-NEXT: ubfx w11, w9, #16, #1
-; CHECK-NEXT: add w9, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: add w8, w12, w8
-; CHECK-NEXT: add w9, w11, w9
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: lsr w9, w9, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v2i8_v2bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: mov w8, v0.s[1]
+; CHECK-SD-NEXT: fmov w9, s0
+; CHECK-SD-NEXT: sxtb w9, w9
+; CHECK-SD-NEXT: sxtb w8, w8
+; CHECK-SD-NEXT: scvtf s1, w9
+; CHECK-SD-NEXT: scvtf s0, w8
+; CHECK-SD-NEXT: bfcvt h2, s0
+; CHECK-SD-NEXT: bfcvt h0, s1
+; CHECK-SD-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v2i8_v2bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: shl v0.2s, v0.2s, #24
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #24
+; CHECK-GI-NEXT: scvtf v0.2s, v0.2s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <2 x i8> %a to <2 x bfloat>
ret <2 x bfloat> %c
}
define <2 x bfloat> @utofp_v2i8_v2bf16(<2 x i8> %a) {
-; CHECK-LABEL: utofp_v2i8_v2bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov w9, v0.s[1]
-; CHECK-NEXT: fmov w10, s0
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: and w10, w10, #0xff
-; CHECK-NEXT: and w9, w9, #0xff
-; CHECK-NEXT: ucvtf s1, w10
-; CHECK-NEXT: ucvtf s0, w9
-; CHECK-NEXT: fmov w10, s1
-; CHECK-NEXT: fmov w9, s0
-; CHECK-NEXT: ubfx w12, w10, #16, #1
-; CHECK-NEXT: ubfx w11, w9, #16, #1
-; CHECK-NEXT: add w9, w9, w8
-; CHECK-NEXT: add w8, w10, w8
-; CHECK-NEXT: add w8, w12, w8
-; CHECK-NEXT: add w9, w11, w9
-; CHECK-NEXT: lsr w8, w8, #16
-; CHECK-NEXT: lsr w9, w9, #16
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v2i8_v2bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: mov w8, v0.s[1]
+; CHECK-SD-NEXT: fmov w9, s0
+; CHECK-SD-NEXT: and w9, w9, #0xff
+; CHECK-SD-NEXT: and w8, w8, #0xff
+; CHECK-SD-NEXT: ucvtf s1, w9
+; CHECK-SD-NEXT: ucvtf s0, w8
+; CHECK-SD-NEXT: bfcvt h2, s0
+; CHECK-SD-NEXT: bfcvt h0, s1
+; CHECK-SD-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v2i8_v2bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi d1, #0x0000ff000000ff
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ucvtf v0.2s, v0.2s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <2 x i8> %a to <2 x bfloat>
ret <2 x bfloat> %c
}
define <3 x bfloat> @stofp_v3i8_v3bf16(<3 x i8> %a) {
-; CHECK-LABEL: stofp_v3i8_v3bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: mov v0.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w2
-; CHECK-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-NEXT: sshr v0.4h, v0.4h, #8
-; CHECK-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v3i8_v3bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov s0, w0
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w2
+; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
+; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v3i8_v3bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov s0, w0
+; CHECK-GI-NEXT: mov v0.h[1], w1
+; CHECK-GI-NEXT: mov v0.h[2], w2
+; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8
+; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-GI-NEXT: mov v1.h[0], v0.h[2]
+; CHECK-GI-NEXT: mov v1.h[1], v0.h[3]
+; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <3 x i8> %a to <3 x bfloat>
ret <3 x bfloat> %c
}
define <3 x bfloat> @utofp_v3i8_v3bf16(<3 x i8> %a) {
-; CHECK-LABEL: utofp_v3i8_v3bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: mov v0.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w2
-; CHECK-NEXT: bic v0.4h, #255, lsl #8
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v3i8_v3bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fmov s0, w0
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w2
+; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v3i8_v3bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov s0, w0
+; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: mov v0.h[1], w1
+; CHECK-GI-NEXT: mov v0.h[2], w2
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov v1.h[0], v0.h[2]
+; CHECK-GI-NEXT: mov v1.h[1], v0.h[3]
+; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <3 x i8> %a to <3 x bfloat>
ret <3 x bfloat> %c
}
define <4 x bfloat> @stofp_v4i8_v4bf16(<4 x i8> %a) {
-; CHECK-LABEL: stofp_v4i8_v4bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: sshr v0.4h, v0.4h, #8
-; CHECK-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-NEXT: scvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v4i8_v4bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
+; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: scvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v4i8_v4bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT: shl v0.4s, v0.4s, #24
+; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #24
+; CHECK-GI-NEXT: scvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <4 x i8> %a to <4 x bfloat>
ret <4 x bfloat> %c
}
define <4 x bfloat> @utofp_v4i8_v4bf16(<4 x i8> %a) {
-; CHECK-LABEL: utofp_v4i8_v4bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: bic v0.4h, #255, lsl #8
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: ucvtf v0.4s, v0.4s
-; CHECK-NEXT: ushr v2.4s, v0.4s, #16
-; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-NEXT: movi v2.4s, #127, msl #8
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v0.4s, v2.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v4i8_v4bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v4i8_v4bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <4 x i8> %a to <4 x bfloat>
ret <4 x bfloat> %c
}
define <8 x bfloat> @stofp_v8i8_v8bf16(<8 x i8> %a) {
-; CHECK-LABEL: stofp_v8i8_v8bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: movi v4.4s, #127, msl #8
-; CHECK-NEXT: sshll v2.4s, v0.4h, #0
-; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: scvtf v2.4s, v2.4s
-; CHECK-NEXT: scvtf v3.4s, v0.4s
-; CHECK-NEXT: ushr v0.4s, v2.4s, #16
-; CHECK-NEXT: ushr v5.4s, v3.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v1.16b, v5.16b, v1.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v4.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: addhn v0.4h, v2.4s, v0.4s
-; CHECK-NEXT: addhn2 v0.8h, v3.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v8i8_v8bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: scvtf v1.4s, v1.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v1.4s
+; CHECK-SD-NEXT: scvtf v1.4s, v2.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v8i8_v8bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: scvtf v1.4s, v1.4s
+; CHECK-GI-NEXT: scvtf v2.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v1.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <8 x i8> %a to <8 x bfloat>
ret <8 x bfloat> %c
}
define <8 x bfloat> @utofp_v8i8_v8bf16(<8 x i8> %a) {
-; CHECK-LABEL: utofp_v8i8_v8bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: movi v4.4s, #127, msl #8
-; CHECK-NEXT: ushll v2.4s, v0.4h, #0
-; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: ucvtf v2.4s, v2.4s
-; CHECK-NEXT: ucvtf v3.4s, v0.4s
-; CHECK-NEXT: ushr v0.4s, v2.4s, #16
-; CHECK-NEXT: ushr v5.4s, v3.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v1.16b, v5.16b, v1.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v4.4s
-; CHECK-NEXT: add v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: addhn v0.4h, v2.4s, v0.4s
-; CHECK-NEXT: addhn2 v0.8h, v3.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v8i8_v8bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v1.4s
+; CHECK-SD-NEXT: ucvtf v1.4s, v2.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v1.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v8i8_v8bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-GI-NEXT: ucvtf v2.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v1.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <8 x i8> %a to <8 x bfloat>
ret <8 x bfloat> %c
}
define <16 x bfloat> @stofp_v16i8_v16bf16(<16 x i8> %a) {
-; CHECK-LABEL: stofp_v16i8_v16bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sshll2 v2.8h, v0.16b, #0
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: movi v7.4s, #127, msl #8
-; CHECK-NEXT: sshll v3.4s, v2.4h, #0
-; CHECK-NEXT: sshll v4.4s, v0.4h, #0
-; CHECK-NEXT: sshll2 v2.4s, v2.8h, #0
-; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: scvtf v3.4s, v3.4s
-; CHECK-NEXT: scvtf v4.4s, v4.4s
-; CHECK-NEXT: scvtf v2.4s, v2.4s
-; CHECK-NEXT: scvtf v6.4s, v0.4s
-; CHECK-NEXT: ushr v5.4s, v3.4s, #16
-; CHECK-NEXT: ushr v0.4s, v4.4s, #16
-; CHECK-NEXT: ushr v16.4s, v2.4s, #16
-; CHECK-NEXT: ushr v17.4s, v6.4s, #16
-; CHECK-NEXT: and v5.16b, v5.16b, v1.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v16.16b, v16.16b, v1.16b
-; CHECK-NEXT: and v17.16b, v17.16b, v1.16b
-; CHECK-NEXT: add v5.4s, v5.4s, v7.4s
-; CHECK-NEXT: add v0.4s, v0.4s, v7.4s
-; CHECK-NEXT: addhn v1.4h, v3.4s, v5.4s
-; CHECK-NEXT: addhn v0.4h, v4.4s, v0.4s
-; CHECK-NEXT: add v3.4s, v16.4s, v7.4s
-; CHECK-NEXT: add v4.4s, v17.4s, v7.4s
-; CHECK-NEXT: addhn2 v1.8h, v2.4s, v3.4s
-; CHECK-NEXT: addhn2 v0.8h, v6.4s, v4.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v16i8_v16bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sshll2 v1.8h, v0.16b, #0
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: sshll v2.4s, v1.4h, #0
+; CHECK-SD-NEXT: sshll v3.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v4.4s, v1.8h, #0
+; CHECK-SD-NEXT: sshll2 v5.4s, v0.8h, #0
+; CHECK-SD-NEXT: scvtf v2.4s, v2.4s
+; CHECK-SD-NEXT: scvtf v3.4s, v3.4s
+; CHECK-SD-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-SD-NEXT: scvtf v2.4s, v4.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v3.4s
+; CHECK-SD-NEXT: scvtf v3.4s, v5.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v2.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v3.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v16i8_v16bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v1.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll v2.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll v3.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v1.4s, v1.8h, #0
+; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: scvtf v2.4s, v2.4s
+; CHECK-GI-NEXT: scvtf v3.4s, v3.4s
+; CHECK-GI-NEXT: scvtf v4.4s, v1.4s
+; CHECK-GI-NEXT: scvtf v5.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn v1.4h, v3.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <16 x i8> %a to <16 x bfloat>
ret <16 x bfloat> %c
}
define <16 x bfloat> @utofp_v16i8_v16bf16(<16 x i8> %a) {
-; CHECK-LABEL: utofp_v16i8_v16bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ushll2 v2.8h, v0.16b, #0
-; CHECK-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: movi v7.4s, #127, msl #8
-; CHECK-NEXT: ushll v3.4s, v2.4h, #0
-; CHECK-NEXT: ushll v4.4s, v0.4h, #0
-; CHECK-NEXT: ushll2 v2.4s, v2.8h, #0
-; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: ucvtf v3.4s, v3.4s
-; CHECK-NEXT: ucvtf v4.4s, v4.4s
-; CHECK-NEXT: ucvtf v2.4s, v2.4s
-; CHECK-NEXT: ucvtf v6.4s, v0.4s
-; CHECK-NEXT: ushr v5.4s, v3.4s, #16
-; CHECK-NEXT: ushr v0.4s, v4.4s, #16
-; CHECK-NEXT: ushr v16.4s, v2.4s, #16
-; CHECK-NEXT: ushr v17.4s, v6.4s, #16
-; CHECK-NEXT: and v5.16b, v5.16b, v1.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v16.16b, v16.16b, v1.16b
-; CHECK-NEXT: and v17.16b, v17.16b, v1.16b
-; CHECK-NEXT: add v5.4s, v5.4s, v7.4s
-; CHECK-NEXT: add v0.4s, v0.4s, v7.4s
-; CHECK-NEXT: addhn v1.4h, v3.4s, v5.4s
-; CHECK-NEXT: addhn v0.4h, v4.4s, v0.4s
-; CHECK-NEXT: add v3.4s, v16.4s, v7.4s
-; CHECK-NEXT: add v4.4s, v17.4s, v7.4s
-; CHECK-NEXT: addhn2 v1.8h, v2.4s, v3.4s
-; CHECK-NEXT: addhn2 v0.8h, v6.4s, v4.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v16i8_v16bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ushll2 v1.8h, v0.16b, #0
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: ushll v2.4s, v1.4h, #0
+; CHECK-SD-NEXT: ushll v3.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v4.4s, v1.8h, #0
+; CHECK-SD-NEXT: ushll2 v5.4s, v0.8h, #0
+; CHECK-SD-NEXT: ucvtf v2.4s, v2.4s
+; CHECK-SD-NEXT: ucvtf v3.4s, v3.4s
+; CHECK-SD-NEXT: bfcvtn v1.4h, v2.4s
+; CHECK-SD-NEXT: ucvtf v2.4s, v4.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v3.4s
+; CHECK-SD-NEXT: ucvtf v3.4s, v5.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v2.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v3.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v16i8_v16bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v1.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll v2.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll v3.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
+; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: ucvtf v2.4s, v2.4s
+; CHECK-GI-NEXT: ucvtf v3.4s, v3.4s
+; CHECK-GI-NEXT: ucvtf v4.4s, v1.4s
+; CHECK-GI-NEXT: ucvtf v5.4s, v0.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v2.4s
+; CHECK-GI-NEXT: bfcvtn v1.4h, v3.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v5.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <16 x i8> %a to <16 x bfloat>
ret <16 x bfloat> %c
}
define <32 x bfloat> @stofp_v32i8_v32bf16(<32 x i8> %a) {
-; CHECK-LABEL: stofp_v32i8_v32bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sshll2 v3.8h, v0.16b, #0
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: sshll2 v4.8h, v1.16b, #0
-; CHECK-NEXT: sshll v1.8h, v1.8b, #0
-; CHECK-NEXT: movi v2.4s, #1
-; CHECK-NEXT: movi v21.4s, #127, msl #8
-; CHECK-NEXT: sshll v5.4s, v3.4h, #0
-; CHECK-NEXT: sshll v6.4s, v0.4h, #0
-; CHECK-NEXT: sshll v7.4s, v4.4h, #0
-; CHECK-NEXT: sshll v16.4s, v1.4h, #0
-; CHECK-NEXT: sshll2 v3.4s, v3.8h, #0
-; CHECK-NEXT: sshll2 v4.4s, v4.8h, #0
-; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: sshll2 v1.4s, v1.8h, #0
-; CHECK-NEXT: scvtf v5.4s, v5.4s
-; CHECK-NEXT: scvtf v6.4s, v6.4s
-; CHECK-NEXT: scvtf v7.4s, v7.4s
-; CHECK-NEXT: scvtf v16.4s, v16.4s
-; CHECK-NEXT: scvtf v17.4s, v3.4s
-; CHECK-NEXT: scvtf v4.4s, v4.4s
-; CHECK-NEXT: scvtf v18.4s, v0.4s
-; CHECK-NEXT: scvtf v19.4s, v1.4s
-; CHECK-NEXT: ushr v0.4s, v5.4s, #16
-; CHECK-NEXT: ushr v3.4s, v6.4s, #16
-; CHECK-NEXT: ushr v1.4s, v7.4s, #16
-; CHECK-NEXT: ushr v20.4s, v16.4s, #16
-; CHECK-NEXT: ushr v23.4s, v17.4s, #16
-; CHECK-NEXT: ushr v24.4s, v4.4s, #16
-; CHECK-NEXT: ushr v22.4s, v18.4s, #16
-; CHECK-NEXT: ushr v25.4s, v19.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v3.16b, v3.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: and v20.16b, v20.16b, v2.16b
-; CHECK-NEXT: and v23.16b, v23.16b, v2.16b
-; CHECK-NEXT: and v24.16b, v24.16b, v2.16b
-; CHECK-NEXT: and v22.16b, v22.16b, v2.16b
-; CHECK-NEXT: and v25.16b, v25.16b, v2.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v21.4s
-; CHECK-NEXT: add v3.4s, v3.4s, v21.4s
-; CHECK-NEXT: add v26.4s, v1.4s, v21.4s
-; CHECK-NEXT: add v20.4s, v20.4s, v21.4s
-; CHECK-NEXT: addhn v1.4h, v5.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v6.4s, v3.4s
-; CHECK-NEXT: addhn v3.4h, v7.4s, v26.4s
-; CHECK-NEXT: addhn v2.4h, v16.4s, v20.4s
-; CHECK-NEXT: add v5.4s, v22.4s, v21.4s
-; CHECK-NEXT: add v6.4s, v23.4s, v21.4s
-; CHECK-NEXT: add v7.4s, v24.4s, v21.4s
-; CHECK-NEXT: add v16.4s, v25.4s, v21.4s
-; CHECK-NEXT: addhn2 v0.8h, v18.4s, v5.4s
-; CHECK-NEXT: addhn2 v1.8h, v17.4s, v6.4s
-; CHECK-NEXT: addhn2 v3.8h, v4.4s, v7.4s
-; CHECK-NEXT: addhn2 v2.8h, v19.4s, v16.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stofp_v32i8_v32bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-SD-NEXT: sshll2 v0.8h, v0.16b, #0
+; CHECK-SD-NEXT: sshll2 v3.8h, v1.16b, #0
+; CHECK-SD-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-SD-NEXT: sshll v4.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll v6.4s, v3.4h, #0
+; CHECK-SD-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-SD-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v3.8h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v1.8h, #0
+; CHECK-SD-NEXT: scvtf v4.4s, v4.4s
+; CHECK-SD-NEXT: scvtf v5.4s, v5.4s
+; CHECK-SD-NEXT: scvtf v6.4s, v6.4s
+; CHECK-SD-NEXT: scvtf v7.4s, v7.4s
+; CHECK-SD-NEXT: scvtf v16.4s, v0.4s
+; CHECK-SD-NEXT: scvtf v17.4s, v3.4s
+; CHECK-SD-NEXT: scvtf v18.4s, v2.4s
+; CHECK-SD-NEXT: scvtf v19.4s, v1.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v4.4s
+; CHECK-SD-NEXT: bfcvtn v1.4h, v5.4s
+; CHECK-SD-NEXT: bfcvtn v3.4h, v6.4s
+; CHECK-SD-NEXT: bfcvtn v2.4h, v7.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v18.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v16.4s
+; CHECK-SD-NEXT: bfcvtn2 v3.8h, v17.4s
+; CHECK-SD-NEXT: bfcvtn2 v2.8h, v19.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stofp_v32i8_v32bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: sshll v4.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v6.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v2.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: sshll2 v1.4s, v1.8h, #0
+; CHECK-GI-NEXT: scvtf v4.4s, v4.4s
+; CHECK-GI-NEXT: scvtf v5.4s, v5.4s
+; CHECK-GI-NEXT: scvtf v6.4s, v6.4s
+; CHECK-GI-NEXT: scvtf v7.4s, v7.4s
+; CHECK-GI-NEXT: scvtf v16.4s, v2.4s
+; CHECK-GI-NEXT: scvtf v17.4s, v0.4s
+; CHECK-GI-NEXT: scvtf v18.4s, v3.4s
+; CHECK-GI-NEXT: scvtf v19.4s, v1.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v4.4s
+; CHECK-GI-NEXT: bfcvtn v1.4h, v5.4s
+; CHECK-GI-NEXT: bfcvtn v2.4h, v6.4s
+; CHECK-GI-NEXT: bfcvtn v3.4h, v7.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v16.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v17.4s
+; CHECK-GI-NEXT: bfcvtn2 v2.8h, v18.4s
+; CHECK-GI-NEXT: bfcvtn2 v3.8h, v19.4s
+; CHECK-GI-NEXT: ret
entry:
%c = sitofp <32 x i8> %a to <32 x bfloat>
ret <32 x bfloat> %c
}
define <32 x bfloat> @utofp_v32i8_v32bf16(<32 x i8> %a) {
-; CHECK-LABEL: utofp_v32i8_v32bf16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ushll2 v3.8h, v0.16b, #0
-; CHECK-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-NEXT: ushll2 v4.8h, v1.16b, #0
-; CHECK-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-NEXT: movi v2.4s, #1
-; CHECK-NEXT: movi v21.4s, #127, msl #8
-; CHECK-NEXT: ushll v5.4s, v3.4h, #0
-; CHECK-NEXT: ushll v6.4s, v0.4h, #0
-; CHECK-NEXT: ushll v7.4s, v4.4h, #0
-; CHECK-NEXT: ushll v16.4s, v1.4h, #0
-; CHECK-NEXT: ushll2 v3.4s, v3.8h, #0
-; CHECK-NEXT: ushll2 v4.4s, v4.8h, #0
-; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0
-; CHECK-NEXT: ucvtf v5.4s, v5.4s
-; CHECK-NEXT: ucvtf v6.4s, v6.4s
-; CHECK-NEXT: ucvtf v7.4s, v7.4s
-; CHECK-NEXT: ucvtf v16.4s, v16.4s
-; CHECK-NEXT: ucvtf v17.4s, v3.4s
-; CHECK-NEXT: ucvtf v4.4s, v4.4s
-; CHECK-NEXT: ucvtf v18.4s, v0.4s
-; CHECK-NEXT: ucvtf v19.4s, v1.4s
-; CHECK-NEXT: ushr v0.4s, v5.4s, #16
-; CHECK-NEXT: ushr v3.4s, v6.4s, #16
-; CHECK-NEXT: ushr v1.4s, v7.4s, #16
-; CHECK-NEXT: ushr v20.4s, v16.4s, #16
-; CHECK-NEXT: ushr v23.4s, v17.4s, #16
-; CHECK-NEXT: ushr v24.4s, v4.4s, #16
-; CHECK-NEXT: ushr v22.4s, v18.4s, #16
-; CHECK-NEXT: ushr v25.4s, v19.4s, #16
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v3.16b, v3.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: and v20.16b, v20.16b, v2.16b
-; CHECK-NEXT: and v23.16b, v23.16b, v2.16b
-; CHECK-NEXT: and v24.16b, v24.16b, v2.16b
-; CHECK-NEXT: and v22.16b, v22.16b, v2.16b
-; CHECK-NEXT: and v25.16b, v25.16b, v2.16b
-; CHECK-NEXT: add v0.4s, v0.4s, v21.4s
-; CHECK-NEXT: add v3.4s, v3.4s, v21.4s
-; CHECK-NEXT: add v26.4s, v1.4s, v21.4s
-; CHECK-NEXT: add v20.4s, v20.4s, v21.4s
-; CHECK-NEXT: addhn v1.4h, v5.4s, v0.4s
-; CHECK-NEXT: addhn v0.4h, v6.4s, v3.4s
-; CHECK-NEXT: addhn v3.4h, v7.4s, v26.4s
-; CHECK-NEXT: addhn v2.4h, v16.4s, v20.4s
-; CHECK-NEXT: add v5.4s, v22.4s, v21.4s
-; CHECK-NEXT: add v6.4s, v23.4s, v21.4s
-; CHECK-NEXT: add v7.4s, v24.4s, v21.4s
-; CHECK-NEXT: add v16.4s, v25.4s, v21.4s
-; CHECK-NEXT: addhn2 v0.8h, v18.4s, v5.4s
-; CHECK-NEXT: addhn2 v1.8h, v17.4s, v6.4s
-; CHECK-NEXT: addhn2 v3.8h, v4.4s, v7.4s
-; CHECK-NEXT: addhn2 v2.8h, v19.4s, v16.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utofp_v32i8_v32bf16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-SD-NEXT: ushll2 v3.8h, v1.16b, #0
+; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-SD-NEXT: ushll v4.4s, v2.4h, #0
+; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll v6.4s, v3.4h, #0
+; CHECK-SD-NEXT: ushll v7.4s, v1.4h, #0
+; CHECK-SD-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll2 v3.4s, v3.8h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v2.8h, #0
+; CHECK-SD-NEXT: ushll2 v1.4s, v1.8h, #0
+; CHECK-SD-NEXT: ucvtf v4.4s, v4.4s
+; CHECK-SD-NEXT: ucvtf v5.4s, v5.4s
+; CHECK-SD-NEXT: ucvtf v6.4s, v6.4s
+; CHECK-SD-NEXT: ucvtf v7.4s, v7.4s
+; CHECK-SD-NEXT: ucvtf v16.4s, v0.4s
+; CHECK-SD-NEXT: ucvtf v17.4s, v3.4s
+; CHECK-SD-NEXT: ucvtf v18.4s, v2.4s
+; CHECK-SD-NEXT: ucvtf v19.4s, v1.4s
+; CHECK-SD-NEXT: bfcvtn v0.4h, v4.4s
+; CHECK-SD-NEXT: bfcvtn v1.4h, v5.4s
+; CHECK-SD-NEXT: bfcvtn v3.4h, v6.4s
+; CHECK-SD-NEXT: bfcvtn v2.4h, v7.4s
+; CHECK-SD-NEXT: bfcvtn2 v0.8h, v18.4s
+; CHECK-SD-NEXT: bfcvtn2 v1.8h, v16.4s
+; CHECK-SD-NEXT: bfcvtn2 v3.8h, v17.4s
+; CHECK-SD-NEXT: bfcvtn2 v2.8h, v19.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utofp_v32i8_v32bf16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: ushll v4.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll v5.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v6.4s, v3.4h, #0
+; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v2.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
+; CHECK-GI-NEXT: ucvtf v4.4s, v4.4s
+; CHECK-GI-NEXT: ucvtf v5.4s, v5.4s
+; CHECK-GI-NEXT: ucvtf v6.4s, v6.4s
+; CHECK-GI-NEXT: ucvtf v7.4s, v7.4s
+; CHECK-GI-NEXT: ucvtf v16.4s, v2.4s
+; CHECK-GI-NEXT: ucvtf v17.4s, v0.4s
+; CHECK-GI-NEXT: ucvtf v18.4s, v3.4s
+; CHECK-GI-NEXT: ucvtf v19.4s, v1.4s
+; CHECK-GI-NEXT: bfcvtn v0.4h, v4.4s
+; CHECK-GI-NEXT: bfcvtn v1.4h, v5.4s
+; CHECK-GI-NEXT: bfcvtn v2.4h, v6.4s
+; CHECK-GI-NEXT: bfcvtn v3.4h, v7.4s
+; CHECK-GI-NEXT: bfcvtn2 v0.8h, v16.4s
+; CHECK-GI-NEXT: bfcvtn2 v1.8h, v17.4s
+; CHECK-GI-NEXT: bfcvtn2 v2.8h, v18.4s
+; CHECK-GI-NEXT: bfcvtn2 v3.8h, v19.4s
+; CHECK-GI-NEXT: ret
entry:
%c = uitofp <32 x i8> %a to <32 x bfloat>
ret <32 x bfloat> %c
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-GI: {{.*}}
; CHECK-GI-FP16: {{.*}}
; CHECK-GI-NOFP16: {{.*}}
-; CHECK-SD: {{.*}}
; CHECK-SD-FP16: {{.*}}
; CHECK-SD-NOFP16: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/mul.ll b/llvm/test/CodeGen/AArch64/mul.ll
index 475bd22c6ebcb..10400fd442cb1 100644
--- a/llvm/test/CodeGen/AArch64/mul.ll
+++ b/llvm/test/CodeGen/AArch64/mul.ll
@@ -186,8 +186,7 @@ define void @v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: mul v0.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll b/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
index 5753798e87512..b35511dd4ab69 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
@@ -786,7 +786,7 @@ define <2 x i8> @extract_scalable_vec() vscale_range(1,16) "target-features"="+s
; CHECK-GI-LABEL: extract_scalable_vec:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov x8, xzr
-; CHECK-GI-NEXT: mov x9, #1 // =0x1
+; CHECK-GI-NEXT: mov w9, #1 // =0x1
; CHECK-GI-NEXT: ld1 { v0.b }[0], [x8]
; CHECK-GI-NEXT: ldr b1, [x9]
; CHECK-GI-NEXT: adrp x8, .LCPI36_0
diff --git a/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll b/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
index d9cdbc2f92aca..2191b67fc816a 100644
--- a/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
+++ b/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
@@ -4,8 +4,8 @@
define <4 x i32> @test_vins_v4i32(<4 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v4i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret
entry:
%c = bitcast float %b to i32
@@ -16,8 +16,8 @@ entry:
define <4 x i32> @test_vins_v4i32_0(<4 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v4i32_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-NEXT: mov v0.s[0], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[0], w8
; CHECK-NEXT: ret
entry:
%c = bitcast float %b to i32
@@ -28,9 +28,9 @@ entry:
define <2 x i32> @test_vins_v2i32(<2 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v2i32:
; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
@@ -42,9 +42,9 @@ entry:
define <2 x i32> @test_vins_v2i32_0(<2 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v2i32_0:
; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-NEXT: mov v0.s[0], v1.s[0]
+; CHECK-NEXT: mov v0.s[0], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
@@ -56,8 +56,8 @@ entry:
define <2 x i64> @test_vins_v2i64(<2 x i64> %a, double %b) {
; CHECK-LABEL: test_vins_v2i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: fmov x8, d1
+; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret
entry:
%c = bitcast double %b to i64
@@ -68,8 +68,8 @@ entry:
define <2 x i64> @test_vins_v2i64_0(<2 x i64> %a, double %b) {
; CHECK-LABEL: test_vins_v2i64_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT: mov v0.d[0], v1.d[0]
+; CHECK-NEXT: fmov x8, d1
+; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret
entry:
%c = bitcast double %b to i64
diff --git a/llvm/test/CodeGen/AArch64/popcount.ll b/llvm/test/CodeGen/AArch64/popcount.ll
index 3900910c10318..65671076a01bc 100644
--- a/llvm/test/CodeGen/AArch64/popcount.ll
+++ b/llvm/test/CodeGen/AArch64/popcount.ll
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+neon,+dotprod | FileCheck %s --check-prefixes=CHECK,DOT
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+sve | FileCheck %s --check-prefixes=CHECK,SVE
; RUN: llc < %s -mtriple=aarch64_be-unknown-unknown | FileCheck %s --check-prefixes=BE
-; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=GISEL
+; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=GISEL,GISELO3
; RUN: llc < %s -O0 -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=GISELO0
; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown -mattr=+neon | FileCheck %s --check-prefixes=GISEL,NEON-GISEL
; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown -mattr=+neon,+dotprod | FileCheck %s --check-prefixes=GISEL,DOT-GISEL
@@ -397,6 +397,14 @@ define <2 x i64> @popcount2x64(<2 x i64> %0) {
; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; BE-NEXT: ret
;
+; GISELO3-LABEL: popcount2x64:
+; GISELO3: // %bb.0: // %Entry
+; GISELO3-NEXT: cnt v0.16b, v0.16b
+; GISELO3-NEXT: uaddlp v0.8h, v0.16b
+; GISELO3-NEXT: uaddlp v0.4s, v0.8h
+; GISELO3-NEXT: uaddlp v0.2d, v0.4s
+; GISELO3-NEXT: ret
+;
; GISELO0-LABEL: popcount2x64:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.16b, v0.16b
@@ -429,6 +437,13 @@ define <2 x i64> @popcount2x64(<2 x i64> %0) {
; SVE-GISEL-NEXT: uaddlp v0.4s, v0.8h
; SVE-GISEL-NEXT: uaddlp v0.2d, v0.4s
; SVE-GISEL-NEXT: ret
+; GISEL-O3-LABEL: popcount2x64:
+; GISEL-O3: // %bb.0: // %Entry
+; GISEL-O3-NEXT: cnt v0.16b, v0.16b
+; GISEL-O3-NEXT: uaddlp v0.8h, v0.16b
+; GISEL-O3-NEXT: uaddlp v0.4s, v0.8h
+; GISEL-O3-NEXT: uaddlp v0.2d, v0.4s
+; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
ret <2 x i64> %1
@@ -550,6 +565,13 @@ define <4 x i32> @popcount4x32(<4 x i32> %0) {
; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; BE-NEXT: ret
;
+; GISELO3-LABEL: popcount4x32:
+; GISELO3: // %bb.0: // %Entry
+; GISELO3-NEXT: cnt v0.16b, v0.16b
+; GISELO3-NEXT: uaddlp v0.8h, v0.16b
+; GISELO3-NEXT: uaddlp v0.4s, v0.8h
+; GISELO3-NEXT: ret
+;
; GISELO0-LABEL: popcount4x32:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.16b, v0.16b
@@ -579,6 +601,12 @@ define <4 x i32> @popcount4x32(<4 x i32> %0) {
; SVE-GISEL-NEXT: uaddlp v0.8h, v0.16b
; SVE-GISEL-NEXT: uaddlp v0.4s, v0.8h
; SVE-GISEL-NEXT: ret
+; GISEL-O3-LABEL: popcount4x32:
+; GISEL-O3: // %bb.0: // %Entry
+; GISEL-O3-NEXT: cnt v0.16b, v0.16b
+; GISEL-O3-NEXT: uaddlp v0.8h, v0.16b
+; GISEL-O3-NEXT: uaddlp v0.4s, v0.8h
+; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
ret <4 x i32> %1
@@ -627,6 +655,13 @@ define <2 x i32> @popcount2x32(<2 x i32> %0) {
; BE-NEXT: rev64 v0.2s, v0.2s
; BE-NEXT: ret
;
+; GISELO3-LABEL: popcount2x32:
+; GISELO3: // %bb.0: // %Entry
+; GISELO3-NEXT: cnt v0.8b, v0.8b
+; GISELO3-NEXT: uaddlp v0.4h, v0.8b
+; GISELO3-NEXT: uaddlp v0.2s, v0.4h
+; GISELO3-NEXT: ret
+;
; GISELO0-LABEL: popcount2x32:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.8b, v0.8b
@@ -656,6 +691,12 @@ define <2 x i32> @popcount2x32(<2 x i32> %0) {
; SVE-GISEL-NEXT: uaddlp v0.4h, v0.8b
; SVE-GISEL-NEXT: uaddlp v0.2s, v0.4h
; SVE-GISEL-NEXT: ret
+; GISEL-O3-LABEL: popcount2x32:
+; GISEL-O3: // %bb.0: // %Entry
+; GISEL-O3-NEXT: cnt v0.8b, v0.8b
+; GISEL-O3-NEXT: uaddlp v0.4h, v0.8b
+; GISEL-O3-NEXT: uaddlp v0.2s, v0.4h
+; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %0)
ret <2 x i32> %1
diff --git a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
index 7011b946aad74..b9e0a7f11d466 100644
--- a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
+++ b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
@@ -185,7 +185,7 @@ define i64 @blend_and_sign_same_bb(i64 %addr) {
; GISEL-NEXT: {{ $}}
; GISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; GISEL-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @discvar
- ; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (s64) from @discvar)
+ ; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (i64) from @discvar)
; GISEL-NEXT: [[MOVKXi:%[0-9]+]]:gpr64noip = MOVKXi [[LDRXui]], 42, 48
; GISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64noip = COPY [[LDRXui]]
; GISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, [[COPY1]], implicit-def dead $x16, implicit-def dead $x17
@@ -237,7 +237,7 @@ define i64 @blend_and_sign_different_bbs(i64 %addr, i64 %cond) {
; GISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; GISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; GISEL-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @discvar
- ; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (s64) from @discvar)
+ ; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (i64) from @discvar)
; GISEL-NEXT: [[MOVKXi:%[0-9]+]]:gpr64noip = MOVKXi [[LDRXui]], 42, 48
; GISEL-NEXT: CBZX [[COPY1]], %bb.3
; GISEL-NEXT: B %bb.2
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
index b31a5ea0b5d79..88f1324762f8f 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
@@ -146,8 +146,7 @@ define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
; CHECK-GI-NEXT: sqadd v0.8b, v3.8b, v5.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x2]
+; CHECK-GI-NEXT: str s0, [x2]
; CHECK-GI-NEXT: ret
%x = load <4 x i8>, ptr %px
%y = load <4 x i8>, ptr %py
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
index 02eb40b412efd..55608f6ef21b8 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
@@ -146,8 +146,7 @@ define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
; CHECK-GI-NEXT: sqsub v0.8b, v3.8b, v5.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x2]
+; CHECK-GI-NEXT: str s0, [x2]
; CHECK-GI-NEXT: ret
%x = load <4 x i8>, ptr %px
%y = load <4 x i8>, ptr %py
diff --git a/llvm/test/CodeGen/AArch64/sub.ll b/llvm/test/CodeGen/AArch64/sub.ll
index dd920b98e18eb..402f35e134dbe 100644
--- a/llvm/test/CodeGen/AArch64/sub.ll
+++ b/llvm/test/CodeGen/AArch64/sub.ll
@@ -174,8 +174,7 @@ define void @v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: sub v0.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
index cd02d18e61643..644313c953607 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
@@ -143,8 +143,7 @@ define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
; CHECK-GI-NEXT: uqadd v0.8b, v3.8b, v5.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x2]
+; CHECK-GI-NEXT: str s0, [x2]
; CHECK-GI-NEXT: ret
%x = load <4 x i8>, ptr %px
%y = load <4 x i8>, ptr %py
diff --git a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
index ef70137e6deee..9a982f0196755 100644
--- a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
@@ -143,8 +143,7 @@ define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
; CHECK-GI-NEXT: uqsub v0.8b, v3.8b, v5.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x2]
+; CHECK-GI-NEXT: str s0, [x2]
; CHECK-GI-NEXT: ret
%x = load <4 x i8>, ptr %px
%y = load <4 x i8>, ptr %py
>From c41de35c9a1717326a80a8f9b6bf7bf36701cdb0 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 31 Dec 2025 10:30:26 +0000
Subject: [PATCH 39/41] Merge should not force values onto GPR if the operands
are on FPR registers
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 5 +-
llvm/test/CodeGen/AArch64/arm64-fp128.ll | 26 +-
llvm/test/CodeGen/AArch64/fcmp.ll | 68 +-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 53 +-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 580 +++++++++---------
.../test/CodeGen/AArch64/fptoui-sat-scalar.ll | 37 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 488 +++++++--------
llvm/test/CodeGen/AArch64/phi.ll | 18 +-
8 files changed, 596 insertions(+), 679 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 507f4d044c396..89981f6b4c22e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -1068,14 +1068,17 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
}
- case TargetOpcode::G_UNMERGE_VALUES: {
+ case TargetOpcode::G_UNMERGE_VALUES:
// If the first operand belongs to a FPR register bank, then make sure that
// we preserve that.
if (OpRegBankIdx[0] != PMI_FirstGPR)
break;
+ [[fallthrough]];
+ case TargetOpcode::G_MERGE_VALUES: {
LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
// UNMERGE into scalars from a vector should always use FPR.
+ // MERGE into a vector should use FPR if the operands are already on FPR.
// Likewise if any of the uses are FP instructions.
if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index 498dce138febf..1ba92d510c74a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -302,10 +302,8 @@ define fp128 @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: fcsel d0, d0, d1, ne
; CHECK-GI-NEXT: fcsel d1, d2, d3, ne
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
%val = select i1 %cond, fp128 %lhs, fp128 %rhs
ret fp128 %val
@@ -1156,18 +1154,14 @@ define <2 x fp128> @vec_select(<2 x i1> %cond, <2 x fp128> %lhs, <2 x fp128> %rh
; CHECK-GI-NEXT: fcsel d0, d1, d3, ne
; CHECK-GI-NEXT: fcsel d3, d5, d6, ne
; CHECK-GI-NEXT: tst w8, #0x1
-; CHECK-GI-NEXT: mov d1, v2.d[1]
-; CHECK-GI-NEXT: mov d5, v4.d[1]
-; CHECK-GI-NEXT: fcsel d2, d2, d4, ne
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: fmov x9, d2
-; CHECK-GI-NEXT: fcsel d2, d1, d5, ne
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d3
-; CHECK-GI-NEXT: mov v1.d[0], x9
-; CHECK-GI-NEXT: fmov x9, d2
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
+; CHECK-GI-NEXT: mov d5, v2.d[1]
+; CHECK-GI-NEXT: mov d6, v4.d[1]
+; CHECK-GI-NEXT: fcsel d1, d2, d4, ne
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
+; CHECK-GI-NEXT: fcsel d2, d5, d6, ne
+; CHECK-GI-NEXT: mov v0.d[1], v3.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
; CHECK-GI-NEXT: ret
%val = select <2 x i1> %cond, <2 x fp128> %lhs, <2 x fp128> %rhs
ret <2 x fp128> %val
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index 2c76de454a39a..450a121d8b6a6 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -31,17 +31,15 @@ define fp128 @f128_fp128(fp128 %a, fp128 %b, fp128 %d, fp128 %e) {
; CHECK-GI-NEXT: .cfi_offset w30, -16
; CHECK-GI-NEXT: stp q3, q2, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q3, q2, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q3, q0, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
-; CHECK-GI-NEXT: mov d0, v2.d[1]
-; CHECK-GI-NEXT: mov d1, v3.d[1]
-; CHECK-GI-NEXT: fcsel d2, d2, d3, mi
-; CHECK-GI-NEXT: fmov x8, d2
-; CHECK-GI-NEXT: fcsel d1, d0, d1, mi
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: mov d2, v3.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d3, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d2, mi
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
entry:
@@ -477,21 +475,17 @@ define <2 x fp128> @v2f128_fp128(<2 x fp128> %a, <2 x fp128> %b, <2 x fp128> %d,
; CHECK-GI-NEXT: mov d0, v2.d[1]
; CHECK-GI-NEXT: mov d1, v3.d[1]
; CHECK-GI-NEXT: fcsel d2, d2, d3, mi
-; CHECK-GI-NEXT: fmov x8, d2
; CHECK-GI-NEXT: fcsel d3, d0, d1, mi
-; CHECK-GI-NEXT: ldp q5, q0, [sp, #64] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: mov d4, v5.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d5, mi
-; CHECK-GI-NEXT: fmov x9, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d3
-; CHECK-GI-NEXT: fcsel d2, d1, d4, mi
-; CHECK-GI-NEXT: mov v1.d[0], x9
-; CHECK-GI-NEXT: fmov x9, d2
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
+; CHECK-GI-NEXT: mov d4, v0.d[1]
+; CHECK-GI-NEXT: mov d5, v1.d[1]
+; CHECK-GI-NEXT: fcsel d1, d0, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v2.d[0]
+; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
+; CHECK-GI-NEXT: fcsel d2, d4, d5, mi
+; CHECK-GI-NEXT: mov v0.d[1], v3.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
; CHECK-GI-NEXT: add sp, sp, #112
; CHECK-GI-NEXT: ret
entry:
@@ -574,29 +568,23 @@ define <3 x fp128> @v3f128_fp128(<3 x fp128> %a, <3 x fp128> %b, <3 x fp128> %d,
; CHECK-GI-NEXT: fcsel d4, d4, d5, mi
; CHECK-GI-NEXT: mov d2, v7.d[1]
; CHECK-GI-NEXT: mov d3, v6.d[1]
-; CHECK-GI-NEXT: fmov x8, d4
; CHECK-GI-NEXT: fcsel d5, d0, d1, mi
; CHECK-GI-NEXT: cmp w20, #0
-; CHECK-GI-NEXT: fcsel d1, d7, d6, mi
-; CHECK-GI-NEXT: ldp q7, q0, [sp, #128] // 32-byte Folded Reload
; CHECK-GI-NEXT: fcsel d3, d2, d3, mi
+; CHECK-GI-NEXT: ldp q2, q0, [sp, #128] // 32-byte Folded Reload
+; CHECK-GI-NEXT: fcsel d1, d7, d6, mi
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d6, v7.d[1]
-; CHECK-GI-NEXT: fcsel d7, d0, d7, mi
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: fmov x9, d7
-; CHECK-GI-NEXT: fcsel d4, d2, d6, mi
-; CHECK-GI-NEXT: mov v1.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d5
-; CHECK-GI-NEXT: mov v2.d[0], x9
-; CHECK-GI-NEXT: fmov x9, d3
-; CHECK-GI-NEXT: fmov x10, d4
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
-; CHECK-GI-NEXT: mov v2.d[1], x10
+; CHECK-GI-NEXT: mov d6, v0.d[1]
+; CHECK-GI-NEXT: mov d7, v2.d[1]
+; CHECK-GI-NEXT: fcsel d2, d0, d2, mi
+; CHECK-GI-NEXT: mov v0.d[0], v4.d[0]
+; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
+; CHECK-GI-NEXT: mov v2.d[0], v2.d[0]
+; CHECK-GI-NEXT: fcsel d4, d6, d7, mi
+; CHECK-GI-NEXT: mov v0.d[1], v5.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v3.d[0]
+; CHECK-GI-NEXT: mov v2.d[1], v4.d[0]
; CHECK-GI-NEXT: add sp, sp, #192
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index 099a5732992d5..7d527f6b6464e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -968,56 +968,51 @@ define i32 @test_signed_f128_i32(fp128 %f) {
;
; CHECK-GI-LABEL: test_signed_f128_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #64
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
+; CHECK-GI-NEXT: sub sp, sp, #80
+; CHECK-GI-NEXT: str d8, [sp, #48] // 8-byte Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -24
-; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: .cfi_offset b8, -32
; CHECK-GI-NEXT: adrp x8, .LCPI30_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: fcsel d10, d0, d1, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d2, x8
; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d2, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d8, [sp, #48] // 8-byte Reload
; CHECK-GI-NEXT: csel w0, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: add sp, sp, #64
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: add sp, sp, #80
; CHECK-GI-NEXT: ret
%x = call i32 @llvm.fptosi.sat.i32.f128(fp128 %f)
ret i32 %x
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index f97fae9dff039..767f63a7c65a7 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -517,57 +517,52 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v1f128_v1i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #64
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
+; CHECK-GI-NEXT: sub sp, sp, #80
+; CHECK-GI-NEXT: str d8, [sp, #48] // 8-byte Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -24
-; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: .cfi_offset b8, -32
; CHECK-GI-NEXT: adrp x8, .LCPI14_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: fcsel d10, d0, d1, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d2, x8
; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d2, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d8, [sp, #48] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: add sp, sp, #64
+; CHECK-GI-NEXT: add sp, sp, #80
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f)
ret <1 x i32> %x
@@ -641,95 +636,92 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #144
+; CHECK-GI-NEXT: str d10, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #104] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #120] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: .cfi_offset b8, -40
-; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: .cfi_offset b9, -40
+; CHECK-GI-NEXT: .cfi_offset b10, -48
; CHECK-GI-NEXT: adrp x8, .LCPI15_2
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
-; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: str q2, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d10, x8
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d11, d0, d10, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
-; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
-; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d10, d0, d10, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #120] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #104] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #144
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -822,126 +814,119 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #160
-; CHECK-GI-NEXT: str d12, [sp, #80] // 8-byte Spill
-; CHECK-GI-NEXT: stp d11, d10, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x21, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
+; CHECK-GI-NEXT: sub sp, sp, #176
+; CHECK-GI-NEXT: str d10, [sp, #112] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x21, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 176
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: .cfi_offset b8, -40
; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
-; CHECK-GI-NEXT: .cfi_offset b12, -80
+; CHECK-GI-NEXT: .cfi_offset b10, -64
; CHECK-GI-NEXT: adrp x8, .LCPI16_2
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: str q2, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q2, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d11, d0, d9, gt
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI16_1
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI16_0]
-; CHECK-GI-NEXT: fcsel d1, d11, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d12
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d9, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d9, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr d12, [sp, #80] // 8-byte Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #112] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #128] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w21
-; CHECK-GI-NEXT: ldp x30, x21, [sp, #128] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #144] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: add sp, sp, #160
+; CHECK-GI-NEXT: add sp, sp, #176
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -1056,14 +1041,13 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #176
-; CHECK-GI-NEXT: str d12, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp d11, d10, [sp, #104] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #120] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #136] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 176
+; CHECK-GI-NEXT: sub sp, sp, #192
+; CHECK-GI-NEXT: str d10, [sp, #128] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #136] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #152] // 8-byte Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 192
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
@@ -1072,140 +1056,135 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: .cfi_offset b8, -48
; CHECK-GI-NEXT: .cfi_offset b9, -56
; CHECK-GI-NEXT: .cfi_offset b10, -64
-; CHECK-GI-NEXT: .cfi_offset b11, -72
-; CHECK-GI-NEXT: .cfi_offset b12, -80
; CHECK-GI-NEXT: adrp x8, .LCPI17_2
-; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q0, q1, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
-; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: stp q1, q3, [sp, #64] // 32-byte Folded Spill
+; CHECK-GI-NEXT: str q2, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: stp q1, q3, [sp, #96] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d11, d0, d9, gt
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI17_0]
-; CHECK-GI-NEXT: fcsel d1, d11, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d12
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q4, q1, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v4.d[1]
-; CHECK-GI-NEXT: fcsel d11, d4, d8, gt
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d12
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #96] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w22, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d9, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d9, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #136] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #152] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #120] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d12, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #136] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #128] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w21
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #104] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w22
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: add sp, sp, #176
+; CHECK-GI-NEXT: add sp, sp, #192
; CHECK-GI-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x
@@ -5157,101 +5136,96 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: str d12, [sp, #64] // 8-byte Spill
-; CHECK-GI-NEXT: stp d11, d10, [sp, #72] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #88] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #104] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #160
+; CHECK-GI-NEXT: stp d11, d10, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #128] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -24
-; CHECK-GI-NEXT: .cfi_offset b8, -32
-; CHECK-GI-NEXT: .cfi_offset b9, -40
-; CHECK-GI-NEXT: .cfi_offset b10, -48
-; CHECK-GI-NEXT: .cfi_offset b11, -56
-; CHECK-GI-NEXT: .cfi_offset b12, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
-; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: str q2, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #8521215115264 // =0x7c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d10, x8
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d11, d0, d10, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
-; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: mov x8, #280925220896768 // =0xff8000000000
-; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: movk x8, #17391, lsl #48
-; CHECK-GI-NEXT: fmov d12, x8
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: fmov d10, x8
; CHECK-GI-NEXT: mov x8, #-264432546480129 // =0xffff0f7fffffffff
; CHECK-GI-NEXT: movk x8, #17360, lsl #48
-; CHECK-GI-NEXT: fcsel d0, d9, d12, mi
-; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d11, x8
+; CHECK-GI-NEXT: fcsel d0, d0, d10, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d11, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfdi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x20, xzr, x19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d8, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d8
-; CHECK-GI-NEXT: fcsel d10, d0, d10, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d8, d12, mi
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d10, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d11, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfdi
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov d0, x20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #104] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #128] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #88] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d12, [sp, #64] // 8-byte Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #72] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #96] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
index 9c9f91ec26008..038ac9f97e6ea 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
@@ -784,43 +784,38 @@ define i32 @test_unsigned_f128_i32(fp128 %f) {
; CHECK-GI-LABEL: test_unsigned_f128_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d8, [sp, #32] // 8-byte Spill
; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset b8, -16
-; CHECK-GI-NEXT: .cfi_offset b9, -24
-; CHECK-GI-NEXT: .cfi_offset b10, -32
; CHECK-GI-NEXT: adrp x8, .LCPI30_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI30_0
; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
-; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: ldr d8, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: b __fixunstfsi
%x = call i32 @llvm.fptoui.sat.i32.f128(fp128 %f)
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index eabe580d7f6d5..2f43fe75e449a 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -474,45 +474,40 @@ define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-GI-LABEL: test_unsigned_v1f128_v1i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d8, [sp, #32] // 8-byte Spill
; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset b8, -16
-; CHECK-GI-NEXT: .cfi_offset b9, -24
-; CHECK-GI-NEXT: .cfi_offset b10, -32
; CHECK-GI-NEXT: adrp x8, .LCPI14_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
-; CHECK-GI-NEXT: fmov s0, w0
; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldr d8, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: fmov s0, w0
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f128.v1i32(<1 x fp128> %f)
@@ -571,76 +566,70 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
+; CHECK-GI-NEXT: sub sp, sp, #112
+; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w30, -16
; CHECK-GI-NEXT: .cfi_offset b8, -24
; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -40
-; CHECK-GI-NEXT: .cfi_offset b11, -48
; CHECK-GI-NEXT: adrp x8, .LCPI15_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
-; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q2, q1, [sp, #48] // 32-byte Folded Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
-; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #96
+; CHECK-GI-NEXT: add sp, sp, #112
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -711,100 +700,94 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #144
+; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #112] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: .cfi_offset b8, -40
; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
; CHECK-GI-NEXT: adrp x8, .LCPI16_2
-; CHECK-GI-NEXT: stp q1, q0, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
-; CHECK-GI-NEXT: stp q1, q2, [sp, #32] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q1, q2, [sp, #64] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI16_1
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI16_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q3, q1, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v3.d[1]
-; CHECK-GI-NEXT: fcsel d10, d3, d8, gt
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #112] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w0
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #144
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -893,128 +876,122 @@ define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #144
-; CHECK-GI-NEXT: stp d11, d10, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x21, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
+; CHECK-GI-NEXT: sub sp, sp, #160
+; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x21, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: .cfi_offset b8, -40
; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
; CHECK-GI-NEXT: adrp x8, .LCPI17_2
-; CHECK-GI-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q1, q2, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
-; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: str q3, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: str q3, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #96] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI17_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: mov w21, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q4, q1, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v4.d[1]
-; CHECK-GI-NEXT: fcsel d10, d4, d8, gt
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w21
-; CHECK-GI-NEXT: ldp x30, x21, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #128] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w0
-; CHECK-GI-NEXT: add sp, sp, #144
+; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x
@@ -4181,79 +4158,76 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: str d10, [sp, #80] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w30, -16
; CHECK-GI-NEXT: .cfi_offset b8, -24
; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -40
-; CHECK-GI-NEXT: .cfi_offset b11, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -48
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
-; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q2, q1, [sp, #48] // 32-byte Folded Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
-; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: mov x8, #281200098803712 // =0xffc000000000
-; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: movk x8, #17391, lsl #48
-; CHECK-GI-NEXT: fmov d11, x8
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: mov x8, #-264157668573185 // =0xffff0fbfffffffff
; CHECK-GI-NEXT: movk x8, #17360, lsl #48
-; CHECK-GI-NEXT: fcsel d0, d9, d11, mi
-; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d10, x8
+; CHECK-GI-NEXT: fcsel d0, d0, d9, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfdi
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d8, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d8
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d11, mi
-; CHECK-GI-NEXT: fcsel d1, d8, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d9, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: fmov d0, x19
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #80] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.d[1], x0
-; CHECK-GI-NEXT: add sp, sp, #96
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/phi.ll b/llvm/test/CodeGen/AArch64/phi.ll
index 02842c04bf7bf..a7ca9ed8a8165 100644
--- a/llvm/test/CodeGen/AArch64/phi.ll
+++ b/llvm/test/CodeGen/AArch64/phi.ll
@@ -274,10 +274,8 @@ define fp128 @tf128(i1 %c, ptr %p, fp128 %a, fp128 %b) {
; CHECK-GI-NEXT: .LBB9_2:
; CHECK-GI-NEXT: mov d2, v1.d[1]
; CHECK-GI-NEXT: .LBB9_3: // %e
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d2
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[0], v1.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v2.d[0]
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -1303,14 +1301,10 @@ define <2 x fp128> @tv2f128(i1 %c, ptr %p, <2 x fp128> %a, <2 x fp128> %b) {
; CHECK-GI-NEXT: mov d4, v3.d[1]
; CHECK-GI-NEXT: mov d5, v2.d[1]
; CHECK-GI-NEXT: .LBB44_3: // %e
-; CHECK-GI-NEXT: fmov x8, d2
-; CHECK-GI-NEXT: fmov x9, d3
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov v1.d[0], x9
-; CHECK-GI-NEXT: fmov x8, d5
-; CHECK-GI-NEXT: fmov x9, d4
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
+; CHECK-GI-NEXT: mov v0.d[0], v2.d[0]
+; CHECK-GI-NEXT: mov v1.d[0], v3.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v5.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
>From 1d2885d44e2fd228c079ac58e6e2804c94e03abe Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Fri, 2 Jan 2026 11:30:37 +0000
Subject: [PATCH 40/41] Modify type constructors to use wrapper constructor to
allow scalar fallback
---
llvm/include/llvm/CodeGen/TargetLowering.h | 2 +-
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 2 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 24 +++---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 79 +++++++++----------
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 2 +-
.../Target/AArch64/AArch64ISelLowering.cpp | 8 +-
.../AArch64/GISel/AArch64CallLowering.cpp | 11 +--
.../GISel/AArch64InstructionSelector.cpp | 4 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +-
.../GISel/AArch64PostLegalizerCombiner.cpp | 4 +-
.../GISel/AArch64PostLegalizerLowering.cpp | 8 +-
.../GISel/AArch64PreLegalizerCombiner.cpp | 2 +-
12 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 92df37765c4a1..1455e0c91d064 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -443,7 +443,7 @@ class LLVM_ABI TargetLoweringBase {
/// G_INSERT_VECTOR_ELT, G_EXTRACT_VECTOR_ELT,
/// G_INSERT_SUBVECTOR, and G_EXTRACT_SUBVECTOR
LLT getVectorIdxLLT(const DataLayout &DL) const {
- return LLT::integer(getVectorIdxWidth(DL));
+ return LLT::buildInteger(getVectorIdxWidth(DL));
}
/// Returns the type to be used for the EVL/AVL operand of VP nodes:
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 421050409f125..defe5ef801a99 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -1305,7 +1305,7 @@ void CallLowering::ValueHandler::copyArgumentMemory(
MemSize, DstAlign);
const LLT PtrTy = MRI.getType(DstPtr);
- const LLT SizeTy = LLT::integer(PtrTy.getSizeInBits());
+ const LLT SizeTy = LLT::buildInteger(PtrTy.getSizeInBits());
auto SizeConst = MIRBuilder.buildConstant(SizeTy, MemSize);
MIRBuilder.buildMemCpy(DstPtr, SrcPtr, SizeConst, *DstMMO, *SrcMMO);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index df26478380f04..eef6b63f37b6c 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -888,7 +888,7 @@ bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
auto Cst = getOrCreateVReg(
*ConstantInt::get(SValue.getType(), JTH.Last - JTH.First));
Cst = MIB.buildZExtOrTrunc(PtrScalarTy, Cst).getReg(0);
- auto Cmp = MIB.buildICmp(CmpInst::ICMP_UGT, LLT::integer(1), Sub, Cst);
+ auto Cmp = MIB.buildICmp(CmpInst::ICMP_UGT, LLT::buildInteger(1), Sub, Cst);
auto BrCond = MIB.buildBrCond(Cmp.getReg(0), *JT.Default);
@@ -919,7 +919,7 @@ void IRTranslator::emitSwitchCase(SwitchCG::CaseBlock &CB,
return;
}
- const LLT i1Ty = LLT::integer(1);
+ const LLT i1Ty = LLT::buildInteger(1);
// Build the compare.
if (!CB.CmpMHS) {
const auto *CI = dyn_cast<ConstantInt>(CB.CmpRHS);
@@ -1131,8 +1131,8 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
if (!B.FallthroughUnreachable) {
// Conditional branch to the default block.
auto RangeCst = MIB.buildConstant(SwitchOpTy, B.Range);
- auto RangeCmp = MIB.buildICmp(CmpInst::Predicate::ICMP_UGT, LLT::integer(1),
- RangeSub, RangeCst);
+ auto RangeCmp = MIB.buildICmp(CmpInst::Predicate::ICMP_UGT,
+ LLT::buildInteger(1), RangeSub, RangeCst);
MIB.buildBrCond(RangeCmp, *B.Default);
}
@@ -1157,16 +1157,16 @@ void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB,
// would need to be to shift a 1 bit in that position.
auto MaskTrailingZeros =
MIB.buildConstant(SwitchTy, llvm::countr_zero(B.Mask));
- Cmp = MIB.buildICmp(ICmpInst::ICMP_EQ, LLT::integer(1), Reg,
+ Cmp = MIB.buildICmp(ICmpInst::ICMP_EQ, LLT::buildInteger(1), Reg,
MaskTrailingZeros)
.getReg(0);
} else if (PopCount == BB.Range) {
// There is only one zero bit in the range, test for it directly.
auto MaskTrailingOnes =
MIB.buildConstant(SwitchTy, llvm::countr_one(B.Mask));
- Cmp =
- MIB.buildICmp(CmpInst::ICMP_NE, LLT::integer(1), Reg, MaskTrailingOnes)
- .getReg(0);
+ Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::buildInteger(1), Reg,
+ MaskTrailingOnes)
+ .getReg(0);
} else {
// Make desired shift.
auto CstOne = MIB.buildConstant(SwitchTy, 1);
@@ -1176,7 +1176,7 @@ void IRTranslator::emitBitTestCase(SwitchCG::BitTestBlock &BB,
auto CstMask = MIB.buildConstant(SwitchTy, B.Mask);
auto AndOp = MIB.buildAnd(SwitchTy, SwitchVal, CstMask);
auto CstZero = MIB.buildConstant(SwitchTy, 0);
- Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::integer(1), AndOp, CstZero)
+ Cmp = MIB.buildICmp(CmpInst::ICMP_NE, LLT::buildInteger(1), AndOp, CstZero)
.getReg(0);
}
@@ -1723,7 +1723,7 @@ bool IRTranslator::translateMemFunc(const CallInst &CI,
SrcRegs.push_back(SrcReg);
}
- LLT SizeTy = LLT::integer(MinPtrSize);
+ LLT SizeTy = LLT::buildInteger(MinPtrSize);
// The size operand should be the minimum of the pointer sizes.
Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1];
@@ -4073,8 +4073,8 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
}
// Perform the comparison.
- auto Cmp =
- CurBuilder->buildICmp(CmpInst::ICMP_NE, LLT::integer(1), Guard, GuardVal);
+ auto Cmp = CurBuilder->buildICmp(CmpInst::ICMP_NE, LLT::buildInteger(1),
+ Guard, GuardVal);
// If the guard/stackslot do not equal, branch to failure MBB.
CurBuilder->buildBrCond(Cmp, *SPD.getFailureMBB());
// Otherwise branch to success MBB.
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 6f3d1f52c6f69..4339b897414e5 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1178,7 +1178,7 @@ LegalizerHelper::createFCMPLibcall(MachineIRBuilder &MIRBuilder,
const CmpInst::Predicate ICmpPred,
const DstOp &Res) -> Register {
// FCMP libcall always returns an i32, and needs an ICMP with #0.
- constexpr LLT TempLLT = LLT::integer(32);
+ LLT TempLLT = LLT::buildInteger(32);
Register Temp = MRI.createGenericVirtualRegister(TempLLT);
// Generate libcall, holding result in Temp
const auto Status = createLibcall(
@@ -4264,8 +4264,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerLoad(GAnyLoad &LoadMI) {
auto LargeLoad = MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, AnyExtTy,
PtrReg, *LargeMMO);
- auto OffsetCst = MIRBuilder.buildConstant(
- OffsetCstRes, LargeSplitSize / 8);
+ auto OffsetCst = MIRBuilder.buildConstant(OffsetCstRes, LargeSplitSize / 8);
Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
auto SmallPtr = MIRBuilder.buildObjectPtrOffset(PtrAddReg, PtrReg, OffsetCst);
auto SmallLoad = MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), AnyExtTy,
@@ -4402,7 +4401,7 @@ LegalizerHelper::scalarizeVectorBooleanStore(GStore &StoreMI) {
// We need to build an integer scalar of the vector bit pattern.
// It's not legal for us to add padding when storing a vector.
unsigned NumBits = MemTy.getSizeInBits();
- LLT IntTy = LLT::integer(NumBits);
+ LLT IntTy = LLT::buildInteger(NumBits);
auto CurrVal = MIRBuilder.buildConstant(IntTy, 0);
LLT IdxTy = TLI.getVectorIdxLLT(MF.getDataLayout());
@@ -4588,15 +4587,15 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
case TargetOpcode::G_FNEG: {
auto [Res, ResTy, SubByReg, SubByRegTy] = MI.getFirst2RegLLTs();
LLT TyInt =
- ResTy.changeElementType(LLT::integer(ResTy.getScalarSizeInBits()));
+ ResTy.changeElementType(LLT::buildInteger(ResTy.getScalarSizeInBits()));
Register castedSubByReg = SubByReg;
if (!(SubByRegTy.getScalarType().isAnyScalar() ||
SubByRegTy.getScalarType().isInteger()))
castedSubByReg =
MIRBuilder
- .buildBitcast(SubByRegTy.changeElementType(
- LLT::integer(SubByRegTy.getScalarSizeInBits())),
+ .buildBitcast(SubByRegTy.changeElementType(LLT::buildInteger(
+ SubByRegTy.getScalarSizeInBits())),
SubByReg)
.getReg(0);
@@ -4605,7 +4604,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
if (ResTy != TyInt) {
Register NewDst =
- MIRBuilder.buildXor(TyInt, castedSubByReg, SignMask).getReg(0);
+ MIRBuilder.buildXor(TyInt, castedSubByReg, SignMask).getReg(0);
MIRBuilder.buildBitcast(Res, NewDst);
} else
MIRBuilder.buildXor(Res, castedSubByReg, SignMask).getReg(0);
@@ -5476,7 +5475,7 @@ LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
return UnableToLegalize;
LLT PtrTy = MRI.getType(AddrReg);
- const LLT OffsetTy = LLT::integer(PtrTy.getSizeInBits());
+ const LLT OffsetTy = LLT::buildInteger(PtrTy.getSizeInBits());
unsigned TotalSize = ValTy.getSizeInBits();
@@ -8244,8 +8243,8 @@ LegalizerHelper::lowerU64ToF64BitFloatOps(MachineInstr &MI) {
static LegalizerHelper::LegalizeResult
loweri64tof16ITOFP(MachineInstr &MI, Register Dst, LLT DstTy, Register Src,
LLT SrcTy, MachineIRBuilder &MIRBuilder) {
- auto DstFpTy =
- SrcTy.changeElementType(LLT::floatIEEE(SrcTy.getScalarSizeInBits()));
+ auto DstFpTy = SrcTy.changeElementType(
+ LLT::buildFloatingIEEE(SrcTy.getScalarSizeInBits()));
auto M1 = MI.getOpcode() == TargetOpcode::G_UITOFP
? MIRBuilder.buildUITOFP(DstFpTy, Src)
: MIRBuilder.buildSITOFP(DstFpTy, Src);
@@ -8289,9 +8288,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) {
LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) {
auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
- const LLT I64 = LLT::integer(64);
- const LLT I32 = LLT::integer(32);
- const LLT I1 = LLT::integer(1);
+ const LLT I64 = LLT::buildInteger(64);
+ const LLT I32 = LLT::buildInteger(32);
+ const LLT I1 = LLT::buildInteger(1);
if (SrcTy == I1) {
auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
@@ -8471,13 +8470,13 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
if (AreExactFloatBounds) {
// Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat.
auto MaxC = MIRBuilder.buildFConstant(SrcTy, MinFloat);
- auto MaxP =
- MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::integer(1), Src, MaxC);
+ auto MaxP = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::buildInteger(1),
+ Src, MaxC);
auto Max = MIRBuilder.buildSelect(SrcTy, MaxP, Src, MaxC);
// Clamp by MaxFloat from above. NaN cannot occur.
auto MinC = MIRBuilder.buildFConstant(SrcTy, MaxFloat);
- auto MinP = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, LLT::integer(1), Max,
- MinC, MachineInstr::FmNoNans);
+ auto MinP = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, LLT::buildInteger(1),
+ Max, MinC, MachineInstr::FmNoNans);
auto Min =
MIRBuilder.buildSelect(SrcTy, MinP, Max, MinC, MachineInstr::FmNoNans);
// Convert clamped value to integer. In the unsigned case we're done,
@@ -8491,7 +8490,7 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
// Otherwise, select 0 if Src is NaN.
auto FpToInt = MIRBuilder.buildFPTOSI(DstTy, Min);
auto IsZero =
- MIRBuilder.buildFCmp(CmpInst::FCMP_UNO, LLT::integer(1), Src, Src);
+ MIRBuilder.buildFCmp(CmpInst::FCMP_UNO, LLT::buildInteger(1), Src, Src);
MIRBuilder.buildSelect(Dst, IsZero, MIRBuilder.buildConstant(DstTy, 0),
FpToInt);
MI.eraseFromParent();
@@ -8506,12 +8505,12 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
// If Src ULT MinFloat, select MinInt. In particular, this also selects
// MinInt if Src is NaN.
- auto ULT = MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, LLT::integer(1), Src,
+ auto ULT = MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, LLT::buildInteger(1), Src,
MIRBuilder.buildFConstant(SrcTy, MinFloat));
auto Max = MIRBuilder.buildSelect(
DstTy, ULT, MIRBuilder.buildConstant(DstTy, MinInt), FpToInt);
// If Src OGT MaxFloat, select MaxInt.
- auto OGT = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::integer(1), Src,
+ auto OGT = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::buildInteger(1), Src,
MIRBuilder.buildFConstant(SrcTy, MaxFloat));
// In the unsigned case we are done, because we mapped NaN to MinInt, which
@@ -8527,7 +8526,7 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
auto Min = MIRBuilder.buildSelect(
DstTy, OGT, MIRBuilder.buildConstant(DstTy, MaxInt), Max);
auto IsZero =
- MIRBuilder.buildFCmp(CmpInst::FCMP_UNO, LLT::integer(1), Src, Src);
+ MIRBuilder.buildFCmp(CmpInst::FCMP_UNO, LLT::buildInteger(1), Src, Src);
MIRBuilder.buildSelect(Dst, IsZero, MIRBuilder.buildConstant(DstTy, 0), Min);
MI.eraseFromParent();
return Legalized;
@@ -8690,7 +8689,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) {
auto [Dst, Src0, Src1] = MI.getFirst3Regs();
const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
- LLT CmpType = MRI.getType(Dst).changeElementType(LLT::integer(1));
+ LLT CmpType = MRI.getType(Dst).changeElementType(LLT::buildInteger(1));
auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
@@ -8754,9 +8753,9 @@ LegalizerHelper::lowerFCopySign(MachineInstr &MI) {
const int Src1Size = Src1Ty.getScalarSizeInBits();
LLT DstIntTy =
- DstTy.changeElementType(LLT::integer(DstTy.getScalarSizeInBits()));
- LLT Src0IntTy = Src0Ty.changeElementType(LLT::integer(Src0Size));
- LLT Src1IntTy = Src1Ty.changeElementType(LLT::integer(Src1Size));
+ DstTy.changeElementType(LLT::buildInteger(DstTy.getScalarSizeInBits()));
+ LLT Src0IntTy = Src0Ty.changeElementType(LLT::buildInteger(Src0Size));
+ LLT Src1IntTy = Src1Ty.changeElementType(LLT::buildInteger(Src1Size));
Register Src0Int = Src0;
Register Src1Int = Src1;
@@ -10096,7 +10095,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
MI.getFirst4RegLLTs();
LLT Op1TyInt =
- Op1Ty.changeElementType(LLT::integer(Op1Ty.getScalarSizeInBits()));
+ Op1Ty.changeElementType(LLT::buildInteger(Op1Ty.getScalarSizeInBits()));
bool IsEltPtr = DstTy.isPointerOrPointerVector();
if (IsEltPtr) {
@@ -10145,8 +10144,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
if (!(Op2Ty.getScalarType().isAnyScalar() ||
Op2Ty.getScalarType().isInteger()))
Op2Reg = MIRBuilder
- .buildBitcast(Op2Ty.changeElementType(
- LLT::integer(Op2Ty.getScalarSizeInBits())),
+ .buildBitcast(Op2Ty.changeElementType(LLT::buildInteger(
+ Op2Ty.getScalarSizeInBits())),
Op2Reg)
.getReg(0);
@@ -10280,13 +10279,13 @@ LegalizerHelper::lowerAbsDiffToMinMax(MachineInstr &MI) {
LegalizerHelper::LegalizeResult LegalizerHelper::lowerFAbs(MachineInstr &MI) {
auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
LLT TyInt =
- DstTy.changeElementType(LLT::integer(DstTy.getScalarSizeInBits()));
+ DstTy.changeElementType(LLT::buildInteger(DstTy.getScalarSizeInBits()));
Register castedSrc = SrcReg;
if (!(SrcTy.getScalarType().isAnyScalar() ||
SrcTy.getScalarType().isInteger()))
castedSrc = MIRBuilder
- .buildBitcast(SrcTy.changeElementType(LLT::integer(
+ .buildBitcast(SrcTy.changeElementType(LLT::buildInteger(
SrcTy.getScalarSizeInBits())),
SrcReg)
.getReg(0);
@@ -10295,20 +10294,20 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFAbs(MachineInstr &MI) {
// Reset sign bit
Register NewDst =
MIRBuilder
- .buildAnd(
- TyInt, castedSrc,
- MIRBuilder.buildConstant(
- TyInt, APInt::getSignedMaxValue(DstTy.getScalarSizeInBits())))
+ .buildAnd(TyInt, castedSrc,
+ MIRBuilder.buildConstant(
+ TyInt, APInt::getSignedMaxValue(
+ DstTy.getScalarSizeInBits())))
.getReg(0);
MIRBuilder.buildBitcast(DstReg, NewDst);
} else
MIRBuilder
- .buildAnd(
- DstReg, castedSrc,
- MIRBuilder.buildConstant(
- TyInt, APInt::getSignedMaxValue(DstTy.getScalarSizeInBits())))
- .getReg(0);
+ .buildAnd(
+ DstReg, castedSrc,
+ MIRBuilder.buildConstant(
+ TyInt, APInt::getSignedMaxValue(DstTy.getScalarSizeInBits())))
+ .getReg(0);
MI.eraseFromParent();
return Legalized;
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 63c9ada9b059d..51f371d4a4108 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -787,7 +787,7 @@ MachineInstrBuilder MachineIRBuilder::buildShuffleSplat(const DstOp &Res,
assert(Src.getLLTTy(*getMRI()) == DstTy.getElementType() &&
"Expected Src to match Dst elt ty");
auto UndefVec = buildUndef(DstTy);
- auto Zero = buildConstant(LLT::integer(64), 0);
+ auto Zero = buildConstant(LLT::buildInteger(64), 0);
auto InsElt = buildInsertVectorElement(DstTy, UndefVec, Src, Zero);
SmallVector<int, 16> ZeroMask(DstTy.getNumElements());
return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 20dc0b020fb91..b80a37a80c518 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18735,13 +18735,13 @@ LLT AArch64TargetLowering::getOptimalMemOpLLT(
if (CanUseNEON && Op.isMemset() && !IsSmallMemset &&
AlignmentIsAcceptable(MVT::v2i64, Align(16)))
- return LLT::fixed_vector(2, LLT::integer(64));
+ return LLT::fixed_vector(2, LLT::buildInteger(64));
if (CanUseFP && !IsSmallMemset && AlignmentIsAcceptable(MVT::f128, Align(16)))
- return LLT::floatIEEE(128);
+ return LLT::buildFloatingIEEE(128);
if (Op.size() >= 8 && AlignmentIsAcceptable(MVT::i64, Align(8)))
- return LLT::integer(64);
+ return LLT::buildInteger(64);
if (Op.size() >= 4 && AlignmentIsAcceptable(MVT::i32, Align(4)))
- return LLT::integer(32);
+ return LLT::buildInteger(32);
return LLT();
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index e975932763e0e..269f7ec95a93e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -257,7 +257,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
ISD::ArgFlagsTy Flags) override {
MachineFunction &MF = MIRBuilder.getMF();
LLT p0 = LLT::pointer(0, 64);
- LLT s64 = LLT::integer(64);
+ LLT s64 = LLT::buildInteger(64);
if (IsTailCall) {
assert(!Flags.isByVal() && "byval unhandled with tail calls");
@@ -444,7 +444,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
auto &Flags = CurArgInfo.Flags[0];
if (MRI.getType(CurVReg).getSizeInBits() == TypeSize::getFixed(1) &&
!Flags.isSExt() && !Flags.isZExt()) {
- CurVReg = MIRBuilder.buildZExt(LLT::integer(8), CurVReg).getReg(0);
+ CurVReg = MIRBuilder.buildZExt(LLT::buildInteger(8), CurVReg).getReg(0);
} else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
1) {
// Some types will need extending as specified by the CC.
@@ -611,7 +611,7 @@ void AArch64CallLowering::saveVarArgRegisters(
bool IsWin64CC = Subtarget.isCallingConvWin64(CCInfo.getCallingConv(),
MF.getFunction().isVarArg());
const LLT p0 = LLT::pointer(0, 64);
- const LLT s64 = LLT::integer(64);
+ const LLT s64 = LLT::buildInteger(64);
unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
unsigned NumVariadicGPRArgRegs = GPRArgRegs.size() - FirstVariadicGPR + 1;
@@ -735,7 +735,8 @@ bool AArch64CallLowering::lowerFormalArguments(
if (!Flags.isZExt() && !Flags.isSExt()) {
// Lower i1 argument as i8, and insert AssertZExt + Trunc later.
Register OrigReg = OrigArg.Regs[0];
- Register WideReg = MRI.createGenericVirtualRegister(LLT::integer(8));
+ Register WideReg =
+ MRI.createGenericVirtualRegister(LLT::buildInteger(8));
OrigArg.Regs[0] = WideReg;
BoolArgs.push_back({OrigReg, WideReg});
}
@@ -1341,7 +1342,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// We cannot use a ZExt ArgInfo flag here, because it will
// zero-extend the argument to i32 instead of just i8.
OutArg.Regs[0] =
- MIRBuilder.buildZExt(LLT::integer(8), OutArg.Regs[0]).getReg(0);
+ MIRBuilder.buildZExt(LLT::buildInteger(8), OutArg.Regs[0]).getReg(0);
LLVMContext &Ctx = MF.getFunction().getContext();
OutArg.Ty = Type::getInt8Ty(Ctx);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index b8059b111a8bc..2e1cc8b53d972 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2236,8 +2236,8 @@ bool AArch64InstructionSelector::convertPtrAddToAdd(
return false;
const LLT CastPtrTy = PtrTy.isVector()
- ? LLT::fixed_vector(2, LLT::integer(64))
- : LLT::integer(64);
+ ? LLT::fixed_vector(2, LLT::buildInteger(64))
+ : LLT::buildInteger(64);
auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg);
// Set regbanks on the registers.
if (PtrTy.isVector())
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index c841d37428120..75e0a7f456818 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -2383,7 +2383,7 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
- LLT i64 = LLT::integer(64);
+ LLT i64 = LLT::buildInteger(64);
auto Addr = MI.getOperand(1).getReg();
auto DesiredI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(2));
auto NewI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(3));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 7275b60bbed9d..fa3bdf185007d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -223,7 +223,7 @@ bool matchAArch64MulConstCombine(
return false;
ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
- auto Shift = B.buildConstant(LLT::integer(64), ShiftAmt);
+ auto Shift = B.buildConstant(LLT::buildInteger(64), ShiftAmt);
auto ShiftedVal = B.buildShl(Ty, LHS, Shift);
Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS;
@@ -239,7 +239,7 @@ bool matchAArch64MulConstCombine(
// Shift the result.
if (TrailingZeroes) {
B.buildShl(DstReg, Res,
- B.buildConstant(LLT::integer(64), TrailingZeroes));
+ B.buildConstant(LLT::buildInteger(64), TrailingZeroes));
return;
}
B.buildCopy(DstReg, Res.getReg(0));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 313185786d992..e42ef1e13f094 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -543,9 +543,9 @@ void applyINS(MachineInstr &MI, MachineRegisterInfo &MRI,
Register DstVec, SrcVec;
int DstLane, SrcLane;
std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo;
- auto SrcCst = Builder.buildConstant(LLT::integer(64), SrcLane);
+ auto SrcCst = Builder.buildConstant(LLT::buildInteger(64), SrcLane);
auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst);
- auto DstCst = Builder.buildConstant(LLT::integer(64), DstLane);
+ auto DstCst = Builder.buildConstant(LLT::buildInteger(64), DstLane);
Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst);
MI.eraseFromParent();
}
@@ -768,7 +768,7 @@ void applyStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI,
auto *Merge = getOpcodeDef<GMerge>(ValReg, MRI);
auto BV =
- MIB.buildBuildVector(LLT::fixed_vector(2, LLT::integer(64)),
+ MIB.buildBuildVector(LLT::fixed_vector(2, LLT::buildInteger(64)),
{Merge->getSourceReg(0), Merge->getSourceReg(1)})
.getReg(0);
MI.getOperand(0).setReg(BV);
@@ -1173,7 +1173,7 @@ void applyLowerBuildToInsertVecElt(MachineInstr &MI, MachineRegisterInfo &MRI,
Register SrcReg = GBuildVec->getSourceReg(I);
if (mi_match(SrcReg, MRI, m_GImplicitDef()))
continue;
- auto IdxReg = B.buildConstant(LLT::integer(64), I);
+ auto IdxReg = B.buildConstant(LLT::buildInteger(64), I);
DstReg =
B.buildInsertVectorElement(DstTy, DstReg, SrcReg, IdxReg).getReg(0);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 4d973ed572307..770ce70bd1a44 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -498,7 +498,7 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
unsigned MidScalarSize = MainTy.getScalarSizeInBits() * 2;
LLT MidScalarLLT =
MainTy.changeElementSize(MidScalarSize).changeElementCount(1);
- Register ZeroReg = B.buildConstant(LLT::integer(64), 0).getReg(0);
+ Register ZeroReg = B.buildConstant(LLT::buildInteger(64), 0).getReg(0);
for (unsigned I = 0; I < WorkingRegisters.size(); I++) {
// If the number of elements is too small to build an instruction, extend
// its size before applying addlv
>From 4e3fbb256e7344f0ac14ab51404a97e8a3bf7ffa Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 21 Jan 2026 11:13:13 +0000
Subject: [PATCH 41/41] Update tests
---
.../AArch64/GlobalISel/combine-unmerge.mir | 8 +-
.../AArch64/GlobalISel/legalize-fcopysign.mir | 10 +-
.../GlobalISel/legalize-fp-arith-fp16.mir | 9 +-
.../AMDGPU/GlobalISel/legalize-fcopysign.mir | 216 +++++++++---------
.../MIR/AArch64/deactivation-symbols.mir | 2 +-
.../print-parse-overloaded-intrinsics.mir | 8 +-
.../GlobalISel/LegalizerHelperTest.cpp | 52 ++---
.../CodeGen/GlobalISel/LegalizerTest.cpp | 8 +-
8 files changed, 155 insertions(+), 158 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
index e5e6517f6391f..f427f8648a301 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
@@ -266,10 +266,10 @@ name: test_combine_unmerge_fpcst
body: |
bb.1:
; CHECK-LABEL: name: test_combine_unmerge_fpcst
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4000
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4400
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: $h0 = COPY [[C]](s16)
; CHECK-NEXT: $h1 = COPY [[C1]](s16)
; CHECK-NEXT: $h2 = COPY [[C2]](s16)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
index 4f036d275b24d..3c1a6822e7428 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
@@ -22,9 +22,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[OR]](<2 x i32>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](<2 x s32>)
; CHECK-NEXT: %fcopysign:_(s32) = COPY [[UV]](s32)
; CHECK-NEXT: $s0 = COPY %fcopysign(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -55,9 +54,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C1]](i64), [[C1]](i64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = disjoint G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[OR]](<2 x i64>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = disjoint G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[OR]](<2 x s64>)
; CHECK-NEXT: %fcopysign:_(s64) = COPY [[UV]](s64)
; CHECK-NEXT: $d0 = COPY %fcopysign(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
index e3c0d4989fc2c..42538d58c87bf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
@@ -150,11 +150,10 @@ body: |
; NO-FP16: liveins: $h0
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %x:_(s16) = COPY $h0
- ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT %x(s16)
- ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -32768
- ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[ANYEXT]], [[C]]
- ; NO-FP16-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[XOR]](i32)
- ; NO-FP16-NEXT: %op:_(s16) = G_BITCAST [[TRUNC]](i16)
+ ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %x(s16)
+ ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT]], [[C]]
+ ; NO-FP16-NEXT: %op:_(s16) = G_TRUNC [[XOR]](s32)
; NO-FP16-NEXT: $h0 = COPY %op(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
index 60ccd20c095cd..1a7cad7886635 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
@@ -22,8 +22,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s16
@@ -37,8 +37,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s16
@@ -52,8 +52,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -79,8 +79,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY %2(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s32
; VI: liveins: $vgpr0, $vgpr1
@@ -91,8 +91,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY %2(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s32
; GFX9: liveins: $vgpr0, $vgpr1
@@ -103,8 +103,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_FCOPYSIGN %0, %1
@@ -126,8 +126,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; VI-LABEL: name: test_copysign_s64_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -138,8 +138,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; GFX9-LABEL: name: test_copysign_s64_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -150,8 +150,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_FCOPYSIGN %0, %1
@@ -176,8 +176,8 @@ body: |
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; VI-LABEL: name: test_copysign_s64_s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
@@ -191,8 +191,8 @@ body: |
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; GFX9-LABEL: name: test_copysign_s64_s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
@@ -206,8 +206,8 @@ body: |
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_FCOPYSIGN %0, %1
@@ -232,8 +232,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; SI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY %2(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s64
; VI: liveins: $vgpr0, $vgpr1_vgpr2
@@ -247,8 +247,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; VI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY %2(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s64
; GFX9: liveins: $vgpr0, $vgpr1_vgpr2
@@ -262,8 +262,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; GFX9-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2
%2:_(s32) = G_FCOPYSIGN %0, %1
@@ -289,8 +289,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s32
@@ -306,8 +306,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s32
@@ -323,8 +323,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -353,8 +353,8 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0 = COPY %3(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s16
; VI: liveins: $vgpr0, $vgpr1
@@ -369,8 +369,8 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0 = COPY %3(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s16
; GFX9: liveins: $vgpr0, $vgpr1
@@ -385,8 +385,8 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0 = COPY %3(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -414,8 +414,8 @@ body: |
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; VI-LABEL: name: test_copysign_s64_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
@@ -431,8 +431,8 @@ body: |
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; GFX9-LABEL: name: test_copysign_s64_s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
@@ -448,8 +448,8 @@ body: |
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -476,8 +476,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s64
@@ -493,8 +493,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s64
@@ -510,8 +510,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2
@@ -543,8 +543,8 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
- ; SI-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY %2(<2 x s16>)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
;
; VI-LABEL: name: test_copysign_v2s16_v2s16
; VI: liveins: $vgpr0, $vgpr1
@@ -562,8 +562,8 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
- ; VI-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY %2(<2 x s16>)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
;
; GFX9-LABEL: name: test_copysign_v2s16_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
@@ -576,8 +576,8 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY %2(<2 x s16>)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_FCOPYSIGN %0, %1
@@ -601,8 +601,8 @@ body: |
; SI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; SI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
;
; VI-LABEL: name: test_copysign_v2s32_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -615,8 +615,8 @@ body: |
; VI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; VI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
;
; GFX9-LABEL: name: test_copysign_v2s32_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -629,8 +629,8 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = G_FCOPYSIGN %0, %1
@@ -656,9 +656,9 @@ body: |
; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; SI-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; VI-LABEL: name: test_copysign_v2s64_v2s64
@@ -674,9 +674,9 @@ body: |
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; VI-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; GFX9-LABEL: name: test_copysign_v2s64_v2s64
@@ -692,9 +692,9 @@ body: |
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; GFX9-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
@@ -727,9 +727,9 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; SI-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; VI-LABEL: name: test_copysign_v2s64_v2s32
@@ -751,9 +751,9 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; VI-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; GFX9-LABEL: name: test_copysign_v2s64_v2s32
@@ -775,9 +775,9 @@ body: |
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; GFX9-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s32>) = COPY $vgpr4_vgpr5
@@ -811,8 +811,8 @@ body: |
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; SI-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; SI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
;
; VI-LABEL: name: test_copysign_v2s32_v2s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
@@ -833,8 +833,8 @@ body: |
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; VI-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; VI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
;
; GFX9-LABEL: name: test_copysign_v2s32_v2s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
@@ -855,8 +855,8 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
%2:_(<2 x s32>) = G_FCOPYSIGN %0, %1
@@ -878,8 +878,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY %2(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s32_flagss
; VI: liveins: $vgpr0, $vgpr1
@@ -890,8 +890,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY %2(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s32_flagss
; GFX9: liveins: $vgpr0, $vgpr1
@@ -902,8 +902,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = nnan G_FCOPYSIGN %0, %1
@@ -929,8 +929,8 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0 = COPY %3(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s16_flags
; VI: liveins: $vgpr0, $vgpr1
@@ -945,8 +945,8 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0 = COPY %3(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s16_flags
; GFX9: liveins: $vgpr0, $vgpr1
@@ -961,8 +961,8 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0 = COPY %3(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -990,8 +990,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s32_flags
@@ -1007,8 +1007,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s32_flags
@@ -1024,8 +1024,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
diff --git a/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir b/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
index 6542508ede116..f99d41e98f06c 100644
--- a/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
@@ -5,7 +5,7 @@
@ds = external global i8
define i64 @pauth_sign_zero(i64 %p) {
- ; CHECK: G_INTRINSIC intrinsic(@llvm.ptrauth.sign), %0(s64), 0, %2(s64), deactivation-symbol @ds
+ ; CHECK: G_INTRINSIC intrinsic(@llvm.ptrauth.sign), %0(i64), 0, %2(i64), deactivation-symbol @ds
%signed = call i64 @llvm.ptrauth.sign(i64 %p, i32 0, i64 0) [ "deactivation-symbol"(ptr @ds) ]
ret i64 %signed
}
diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
index 9a014e0cce5d6..2d22abd86cebe 100644
--- a/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
@@ -10,10 +10,10 @@
define i32 @int_aarch64_sdiv(i32 %a, i32 %b) nounwind readnone ssp {
; CHECK-LABEL: name: int_aarch64_sdiv
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), [[COPY]](s32), [[COPY1]](s32)
- ; CHECK: $w0 = COPY [[INT]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK: [[INT:%[0-9]+]]:_(i32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), [[COPY]](i32), [[COPY1]](i32)
+ ; CHECK: $w0 = COPY [[INT]](i32)
; CHECK: RET_ReallyLR implicit $w0
entry:
%sdiv = call i32 @llvm.aarch64.sdiv.i32(i32 %a, i32 %b)
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
index 22181ce33f0da..8f7008d2d1e0e 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
@@ -1607,9 +1607,9 @@ TEST_F(AArch64GISelMITest, LowerFNEG) {
auto CheckStr = R"(
CHECK: [[FADD:%[0-9]+]]:_(s64) = nsz G_FADD %0:_, %1:_
- CHECK: [[CONST0:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
+ CHECK: [[CONST0:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
CHECK: [[FSUB0:%[0-9]+]]:_(s64) = G_XOR [[FADD]]:_, [[CONST0]]:_
- CHECK: [[CONST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
+ CHECK: [[CONST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
CHECK: [[FSUB1:%[0-9]+]]:_(s64) = G_XOR %0:_, [[CONST1]]:_
)";
@@ -1673,32 +1673,32 @@ TEST_F(AArch64GISelMITest, LowerMinMax) {
Helper.lower(*UMaxV, 0, v2s32));
auto CheckStr = R"(
- CHECK: [[CMP0:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), %0:_(s64), %1:_
- CHECK: [[SMIN:%[0-9]+]]:_(s64) = G_SELECT [[CMP0]]:_(s1), %0:_, %1:_
+ CHECK: [[CMP0:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), %0:_(s64), %1:_
+ CHECK: [[SMIN:%[0-9]+]]:_(s64) = G_SELECT [[CMP0]]:_(i1), %0:_, %1:_
- CHECK: [[CMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), %0:_(s64), %1:_
- CHECK: [[SMAX:%[0-9]+]]:_(s64) = G_SELECT [[CMP1]]:_(s1), %0:_, %1:_
+ CHECK: [[CMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(sgt), %0:_(s64), %1:_
+ CHECK: [[SMAX:%[0-9]+]]:_(s64) = G_SELECT [[CMP1]]:_(i1), %0:_, %1:_
- CHECK: [[CMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), %0:_(s64), %1:_
- CHECK: [[UMIN:%[0-9]+]]:_(s64) = G_SELECT [[CMP2]]:_(s1), %0:_, %1:_
+ CHECK: [[CMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ult), %0:_(s64), %1:_
+ CHECK: [[UMIN:%[0-9]+]]:_(s64) = G_SELECT [[CMP2]]:_(i1), %0:_, %1:_
- CHECK: [[CMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), %0:_(s64), %1:_
- CHECK: [[UMAX:%[0-9]+]]:_(s64) = G_SELECT [[CMP3]]:_(s1), %0:_, %1:_
+ CHECK: [[CMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), %0:_(s64), %1:_
+ CHECK: [[UMAX:%[0-9]+]]:_(s64) = G_SELECT [[CMP3]]:_(i1), %0:_, %1:_
CHECK: [[VEC0:%[0-9]+]]:_(<2 x s32>) = G_BITCAST %0:_(s64)
CHECK: [[VEC1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST %1:_(s64)
- CHECK: [[VCMP0:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(slt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
- CHECK: [[SMINV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP0]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
+ CHECK: [[VCMP0:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(slt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
+ CHECK: [[SMINV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP0]]:_(<2 x i1>), [[VEC0]]:_, [[VEC1]]:_
- CHECK: [[VCMP1:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(sgt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
- CHECK: [[SMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP1]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
+ CHECK: [[VCMP1:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(sgt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
+ CHECK: [[SMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP1]]:_(<2 x i1>), [[VEC0]]:_, [[VEC1]]:_
- CHECK: [[VCMP2:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ult), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
- CHECK: [[UMINV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP2]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
+ CHECK: [[VCMP2:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(ult), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
+ CHECK: [[UMINV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP2]]:_(<2 x i1>), [[VEC0]]:_, [[VEC1]]:_
- CHECK: [[VCMP3:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ugt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
- CHECK: [[UMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP3]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
+ CHECK: [[VCMP3:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(ugt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
+ CHECK: [[UMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP3]]:_(<2 x i1>), [[VEC0]]:_, [[VEC1]]:_
)";
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
@@ -2181,8 +2181,8 @@ TEST_F(AArch64GISelMITest, LibcallMul) {
CHECK: $x0 = COPY [[COPY]]
CHECK: $x1 = COPY [[COPY]]
CHECK: BL &__muldi3
- CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
- CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]
CHECK: $x2 = COPY [[UV2]]
@@ -2239,8 +2239,8 @@ TEST_F(AArch64GISelMITest, LibcallSRem) {
CHECK: $x0 = COPY [[COPY]]
CHECK: $x1 = COPY [[COPY]]
CHECK: BL &__moddi3
- CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
- CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]
CHECK: $x2 = COPY [[UV2]]
@@ -2297,8 +2297,8 @@ TEST_F(AArch64GISelMITest, LibcallURem) {
CHECK: $x0 = COPY [[COPY]]
CHECK: $x1 = COPY [[COPY]]
CHECK: BL &__umoddi3
- CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
- CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]
CHECK: $x2 = COPY [[UV2]]
@@ -2354,7 +2354,7 @@ TEST_F(AArch64GISelMITest, LibcallCtlzZeroUndef) {
CHECK: BL &__clzsi2
CHECK: $x0 = COPY [[COPY]]
CHECK: BL &__clzdi2
- CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]
CHECK: BL &__clzti2
@@ -4266,7 +4266,7 @@ TEST_F(AArch64GISelMITest, MoreElementsSelect) {
CHECK: [[ZERO0:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), %{{[0-9]+}}:_(s64), [[ZERO0]]
CHECK: [[IMPDEF:%[0-9]+]]:_(<2 x s1>) = G_IMPLICIT_DEF
- CHECK: [[ZERO1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ CHECK: [[ZERO1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
CHECK: [[INSERT:%[0-9]+]]:_(<2 x s1>) = G_INSERT_VECTOR_ELT [[IMPDEF]]:_, [[CMP]]:_(s1), [[ZERO1]]
CHECK: [[SHUFFLE:%[0-9]+]]:_(<2 x s1>) = G_SHUFFLE_VECTOR [[INSERT]]:_(<2 x s1>), [[IMPDEF]]:_, shufflemask(0, 0)
CHECK: [[SELECT:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[SHUFFLE]]:_(<2 x s1>), [[BITCAST0]]:_, [[BITCAST1]]:_
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
index c5992ebb831ed..81626a03bd6d4 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
@@ -77,8 +77,8 @@ TEST_F(AArch64GISelMITest, BasicLegalizerTest) {
StringRef CheckString = R"(
CHECK: %vptr:_(p0) = COPY $x4
CHECK-NEXT: [[LOAD_0:%[0-9]+]]:_(s16) = G_LOAD %vptr:_(p0) :: (load (s8))
- CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(s64)
+ CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(i64)
CHECK-NEXT: [[LOAD_1:%[0-9]+]]:_(s16) = G_LOAD [[VPTR_1]]:_(p0) :: (load (s8) from unknown-address + 1)
CHECK-NEXT: %v:_(<2 x s8>) = G_BUILD_VECTOR_TRUNC [[LOAD_0]]:_(s16), [[LOAD_1]]:_(s16)
CHECK-NEXT: $h4 = COPY %v:_(<2 x s8>)
@@ -209,8 +209,8 @@ TEST_F(AArch64GISelMITest, UnorderedArtifactCombiningManyCopiesTest) {
StringRef CheckString = R"(
CHECK: %vptr:_(p0) = COPY $x4
CHECK-NEXT: [[LOAD_0:%[0-9]+]]:_(s16) = G_LOAD %vptr:_(p0) :: (load (s8))
- CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(s64)
+ CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(i64)
CHECK-NEXT: [[LOAD_1:%[0-9]+]]:_(s16) = G_LOAD [[VPTR_1]]:_(p0) :: (load (s8) from unknown-address + 1)
CHECK-NEXT: [[V0_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD_0]]:_(s16)
CHECK-NEXT: [[FF_MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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