[llvm] [AArch64] Fold sext-in-reg for predicate -> fixed-length conversions. (PR #176883)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp --diff_from_common_commit
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 61cd21458..92ce9e3a2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4721,7 +4721,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
   unsigned FirstAnswer = 1;
 
   assert((!VT.isScalableVector() || NumElts == 1) &&
-       "DemandedElts for scalable vectors must be 1 to represent all lanes");
+         "DemandedElts for scalable vectors must be 1 to represent all lanes");
 
   if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
     const APInt &Val = C->getAPIntValue();
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index 99078fcd5..6e6fc06e9 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -167,7 +167,8 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_EXTRACT_SUBVECTOR) {
 TEST_F(AArch64SelectionDAGTest, ComputeNumSignBitsSVE_EXTRACT_SUBVECTOR) {
   SDLoc Loc;
   auto IntVT = EVT::getIntegerVT(Context, 8);
-  auto ScalableVecVT = EVT::getVectorVT(Context, IntVT, 16, /*IsScalable=*/true);
+  auto ScalableVecVT =
+      EVT::getVectorVT(Context, IntVT, 16, /*IsScalable=*/true);
   auto FixedVecVT = EVT::getVectorVT(Context, IntVT, 16, /*IsScalable=*/false);
   auto IdxVT = EVT::getIntegerVT(Context, 64);
   auto Vec = DAG->getConstant(1, Loc, ScalableVecVT);

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https://github.com/llvm/llvm-project/pull/176883