[llvm] [AMDGPU][SILoadStoreOptimizer] Fix lds address operand offset (PR #176816)

[Matt Arsenault via llvm-commits]

================
@@ -2242,6 +2274,72 @@ SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) const {
   return Def->getOperand(1).getImm();
 }
 
+std::optional<int64_t>
+SILoadStoreOptimizer::extractConstOffset64(const MachineOperand &Op) const {
+  if (Op.isImm())
+    return Op.getImm();
+
+  if (!Op.isReg())
+    return std::nullopt;
+
+  MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
+  if (!Def)
+    return std::nullopt;
+
+  // Handle S_MOV_B64_IMM_PSEUDO for 64-bit immediates
+  if (Def->getOpcode() == AMDGPU::S_MOV_B64_IMM_PSEUDO)
+    return TII->getNamedImmOperand(*Def, AMDGPU::OpName::src0);
+
+  return std::nullopt;
+}
+
+// Helper to extract a 64-bit constant offset from a V_ADD_U64_e64 instruction.
+// Returns true if successful, populating Addr with base register info and
+// offset.
+bool SILoadStoreOptimizer::processBaseWithConstOffset64(
+    const MachineOperand &Base, MemAddress &Addr) const {
+  if (!Base.isReg())
+    return false;
+
+  MachineInstr *Def = MRI->getUniqueVRegDef(Base.getReg());
+  if (!Def || Def->getOpcode() != AMDGPU::V_ADD_U64_e64)
+    return false;
+
+  const auto *Src0 = TII->getNamedOperand(*Def, AMDGPU::OpName::src0);
+  const auto *Src1 = TII->getNamedOperand(*Def, AMDGPU::OpName::src1);
+  if (!Src0 || !Src1)
+    return false;
----------------
arsenm wrote:

```suggestion
```
Cannot fail 

https://github.com/llvm/llvm-project/pull/176816