[llvm] 5afabf1 - [AArch64] Correct SD/GI test checks in arm64-neon-simd-ldst-one.ll. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2026-01-21T10:28:36Z
New Revision: 5afabf1ae83b82d3b5d62f7fc8291565945556fb

URL: https://github.com/llvm/llvm-project/commit/5afabf1ae83b82d3b5d62f7fc8291565945556fb
DIFF: https://github.com/llvm/llvm-project/commit/5afabf1ae83b82d3b5d62f7fc8291565945556fb.diff

LOG: [AArch64] Correct SD/GI test checks in arm64-neon-simd-ldst-one.ll. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll b/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
index f47c06e1ba4cb..7483eab10df65 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 
 %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
@@ -296,18 +296,18 @@ entry:
 define <1 x i64> @testDUP.v1i64(ptr %a, ptr %b) #0 {
 ; As there is a store operation depending on %1, LD1R pattern can't be selected.
 ; So LDR and FMOV should be emitted.
-; CHECK-GI-LABEL: testDUP.v1i64:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    ldr x8, [x0]
-; CHECK-GI-NEXT:    fmov d0, x8
-; CHECK-GI-NEXT:    str x8, [x1]
-; CHECK-GI-NEXT:    ret
-;
 ; CHECK-SD-LABEL: testDUP.v1i64:
 ; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ldr d0, [x0]
-; CHECK-SD-NEXT:    str d0, [x1]
+; CHECK-SD-NEXT:    ldr x8, [x0]
+; CHECK-SD-NEXT:    fmov d0, x8
+; CHECK-SD-NEXT:    str x8, [x1]
 ; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: testDUP.v1i64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    ldr d0, [x0]
+; CHECK-GI-NEXT:    str d0, [x1]
+; CHECK-GI-NEXT:    ret
   %1 = load i64, ptr %a, align 8
   store i64 %1, ptr %b, align 8
   %vecinit.i = insertelement <1 x i64> undef, i64 %1, i32 0
@@ -614,16 +614,16 @@ entry:
 }
 
 define void @test_vst1_lane0_s16(ptr %a, <4 x i16> %b) {
-; CHECK-GI-LABEL: test_vst1_lane0_s16:
-; CHECK-GI:       // %bb.0: // %entry
-; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT:    str h0, [x0]
-; CHECK-GI-NEXT:    ret
-;
 ; CHECK-SD-LABEL: test_vst1_lane0_s16:
 ; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-SD-NEXT:    str h0, [x0]
 ; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vst1_lane0_s16:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    str h0, [x0]
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = extractelement <4 x i16> %b, i32 0
   store i16 %0, ptr %a, align 2
@@ -643,16 +643,16 @@ entry:
 }
 
 define void @test_vst1_lane0_s32(ptr %a, <2 x i32> %b) {
-; CHECK-GI-LABEL: test_vst1_lane0_s32:
-; CHECK-GI:       // %bb.0: // %entry
-; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT:    str s0, [x0]
-; CHECK-GI-NEXT:    ret
-;
 ; CHECK-SD-LABEL: test_vst1_lane0_s32:
 ; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-SD-NEXT:    str s0, [x0]
 ; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vst1_lane0_s32:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    str s0, [x0]
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = extractelement <2 x i32> %b, i32 0
   store i32 %0, ptr %a, align 4
@@ -683,16 +683,16 @@ entry:
 }
 
 define void @test_vst1_lane0_f32(ptr %a, <2 x float> %b) {
-; CHECK-GI-LABEL: test_vst1_lane0_f32:
-; CHECK-GI:       // %bb.0: // %entry
-; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT:    str s0, [x0]
-; CHECK-GI-NEXT:    ret
-;
 ; CHECK-SD-LABEL: test_vst1_lane0_f32:
 ; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-SD-NEXT:    str s0, [x0]
 ; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_vst1_lane0_f32:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    str s0, [x0]
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = extractelement <2 x float> %b, i32 0
   store float %0, ptr %a, align 4