[llvm] [AMDGPU] Add wave reduce intrinsics for double types - 1 (PR #170811)

[Matt Arsenault via llvm-commits]

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@@ -5943,6 +5942,63 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
                              .addReg(Accumulator->getOperand(0).getReg());
         break;
       }
+      case AMDGPU::V_MIN_F64_e64:
+      case AMDGPU::V_MAX_F64_e64: {
+        int SrcIdx =
+            AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src);
+        const TargetRegisterClass *VregRC =
+            TRI->getAllocatableClass(TII->getRegClass(MI.getDesc(), SrcIdx));
+        const TargetRegisterClass *VregSubRC =
+            TRI->getSubRegisterClass(VregRC, AMDGPU::sub0);
+        Register AccumulatorVReg = MRI.createVirtualRegister(VregRC);
+        Register DstVreg = MRI.createVirtualRegister(VregRC);
+        Register LaneValLo =
+            MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+        Register LaneValHi =
+            MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+        BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_MOV_B64_PSEUDO),
+                AccumulatorVReg)
+            .addReg(Accumulator->getOperand(0).getReg());
+        if (IsGFX12Plus) {
+          switch (Opc) {
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arsenm wrote:

This opcode usage is confusing. It looks like this is substituting the real opcode for another, but really the opcode was just a filler value from the argument to this function. Can you add a comment about this 

https://github.com/llvm/llvm-project/pull/170811