[llvm] 0f582c3 - [RISCV][llvm] Simplify bf16 _ALT suffix in VSD/VVL patterns. NFC (#176744)
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llvm-commits at lists.llvm.org
Tue Jan 20 23:14:24 PST 2026
Author: Brandon Wu
Date: 2026-01-21T07:14:19Z
New Revision: 0f582c3fa9090340f00ec39c912d89bece82f329
URL: https://github.com/llvm/llvm-project/commit/0f582c3fa9090340f00ec39c912d89bece82f329
DIFF: https://github.com/llvm/llvm-project/commit/0f582c3fa9090340f00ec39c912d89bece82f329.diff
LOG: [RISCV][llvm] Simplify bf16 _ALT suffix in VSD/VVL patterns. NFC (#176744)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index acf942484efae..97e61d61ceb9a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -202,13 +202,12 @@ class VPatBinarySDNode_VF_RM<SDPatternOperator vop,
multiclass VPatBinaryFPSDNode_VV_VF<SDPatternOperator vop, string instruction_name,
bit isSEWAware = 0> {
foreach vti = AllFloatAndBF16Vectors in {
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = GetVTypePredicates<vti>.Predicates in {
- def : VPatBinarySDNode_VV<vop, instruction_name #
- !if(!eq(vti.Scalar, bf16), "_ALT", ""),
+ def : VPatBinarySDNode_VV<vop, instruction_name # alt,
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
- def : VPatBinarySDNode_VF<vop, instruction_name#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ def : VPatBinarySDNode_VF<vop, instruction_name # alt #
"_V"#vti.ScalarSuffix,
vti.Vector, vti.Vector, vti.Scalar,
vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
@@ -221,13 +220,12 @@ multiclass VPatBinaryFPSDNode_VV_VF_RM<SDPatternOperator vop, string instruction
list<VTypeInfo> vtilist = AllFloatVectors,
bit isSEWAware = 0> {
foreach vti = vtilist in {
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = GetVTypePredicates<vti>.Predicates in {
- def : VPatBinarySDNode_VV_RM<vop, instruction_name #
- !if(!eq(vti.Scalar, bf16), "_ALT", ""),
+ def : VPatBinarySDNode_VV_RM<vop, instruction_name # alt,
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
- def : VPatBinarySDNode_VF_RM<vop, instruction_name#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ def : VPatBinarySDNode_VF_RM<vop, instruction_name # alt #
"_V"#vti.ScalarSuffix,
vti.Vector, vti.Vector, vti.Scalar,
vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
@@ -1366,6 +1364,7 @@ foreach vtiToWti = AllWidenableBF16ToFloatVectors in {
}
foreach vti = AllFloatAndBF16Vectors in {
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = GetVTypePredicates<vti>.Predicates in {
// 13.8. Vector Floating-Point Square-Root Instruction
if !ne(vti.Scalar, bf16) then
@@ -1380,45 +1379,39 @@ foreach vti = AllFloatAndBF16Vectors in {
// 13.12. Vector Floating-Point Sign-Injection Instructions
def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),
- (!cast<Instruction>("PseudoVFSGNJX"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJX"# alt #
"_VV_"# vti.LMul.MX#"_E"#vti.SEW)
(vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TA_MA)>;
// Handle fneg with VFSGNJN using the same input for both operands.
def : Pat<(fneg (vti.Vector vti.RegClass:$rs)),
- (!cast<Instruction>("PseudoVFSGNJN"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJN"# alt #
"_VV_"# vti.LMul.MX#"_E"#vti.SEW)
(vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$rs2))),
- (!cast<Instruction>("PseudoVFSGNJ"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJ"# alt #
"_VV_"# vti.LMul.MX#"_E"#vti.SEW)
(vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs2)))),
- (!cast<Instruction>("PseudoVFSGNJ"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJ"# alt #
"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
(vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (fneg vti.RegClass:$rs2)))),
- (!cast<Instruction>("PseudoVFSGNJN"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJN"# alt #
"_VV_"# vti.LMul.MX#"_E"#vti.SEW)
(vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))),
- (!cast<Instruction>("PseudoVFSGNJN"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJN"# alt #
"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
(vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 44550ea84d56d..32fc3b7a97613 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1044,14 +1044,13 @@ class VPatBinaryVL_VF_RM<SDPatternOperator vop,
multiclass VPatBinaryFPVL_VV_VF<SDPatternOperator vop, string instruction_name,
bit isSEWAware = 0> {
foreach vti = AllFloatAndBF16Vectors in {
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = GetVTypePredicates<vti>.Predicates in {
- def : VPatBinaryVL_V<vop, instruction_name#
- !if(!eq(vti.Scalar, bf16), "_ALT", ""), "VV",
+ def : VPatBinaryVL_V<vop, instruction_name# alt, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
vti.RegClass, isSEWAware>;
- def : VPatBinaryVL_VF<vop, instruction_name#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#"_V"#
+ def : VPatBinaryVL_VF<vop, instruction_name# alt #"_V"#
vti.ScalarSuffix,
vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
@@ -1064,14 +1063,13 @@ multiclass VPatBinaryFPVL_VV_VF_RM<SDPatternOperator vop, string instruction_nam
list<VTypeInfo> vtilist = AllFloatVectors,
bit isSEWAware = 0> {
foreach vti = vtilist in {
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = GetVTypePredicates<vti>.Predicates in {
- def : VPatBinaryVL_V_RM<vop, instruction_name #
- !if(!eq(vti.Scalar, bf16), "_ALT", ""), "VV",
+ def : VPatBinaryVL_V_RM<vop, instruction_name # alt, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
vti.RegClass, isSEWAware>;
- def : VPatBinaryVL_VF_RM<vop, instruction_name#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ def : VPatBinaryVL_VF_RM<vop, instruction_name# alt #
"_V"#vti.ScalarSuffix,
vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
@@ -1203,6 +1201,7 @@ multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
string inst_name,
string swapped_op_inst_name> {
foreach fvti = AllFloatAndBF16Vectors in {
+ defvar alt = !if(!eq(fvti.Scalar, bf16), "_ALT", "");
let Predicates = GetVTypePredicates<fvti>.Predicates in {
def : Pat<(fvti.Mask (vop (fvti.Vector fvti.RegClass:$rs1),
fvti.RegClass:$rs2,
@@ -1210,8 +1209,7 @@ multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
VR:$passthru,
(fvti.Mask VMV0:$vm),
VLOpFrag)),
- (!cast<Instruction>(inst_name#
- !if(!eq(fvti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>(inst_name# alt #
"_VV_"#fvti.LMul.MX#"_MASK")
VR:$passthru, fvti.RegClass:$rs1,
fvti.RegClass:$rs2, (fvti.Mask VMV0:$vm),
@@ -1222,8 +1220,7 @@ multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
VR:$passthru,
(fvti.Mask VMV0:$vm),
VLOpFrag)),
- (!cast<Instruction>(inst_name#
- !if(!eq(fvti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>(inst_name# alt #
"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")
VR:$passthru, fvti.RegClass:$rs1,
fvti.ScalarRegClass:$rs2, (fvti.Mask VMV0:$vm),
@@ -1234,8 +1231,7 @@ multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,
VR:$passthru,
(fvti.Mask VMV0:$vm),
VLOpFrag)),
- (!cast<Instruction>(swapped_op_inst_name#
- !if(!eq(fvti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>(swapped_op_inst_name# alt #
"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")
VR:$passthru, fvti.RegClass:$rs1,
fvti.ScalarRegClass:$rs2, (fvti.Mask VMV0:$vm),
@@ -2473,12 +2469,12 @@ foreach vti = AllFloatVectors in {
}
foreach vti = AllBF16Vectors in {
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = GetVTypePredicates<vti>.Predicates in {
// 13.12. Vector Floating-Point Sign-Injection Instructions
def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask VMV0:$vm),
VLOpFrag),
- (!cast<Instruction>("PseudoVFSGNJX"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJX"# alt #
"_VV_"# vti.LMul.MX #"_E"#vti.SEW#"_MASK")
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs,
vti.RegClass:$rs, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,
@@ -2486,8 +2482,7 @@ foreach vti = AllBF16Vectors in {
// Handle fneg with VFSGNJN using the same input for both operands.
def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask VMV0:$vm),
VLOpFrag),
- (!cast<Instruction>("PseudoVFSGNJN"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJN"# alt #
"_VV_"# vti.LMul.MX#"_E"#vti.SEW #"_MASK")
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs,
vti.RegClass:$rs, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,
@@ -2498,8 +2493,7 @@ foreach vti = AllBF16Vectors in {
vti.RegClass:$passthru,
(vti.Mask VMV0:$vm),
VLOpFrag),
- (!cast<Instruction>("PseudoVFSGNJ"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJ"# alt #
"_VV_"# vti.LMul.MX#"_E"#vti.SEW#"_MASK")
vti.RegClass:$passthru, vti.RegClass:$rs1,
vti.RegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,
@@ -2512,8 +2506,7 @@ foreach vti = AllBF16Vectors in {
srcvalue,
(vti.Mask true_mask),
VLOpFrag),
- (!cast<Instruction>("PseudoVFSGNJN"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJN"# alt #
"_VV_"# vti.LMul.MX#"_E"#vti.SEW)
(vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;
@@ -2523,8 +2516,7 @@ foreach vti = AllBF16Vectors in {
vti.RegClass:$passthru,
(vti.Mask VMV0:$vm),
VLOpFrag),
- (!cast<Instruction>("PseudoVFSGNJ"#
- !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ (!cast<Instruction>("PseudoVFSGNJ"# alt #
"_V"#vti.ScalarSuffix#"_"# vti.LMul.MX#"_E"#vti.SEW#"_MASK")
vti.RegClass:$passthru, vti.RegClass:$rs1,
vti.ScalarRegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,
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