[llvm] [llvm][RISCV] Make X0 register pair legal in pre-ra pass (PR #169164)

[Sam Elliott via llvm-commits]

https://github.com/lenary commented:

Please may you also add an IR test to `llvm/test/CodeGen/RISCV/zilsd.ll` to show that the late pass will handle this correctly - I'm happy for this to be a copy of `basic_store_zero_combine`, which seems like it has all the info required.

https://github.com/llvm/llvm-project/pull/169164