[llvm] AMDGPU: Handle FP in integer in argument lowering (PR #175835)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/175835

>From bbe906e08607f7529e8e594fb347ffbdf39269e6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 13 Jan 2026 21:59:26 +0100
Subject: [PATCH 1/3] AMDGPU: Handle FP in integer in argument lowering

This avoids an assertion when softPromoteHalfType is
enabled.
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ed5988ee6efc3..94f71ab12c5d4 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2306,9 +2306,16 @@ SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
     Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
   }
 
-  if (MemVT.isFloatingPoint())
-    Val = getFPExtOrFPRound(DAG, Val, SL, VT);
-  else if (Signed)
+  if (MemVT.isFloatingPoint()) {
+    if (VT.isFloatingPoint())
+      Val = getFPExtOrFPRound(DAG, Val, SL, VT);
+    else {
+      assert(!MemVT.isVector());
+      EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
+      SDValue Cast = DAG.getBitcast(IntVT, Val);
+      Val = DAG.getAnyExtOrTrunc(Cast, SL, VT);
+    }
+  } else if (Signed)
     Val = DAG.getSExtOrTrunc(Val, SL, VT);
   else
     Val = DAG.getZExtOrTrunc(Val, SL, VT);

>From a83a4127895b2d9de387d9d247ab1dc174ad96ae Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 20 Jan 2026 20:52:07 +0100
Subject: [PATCH 2/3] Apply suggestion from @cdevadas

Co-authored-by: Christudasan Devadasan <christudasan.devadasan at amd.com>
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 94f71ab12c5d4..1e8e285e9dda2 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2307,9 +2307,9 @@ SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
   }
 
   if (MemVT.isFloatingPoint()) {
-    if (VT.isFloatingPoint())
+    if (VT.isFloatingPoint()) {
       Val = getFPExtOrFPRound(DAG, Val, SL, VT);
-    else {
+    }  else {
       assert(!MemVT.isVector());
       EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
       SDValue Cast = DAG.getBitcast(IntVT, Val);

>From 19f22a0caa599f8bc2af000c537efc22f8818083 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 20 Jan 2026 20:52:32 +0100
Subject: [PATCH 3/3] whitespace fix

---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 1e8e285e9dda2..5dce7832e6c6f 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2309,7 +2309,7 @@ SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
   if (MemVT.isFloatingPoint()) {
     if (VT.isFloatingPoint()) {
       Val = getFPExtOrFPRound(DAG, Val, SL, VT);
-    }  else {
+    } else {
       assert(!MemVT.isVector());
       EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
       SDValue Cast = DAG.getBitcast(IntVT, Val);