[llvm] [AMDGPU] Introduce custom MIR formatting for s_wait_alu (PR #176316)

[Matt Arsenault via llvm-commits]

================
@@ -90,6 +138,93 @@ void AMDGPUMIRFormatter::printSDelayAluImm(int64_t Imm,
   Outdep(Id1);
 }
 
+bool AMDGPUMIRFormatter::parseSWaitAluImmMnemonic(
+    const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src,
+    llvm::MIRFormatter::ErrorCallbackType &ErrorCallback) const {
+  // TODO: For now accept integer masks for compatibility with old MIR.
+  if (!Src.consumeInteger(10, Imm))
+    return false;
+
+  // Initialize with all checks off.
+  Imm = AMDGPU::DepCtr::getDefaultDepCtrEncoding(STI);
+  // The input is in the form: .Name1_Num1_Name2_Num2
+  // Drop the '.' prefix.
+  bool Expected = Src.consume_front(SWaitAluImmPrefix);
+  if (!Expected)
+    return ErrorCallback(Src.begin(), "expected prefix");
+  bool Empty = true;
+
+  // Special case for all off.
+  if (Src == AllOff)
+    return false;
+
+  // Parse a counter name, number pair in each iteration.
+  while (!Src.empty()) {
+    // Src: Name1_Num1_Name2_Num2
+    //           ^
+    size_t Delim1Idx = Src.find(SWaitAluDelim);
+    if (Delim1Idx == StringRef::npos) {
+      if (Empty)
+        return ErrorCallback(Src.begin() + Src.size(),
+                             "expected <CounterName>_<CounterNum>");
+      break;
+    }
+    // Src: Name1_Num1_Name2_Num2
+    //      ^^^^^
+    StringRef Name = Src.substr(0, Delim1Idx);
+    // Src: Name1_Num1_Name2_Num2
+    //                ^
+    size_t Delim2Idx = Src.find(SWaitAluDelim, Delim1Idx + 1);
+    // Src: Name1_Num1_Name2_Num2
+    //            ^^^^
+    StringRef NumStr = Src.substr(Delim1Idx + 1, Delim2Idx);
+    if (Name.empty() || NumStr.empty())
+      return ErrorCallback(Src.begin() + Delim1Idx,
+                           "expected <CounterName>_<CounterNum>");
+    // Make sure the counter number is legal.
+    int64_t Num;
+    if (NumStr.consumeInteger(10, Num) || Num < 0)
+      return ErrorCallback(Src.begin() + Delim1Idx + 1,
+                           "expected non-negative integer counter number");
+
+    // Encode the counter number into Imm.
+    unsigned Max;
+    if (Name == VaVdstName) {
+      Max = llvm::AMDGPU::DepCtr::getVaVdstBitMask();
+      Imm = llvm::AMDGPU::DepCtr::encodeFieldVaVdst(Imm, Num);
+    } else if (Name == VmVsrcName) {
+      Max = llvm::AMDGPU::DepCtr::getVmVsrcBitMask();
+      Imm = llvm::AMDGPU::DepCtr::encodeFieldVmVsrc(Imm, Num);
+    } else if (Name == VaSdstName) {
+      Max = llvm::AMDGPU::DepCtr::getVaSdstBitMask();
+      Imm = llvm::AMDGPU::DepCtr::encodeFieldVaSdst(Imm, Num);
+    } else if (Name == VaSsrcName) {
+      Max = llvm::AMDGPU::DepCtr::getVaSsrcBitMask();
+      Imm = llvm::AMDGPU::DepCtr::encodeFieldVaSsrc(Imm, Num);
+    } else if (Name == HoldCntName) {
+      Max = llvm::AMDGPU::DepCtr::getHoldCntBitMask(STI);
+      Imm = llvm::AMDGPU::DepCtr::encodeFieldHoldCnt(Imm, Num);
+    } else if (Name == VaVccName) {
+      Max = llvm::AMDGPU::DepCtr::getVaVccBitMask();
+      Imm = llvm::AMDGPU::DepCtr::encodeFieldVaVcc(Imm, Num);
+    } else if (Name == SaSdstName) {
+      Max = llvm::AMDGPU::DepCtr::getSaSdstBitMask();
+      Imm = llvm::AMDGPU::DepCtr::encodeFieldSaSdst(Imm, Num);
+    } else {
+      return ErrorCallback(Src.begin(), "bad counter name");
----------------
arsenm wrote:

```suggestion
      return ErrorCallback(Src.begin(), "invalid counter name");
```

https://github.com/llvm/llvm-project/pull/176316