[llvm] 2668f87 - [AMDGPU][NFC] Update test to use update_llc_test_checks (#176595)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 19 11:13:33 PST 2026
Author: vangthao95
Date: 2026-01-19T11:13:29-08:00
New Revision: 2668f87fc64648c60444a38f949730f884c65d74
URL: https://github.com/llvm/llvm-project/commit/2668f87fc64648c60444a38f949730f884c65d74
DIFF: https://github.com/llvm/llvm-project/commit/2668f87fc64648c60444a38f949730f884c65d74.diff
LOG: [AMDGPU][NFC] Update test to use update_llc_test_checks (#176595)
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
index adae3a0e382ab..7db49bca36062 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
@@ -1,21 +1,47 @@
-; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX678,GFX6789 %s
-; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX9,GFX6789 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX678 %s
+; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX9 %s
; RUN: llc -global-isel -mcpu=gfx1010 -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GFX10 %s
-; RUN: llc -global-isel -mcpu=gfx1100 -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GFX10 %s
+; RUN: llc -global-isel -mcpu=gfx1100 -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GFX11 %s
declare i64 @llvm.smax.i64(i64, i64)
declare i64 @llvm.smin.i64(i64, i64)
-; GCN-LABEL: {{^}}v_clamp_i64_i16
-; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
-; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
-; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GFX10: v_cvt_pk_i16_i32{{(_e64)?}} [[A:v[0-9]+]], {{v[0-9]+}}, [[B:v[0-9]+]]
-; GFX10: v_mov_b32_e32 [[B]], 0x7fff
-; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[B]]
define i16 @v_clamp_i64_i16(i64 %in) #0 {
+; GFX678-LABEL: v_clamp_i64_i16:
+; GFX678: ; %bb.0: ; %entry
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: v_cvt_pk_i16_i32_e32 v0, v0, v1
+; GFX678-NEXT: v_mov_b32_e32 v1, 0xffff8000
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX678-NEXT: v_med3_i32 v0, v1, v0, v2
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_clamp_i64_i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff8000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX9-NEXT: v_med3_i32 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_clamp_i64_i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX10-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_clamp_i64_i16:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX11-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%max = call i64 @llvm.smax.i64(i64 %in, i64 -32768)
%min = call i64 @llvm.smin.i64(i64 %max, i64 32767)
@@ -23,16 +49,41 @@ entry:
ret i16 %result
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_reverse
-; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
-; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
-; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GFX10: v_cvt_pk_i16_i32{{(_e64)?}} [[A:v[0-9]+]], {{v[0-9]+}}, [[B:v[0-9]+]]
-; GFX10: v_mov_b32_e32 [[B]], 0x7fff
-; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[B]]
define i16 @v_clamp_i64_i16_reverse(i64 %in) #0 {
+; GFX678-LABEL: v_clamp_i64_i16_reverse:
+; GFX678: ; %bb.0: ; %entry
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: v_cvt_pk_i16_i32_e32 v0, v0, v1
+; GFX678-NEXT: v_mov_b32_e32 v1, 0xffff8000
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX678-NEXT: v_med3_i32 v0, v1, v0, v2
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_clamp_i64_i16_reverse:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff8000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX9-NEXT: v_med3_i32 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_clamp_i64_i16_reverse:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX10-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_clamp_i64_i16_reverse:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX11-NEXT: v_mov_b32_e32 v1, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%min = call i64 @llvm.smin.i64(i64 %in, i64 32767)
%max = call i64 @llvm.smax.i64(i64 %min, i64 -32768)
@@ -40,15 +91,62 @@ entry:
ret i16 %result
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_invalid_lower
-; GFX6789: v_mov_b32_e32 v{{[0-9]+}}, 0x8001
-; GFX6789: v_mov_b32_e32 [[B:v[0-9]+]], 0x8001
-; GFX6789: v_cndmask_b32_e32 [[A:v[0-9]+]], [[B]], [[A]], vcc
-; GFX6789: v_cndmask_b32_e32 [[C:v[0-9]+]], 0, [[C]], vcc
-
-; GFX10: v_{{(dual_)?}}cndmask_b32{{(_e32)?}} [[A:v[0-9]+]], 0x8001, [[A]]
-; GFX10: v_cndmask_b32_e32 [[B:v[0-9]+]], 0, [[B]], vcc_lo
define i16 @v_clamp_i64_i16_invalid_lower(i64 %in) #0 {
+; GFX678-LABEL: v_clamp_i64_i16_invalid_lower:
+; GFX678: ; %bb.0: ; %entry
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x8001
+; GFX678-NEXT: v_mov_b32_e32 v3, 0
+; GFX678-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX678-NEXT: v_mov_b32_e32 v4, 0x8001
+; GFX678-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX678-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX678-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX678-NEXT: v_mov_b32_e32 v3, -1
+; GFX678-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX678-NEXT: v_mov_b32_e32 v4, 0xffff8000
+; GFX678-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_clamp_i64_i16_invalid_lower:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x8001
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x8001
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, -1
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff8000
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_clamp_i64_i16_invalid_lower:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x8001, v[0:1]
+; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX10-NEXT: v_mov_b32_e32 v3, -1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x8001, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0xffff8000, v0, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_clamp_i64_i16_invalid_lower:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x8001, v[0:1]
+; GFX11-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX11-NEXT: v_dual_mov_b32 v3, -1 :: v_dual_cndmask_b32 v0, 0x8001, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0xffff8000, v0, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%min = call i64 @llvm.smin.i64(i64 %in, i64 32769)
%max = call i64 @llvm.smax.i64(i64 %min, i64 -32768)
@@ -56,12 +154,63 @@ entry:
ret i16 %result
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_invalid_lower_and_higher
-; GFX6789: v_mov_b32_e32 v{{[0-9]+}}, 0x8000
-; GFX6789: v_mov_b32_e32 [[B:v[0-9]+]], 0x8000
-; GFX6789: v_cndmask_b32_e32 [[A:v[0-9]+]], [[B]], [[A]], vcc
-; GFX10: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8000, [[A]], vcc_lo
define i16 @v_clamp_i64_i16_invalid_lower_and_higher(i64 %in) #0 {
+; GFX678-LABEL: v_clamp_i64_i16_invalid_lower_and_higher:
+; GFX678: ; %bb.0: ; %entry
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: v_mov_b32_e32 v2, 0xffff7fff
+; GFX678-NEXT: v_mov_b32_e32 v3, -1
+; GFX678-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX678-NEXT: v_mov_b32_e32 v4, 0xffff7fff
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x8000
+; GFX678-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX678-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc
+; GFX678-NEXT: v_mov_b32_e32 v3, 0
+; GFX678-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX678-NEXT: v_mov_b32_e32 v4, 0x8000
+; GFX678-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_clamp_i64_i16_invalid_lower_and_higher:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff7fff
+; GFX9-NEXT: v_mov_b32_e32 v3, -1
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff7fff
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x8000
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x8000
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_clamp_i64_i16_invalid_lower_and_higher:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff7fff
+; GFX10-NEXT: v_mov_b32_e32 v3, -1
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0xffff7fff, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc_lo
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x8000, v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x8000, v0, vcc_lo
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_clamp_i64_i16_invalid_lower_and_higher:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v2, 0xffff7fff
+; GFX11-NEXT: v_mov_b32_e32 v3, -1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0xffff7fff, v0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc_lo
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0x8000, v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x8000, v0, vcc_lo
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%max = call i64 @llvm.smax.i64(i64 %in, i64 -32769)
%min = call i64 @llvm.smin.i64(i64 %max, i64 32768)
@@ -69,16 +218,41 @@ entry:
ret i16 %result
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_lower_than_short
-; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
-; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
-; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GFX10: v_cvt_pk_i16_i32{{(_e64)?}} [[A:v[0-9]+]], {{v[0-9]+}}, [[B:v[0-9]+]]
-; GFX10: v_mov_b32_e32 [[B]], 0x100
-; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[B]]
define i16 @v_clamp_i64_i16_lower_than_short(i64 %in) #0 {
+; GFX678-LABEL: v_clamp_i64_i16_lower_than_short:
+; GFX678: ; %bb.0: ; %entry
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: v_cvt_pk_i16_i32_e32 v0, v0, v1
+; GFX678-NEXT: v_mov_b32_e32 v1, 0xffffff01
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x100
+; GFX678-NEXT: v_med3_i32 v0, v1, v0, v2
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_clamp_i64_i16_lower_than_short:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffff01
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x100
+; GFX9-NEXT: v_med3_i32 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_clamp_i64_i16_lower_than_short:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x100
+; GFX10-NEXT: v_med3_i32 v0, 0xffffff01, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_clamp_i64_i16_lower_than_short:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX11-NEXT: v_mov_b32_e32 v1, 0x100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_med3_i32 v0, 0xffffff01, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%min = call i64 @llvm.smin.i64(i64 %in, i64 256)
%max = call i64 @llvm.smax.i64(i64 %min, i64 -255)
@@ -86,16 +260,41 @@ entry:
ret i16 %result
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_lower_than_short_reverse
-; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
-; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
-; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GFX10: v_cvt_pk_i16_i32{{(_e64)?}} [[A:v[0-9]+]], {{v[0-9]+}}, [[B:v[0-9]+]]
-; GFX10: v_mov_b32_e32 [[B]], 0x100
-; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[B]]
define i16 @v_clamp_i64_i16_lower_than_short_reverse(i64 %in) #0 {
+; GFX678-LABEL: v_clamp_i64_i16_lower_than_short_reverse:
+; GFX678: ; %bb.0: ; %entry
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: v_cvt_pk_i16_i32_e32 v0, v0, v1
+; GFX678-NEXT: v_mov_b32_e32 v1, 0xffffff01
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x100
+; GFX678-NEXT: v_med3_i32 v0, v1, v0, v2
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_clamp_i64_i16_lower_than_short_reverse:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffff01
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x100
+; GFX9-NEXT: v_med3_i32 v0, v1, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_clamp_i64_i16_lower_than_short_reverse:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x100
+; GFX10-NEXT: v_med3_i32 v0, 0xffffff01, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_clamp_i64_i16_lower_than_short_reverse:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_pk_i16_i32 v0, v0, v1
+; GFX11-NEXT: v_mov_b32_e32 v1, 0x100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_med3_i32 v0, 0xffffff01, v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%max = call i64 @llvm.smax.i64(i64 %in, i64 -255)
%min = call i64 @llvm.smin.i64(i64 %max, i64 256)
@@ -103,10 +302,12 @@ entry:
ret i16 %result
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_zero
-; GFX6789: v_mov_b32_e32 v0, 0
-; GFX10: v_mov_b32_e32 v0, 0
define i16 @v_clamp_i64_i16_zero(i64 %in) #0 {
+; GCN-LABEL: v_clamp_i64_i16_zero:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
%max = call i64 @llvm.smax.i64(i64 %in, i64 0)
%min = call i64 @llvm.smin.i64(i64 %max, i64 0)
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