[llvm] [X86] combine-pclmul.ll - add tests showing failure to merge shuffles into X86ISD::PCLMULQDQ node control mask (PR #176741)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: Simon Pilgrim (RKSimon)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/176741.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/X86/combine-pclmul.ll (+39) 


``````````diff
diff --git a/llvm/test/CodeGen/X86/combine-pclmul.ll b/llvm/test/CodeGen/X86/combine-pclmul.ll
index e3cf8932ed8b0..1f52df3ebe91f 100644
--- a/llvm/test/CodeGen/X86/combine-pclmul.ll
+++ b/llvm/test/CodeGen/X86/combine-pclmul.ll
@@ -75,6 +75,45 @@ define <8 x i64> @test_concat_pclmulqdq_v8i64_v4i64(<8 x i64> %a0, <8 x i64> %a1
   ret <8 x i64> %res
 }
 
+define <2 x i64> @test_shuffle_pclmulqdq_v2i64(<2 x i64> %a0, <2 x i64> %a1) {
+; CHECK-LABEL: test_shuffle_pclmulqdq_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpbroadcastq %xmm0, %xmm0
+; CHECK-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; CHECK-NEXT:    vpclmulqdq $1, %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %s0 = shufflevector <2 x i64> %a0, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
+  %s1 = shufflevector <2 x i64> %a1, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
+  %clmul = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %s0, <2 x i64> %s1, i8 1)
+  ret <2 x i64> %clmul
+}
+
+define <4 x i64> @test_shuffle_pclmulqdq_v4i64(<4 x i64> %a0, <4 x i64> %a1) {
+; CHECK-LABEL: test_shuffle_pclmulqdq_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
+; CHECK-NEXT:    vpshufd {{.*#+}} ymm1 = ymm1[2,3,0,1,6,7,4,5]
+; CHECK-NEXT:    vpclmulqdq $16, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+  %s0 = shufflevector <4 x i64> %a0, <4 x i64> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+  %s1 = shufflevector <4 x i64> %a1, <4 x i64> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+  %clmul = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %s0, <4 x i64> %s1, i8 16)
+  ret <4 x i64> %clmul
+}
+
+define <8 x i64> @test_shuffle_pclmulqdq_v8i64(<8 x i64> %a0, <8 x i64> %a1) {
+; CHECK-LABEL: test_shuffle_pclmulqdq_v8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpshufd {{.*#+}} zmm0 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
+; CHECK-NEXT:    vpshufd {{.*#+}} zmm1 = zmm1[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
+; CHECK-NEXT:    vpclmulqdq $17, %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    retq
+  %s0 = shufflevector <8 x i64> %a0, <8 x i64> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+  %s1 = shufflevector <8 x i64> %a1, <8 x i64> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+  %clmul = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %s0, <8 x i64> %s1, i8 17)
+  ret <8 x i64> %clmul
+}
+
 define <2 x i64> @test_demanded_elts_pclmulqdq_0(<2 x i64> %a0, <2 x i64> %a1, i64 %s0, i64 %s1) {
 ; CHECK-LABEL: test_demanded_elts_pclmulqdq_0:
 ; CHECK:       # %bb.0:

``````````

</details>


https://github.com/llvm/llvm-project/pull/176741