[llvm] [RISCV][GISel] Support select G_INSERT_VECTOR_ELT (PR #176687)
Jianjian Guan via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 18 19:30:04 PST 2026
https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/176687
Depend on https://github.com/llvm/llvm-project/pull/171092
>From e68e77195918c68454c78095c0bfa1178880d680 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Mon, 8 Dec 2025 14:31:23 +0800
Subject: [PATCH 1/3] [RISCV][GISel] Support select G_INSERT_SUBVECTOR
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 64 ++-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +-
.../RISCV/GlobalISel/rvv/insert-subvector.ll | 411 ++++++++++++++++++
3 files changed, 476 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/rvv/insert-subvector.ll
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index bdd79e7e6a0db..6b5f076e1948d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -101,7 +101,7 @@ class RISCVInstructionSelector : public InstructionSelector {
MachineIRBuilder &MIB) const;
bool selectIntrinsic(MachineInstr &I, MachineIRBuilder &MIB) const;
bool selectExtractSubvector(MachineInstr &MI, MachineIRBuilder &MIB) const;
-
+ bool selectInsertSubVector(MachineInstr &I, MachineIRBuilder &MIB) const;
ComplexRendererFns selectShiftMask(MachineOperand &Root,
unsigned ShiftWidth) const;
ComplexRendererFns selectShiftMaskXLen(MachineOperand &Root) const {
@@ -1081,6 +1081,66 @@ bool RISCVInstructionSelector::selectExtractSubvector(
return true;
}
+bool RISCVInstructionSelector::selectInsertSubVector(
+ MachineInstr &MI, MachineIRBuilder &MIB) const {
+ assert(MI.getOpcode() == TargetOpcode::G_INSERT_SUBVECTOR);
+
+ Register DstReg = MI.getOperand(0).getReg();
+ Register VecReg = MI.getOperand(1).getReg();
+ Register SubVecReg = MI.getOperand(2).getReg();
+
+ LLT VecTy = MRI->getType(VecReg);
+ LLT SubVecTy = MRI->getType(SubVecReg);
+
+ MVT VecMVT = getMVTForLLT(VecTy);
+ MVT SubVecMVT = getMVTForLLT(SubVecTy);
+
+ unsigned Idx = static_cast<unsigned>(MI.getOperand(3).getImm());
+
+ unsigned SubRegIdx;
+ std::tie(SubRegIdx, Idx) =
+ RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
+ VecMVT, SubVecMVT, Idx, &TRI);
+
+ // If the Idx hasn't been completely eliminated then this is a subvector
+ // insert which doesn't naturally align to a vector register. These must
+ // be handled using instructions to manipulate the vector registers.
+ if (Idx != 0)
+ return false;
+
+ RISCVVType::VLMUL SubVecLMUL = RISCVTargetLowering::getLMUL(SubVecMVT);
+ [[maybe_unused]] bool IsSubVecPartReg =
+ SubVecLMUL == RISCVVType::VLMUL::LMUL_F2 ||
+ SubVecLMUL == RISCVVType::VLMUL::LMUL_F4 ||
+ SubVecLMUL == RISCVVType::VLMUL::LMUL_F8;
+
+ // Constrain dst
+ unsigned DstRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(VecMVT);
+ const TargetRegisterClass *DstRC = TRI.getRegClass(DstRegClassID);
+ if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
+ return false;
+
+ // If we haven't set a SubRegIdx, then we must be going between
+ // equally-sized LMUL groups (e.g. VR -> VR). This can be done as a copy.
+ if (SubRegIdx == RISCV::NoSubRegister) {
+ assert(RISCVTargetLowering::getRegClassIDForVecVT(SubVecMVT) ==
+ DstRegClassID &&
+ "Unexpected subvector insert");
+ MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(SubVecReg);
+ MI.eraseFromParent();
+ return true;
+ }
+
+ // Use INSERT_SUBREG to insert the subvector into the vector at the
+ // appropriate subregister index.
+ auto Ins =
+ MIB.buildInstr(TargetOpcode::INSERT_SUBREG, {DstReg}, {VecReg, SubVecReg})
+ .addImm(SubRegIdx);
+
+ MI.eraseFromParent();
+ return constrainSelectedInstRegOperands(*Ins, TII, TRI, RBI);
+}
+
bool RISCVInstructionSelector::select(MachineInstr &MI) {
MachineIRBuilder MIB(MI);
@@ -1357,6 +1417,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
return selectIntrinsic(MI, MIB);
case TargetOpcode::G_EXTRACT_SUBVECTOR:
return selectExtractSubvector(MI, MIB);
+ case TargetOpcode::G_INSERT_SUBVECTOR:
+ return selectInsertSubVector(MI, MIB);
default:
return false;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3e34954c324d2..53617101c6cd1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -25783,7 +25783,8 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
return false;
}
- if (II->getIntrinsicID() == Intrinsic::vector_extract)
+ if (II->getIntrinsicID() == Intrinsic::vector_extract ||
+ II->getIntrinsicID() == Intrinsic::vector_insert)
return false;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insert-subvector.ll
new file mode 100644
index 0000000000000..571e3bd25d1b0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insert-subvector.ll
@@ -0,0 +1,411 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv8i32_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv2r.v v8, v12
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
+ ret <vscale x 8 x i32> %v
+}
+
+define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv8i32_nxv4i32_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv2r.v v10, v12
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)
+ ret <vscale x 8 x i32> %v
+}
+
+define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv8i32_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v8, v12
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)
+ ret <vscale x 8 x i32> %v
+}
+
+define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv8i32_nxv2i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v9, v12
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)
+ ret <vscale x 8 x i32> %v
+}
+
+define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv8i32_nxv2i32_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v12
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)
+ ret <vscale x 8 x i32> %v
+}
+
+define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv8i32_nxv2i32_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v11, v12
+; CHECK-NEXT: ret
+ %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)
+ ret <vscale x 8 x i32> %v
+}
+
+define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_0(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {
+; CHECK-LABEL: insert_nxv1i8_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)
+ ret <vscale x 4 x i8> %v
+}
+
+define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {
+; CHECK-LABEL: insert_nxv1i8_nxv4i8_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 3
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: mul a1, a0, a1
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
+ ret <vscale x 4 x i8> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 0)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv8i32_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv4r.v v12, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 8)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv2r.v v8, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv4i32_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv2r.v v10, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv4i32_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv2r.v v12, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 8)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv4i32_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv2r.v v14, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 12)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v8, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv2i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v9, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv2i32_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv2i32_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v11, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv2i32_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v12, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 8)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv2i32_10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v13, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 10)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv2i32_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v14, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 12)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv2i32_14:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v15, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 14)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vmv.v.v v8, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 0)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: add a1, a0, a0
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a0
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 1)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_6(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
+; CHECK-LABEL: insert_nxv16i32_nxv1i32_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vmv.v.v v11, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 6)
+ ret <vscale x 16 x i32> %v
+}
+
+define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_0(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
+; CHECK-LABEL: insert_nxv16i8_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)
+ ret <vscale x 16 x i8> %v
+}
+
+define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_1(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
+; CHECK-LABEL: insert_nxv16i8_nxv1i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: add a1, a0, a0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a0
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 1)
+ ret <vscale x 16 x i8> %v
+}
+
+define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_2(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
+; CHECK-LABEL: insert_nxv16i8_nxv1i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a1, a0, 3
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a0
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 2)
+ ret <vscale x 16 x i8> %v
+}
+
+define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
+; CHECK-LABEL: insert_nxv16i8_nxv1i8_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 3
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: mul a1, a0, a1
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
+ ret <vscale x 16 x i8> %v
+}
+
+define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_7(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
+; CHECK-LABEL: insert_nxv16i8_nxv1i8_7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: li a1, 7
+; CHECK-NEXT: mul a1, a0, a1
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 7)
+ ret <vscale x 16 x i8> %v
+}
+
+define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_15(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
+; CHECK-LABEL: insert_nxv16i8_nxv1i8_15:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: li a1, 7
+; CHECK-NEXT: mul a1, a0, a1
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v10, a1
+; CHECK-NEXT: ret
+ %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 15)
+ ret <vscale x 16 x i8> %v
+}
+
+define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_0(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
+; CHECK-LABEL: insert_nxv32f16_nxv2f16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vmv.v.v v8, v16
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 0)
+ ret <vscale x 32 x half> %v
+}
+
+define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_2(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
+; CHECK-LABEL: insert_nxv32f16_nxv2f16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a1, a0, a0
+; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a0
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 2)
+ ret <vscale x 32 x half> %v
+}
+
+define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_26(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
+; CHECK-LABEL: insert_nxv32f16_nxv2f16_26:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a1, a0, a0
+; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v14, v16, a0
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26)
+ ret <vscale x 32 x half> %v
+}
+
+define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) {
+; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> poison, <vscale x 1 x half> %subvec, i64 0)
+ ret <vscale x 32 x half> %v
+}
+
+define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_26(<vscale x 1 x half> %subvec) {
+; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_26:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: srli a1, a0, 3
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v14, v8, a0
+; CHECK-NEXT: ret
+ %v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> poison, <vscale x 1 x half> %subvec, i64 26)
+ ret <vscale x 32 x half> %v
+}
>From eb4a6408ac0d1e8e918b8ac4da07fd1deb55268f Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Fri, 19 Dec 2025 15:16:03 +0800
Subject: [PATCH 2/3] Address comment
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 6 ------
1 file changed, 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 6b5f076e1948d..f745bda54a452 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1108,12 +1108,6 @@ bool RISCVInstructionSelector::selectInsertSubVector(
if (Idx != 0)
return false;
- RISCVVType::VLMUL SubVecLMUL = RISCVTargetLowering::getLMUL(SubVecMVT);
- [[maybe_unused]] bool IsSubVecPartReg =
- SubVecLMUL == RISCVVType::VLMUL::LMUL_F2 ||
- SubVecLMUL == RISCVVType::VLMUL::LMUL_F4 ||
- SubVecLMUL == RISCVVType::VLMUL::LMUL_F8;
-
// Constrain dst
unsigned DstRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(VecMVT);
const TargetRegisterClass *DstRC = TRI.getRegClass(DstRegClassID);
>From d9a84f953b96c354b2eb1a8a72362af125a5774f Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Wed, 22 Oct 2025 16:22:25 +0800
Subject: [PATCH 3/3] [RISCV][GISel] Support select G_INSERT_VECTOR_ELT
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 13 +
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 105 +-
.../Target/RISCV/GISel/RISCVLegalizerInfo.h | 2 +
.../GISel/RISCVPostLegalizerCombiner.cpp | 41 +
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 17 +
llvm/lib/Target/RISCV/RISCVCombine.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrGISel.td | 22 +
.../rvv/legalize-insertelement-rv32.mir | 591 +++++++----
.../rvv/legalize-insertelement-rv64.mir | 592 +++++++----
.../RISCV/GlobalISel/rvv/insertelt-fp.ll | 515 ++++++++++
.../GlobalISel/rvv/insertelt-int-rv32.ll | 952 ++++++++++++++++++
.../GlobalISel/rvv/insertelt-int-rv64.ll | 759 ++++++++++++++
12 files changed, 3178 insertions(+), 432 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-fp.ll
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-int-rv32.ll
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-int-rv64.ll
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index f745bda54a452..e90eda6a798c7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1478,6 +1478,19 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
MRI->setType(DstReg, sXLen);
break;
}
+ case RISCV::G_VMV_S_VL: {
+ Register ScalarReg = MI.getOperand(2).getReg();
+ if (isRegInFprb(ScalarReg))
+ MI.setDesc(TII.get(RISCV::G_VFMV_S_F_VL));
+ else {
+ const LLT sXLen = LLT::scalar(STI.getXLen());
+ auto AnyExt = MIB.buildInstr(TargetOpcode::COPY, {sXLen}, {ScalarReg});
+ RBI.constrainGenericRegister(AnyExt.getReg(0), RISCV::GPRRegClass, *MRI);
+ MI.getOperand(2).setReg(AnyExt.getReg(0));
+ MI.setDesc(TII.get(RISCV::G_VMV_S_X_VL));
+ }
+ break;
+ }
}
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index ae43fccf8e818..b9179f1e1c88f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -733,10 +733,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
};
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
- .legalIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
- InsertVectorEltPred, typeIs(2, sXLen)))
- .legalIf(all(typeIsLegalBoolVec(0, BoolVecTys, ST), InsertVectorEltPred,
- typeIs(2, sXLen)));
+ .customIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
+ InsertVectorEltPred, typeIs(2, sXLen)))
+ .customIf(all(typeIsLegalBoolVec(0, BoolVecTys, ST), InsertVectorEltPred,
+ typeIs(2, sXLen)));
getLegacyLegalizerInfo().computeTables();
verify(*ST.getInstrInfo());
@@ -1361,6 +1361,101 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
return true;
}
+static std::optional<LLT>
+getSmallestVectorTypeForIndex(LLT VecTy, unsigned MaxIdx,
+ const RISCVSubtarget &Subtarget) {
+ MVT VecVT = getMVTForLLT(VecTy);
+ assert(VecVT.isScalableVector());
+ const unsigned EltSize = VecVT.getScalarSizeInBits();
+ const unsigned VectorBitsMin = Subtarget.getRealMinVLen();
+ const unsigned MinVLMAX = VectorBitsMin / EltSize;
+ MVT SmallerVT;
+ if (MaxIdx < MinVLMAX)
+ SmallerVT = RISCVTargetLowering::getM1VT(VecVT);
+ else if (MaxIdx < MinVLMAX * 2)
+ SmallerVT =
+ RISCVTargetLowering::getM1VT(VecVT).getDoubleNumVectorElementsVT();
+ else if (MaxIdx < MinVLMAX * 4)
+ SmallerVT = RISCVTargetLowering::getM1VT(VecVT)
+ .getDoubleNumVectorElementsVT()
+ .getDoubleNumVectorElementsVT();
+ if (!SmallerVT.isValid() || !VecVT.bitsGT(SmallerVT))
+ return std::nullopt;
+ return getLLTForMVT(SmallerVT);
+}
+
+bool RISCVLegalizerInfo::legalizeInsertVectotElt(MachineInstr &MI,
+ LegalizerHelper &Helper,
+ MachineIRBuilder &MIB) const {
+ MachineOperand &Dst = MI.getOperand(0); // Destination vector
+ MachineOperand &Src = MI.getOperand(1); // Source vector
+ MachineOperand &Elt = MI.getOperand(2); // Element to insert
+ MachineOperand &Idx = MI.getOperand(3); // Index to insert at
+ MachineRegisterInfo &MRI = *MIB.getMRI();
+
+ Register Vec = Src.getReg();
+
+ LLT OrigVecTy = MRI.getType(Vec);
+ LLT ContainerTy = OrigVecTy;
+
+ // If we know the index we're going to insert at, we can shrink Vec so that
+ // we're performing the scalar inserts and slideup on a smaller LMUL.
+ std::optional<unsigned> AlignedIdx;
+ if (auto IdxConst = getIConstantVRegValWithLookThrough(Idx.getReg(), MRI)) {
+ unsigned IdxVal = IdxConst->Value.getZExtValue();
+
+ // Do we know an upper bound on LMUL?
+ if (auto ShrunkTy = getSmallestVectorTypeForIndex(OrigVecTy, IdxVal, STI)) {
+ ContainerTy = *ShrunkTy;
+ AlignedIdx = 0;
+ }
+
+ if (AlignedIdx)
+ Vec = MIB.buildExtractSubvector(ContainerTy, Src, *AlignedIdx).getReg(0);
+ }
+
+ // TODO: i64 in rv32
+
+ auto [Mask, VL] = buildDefaultVLOps(ContainerTy, MIB, MRI);
+
+ if (auto IdxConst = getIConstantVRegValWithLookThrough(Idx.getReg(), MRI)) {
+ unsigned IdxVal = IdxConst->Value.getZExtValue();
+ // For zero index, only need vmv.
+ if (IdxVal == 0) {
+ auto VMVOp =
+ MIB.buildInstr(RISCV::G_VMV_S_VL, {ContainerTy}, {Vec, Elt, VL});
+ if (AlignedIdx)
+ VMVOp = MIB.buildInsertSubvector(OrigVecTy, Src, VMVOp, *AlignedIdx);
+ VMVOp->getOperand(0).setReg(Dst.getReg());
+ MI.eraseFromParent();
+ return true;
+ }
+ }
+
+ auto VMVOp = MIB.buildInstr(RISCV::G_VMV_S_VL, {ContainerTy},
+ {MIB.buildUndef(ContainerTy), Elt, VL});
+
+ // InSertVL
+ const LLT sXLen = LLT::scalar(STI.getXLen());
+ auto CstOne = MIB.buildConstant(sXLen, 1);
+ auto Add = MIB.buildAdd(sXLen, Idx, CstOne);
+
+ // Build Slide
+ unsigned Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED;
+
+ auto Slideup = MIB.buildInstr(RISCV::G_VSLIDEUP_VL, {ContainerTy},
+ {Vec, VMVOp, Idx, Mask, Add})
+ .addImm(Policy);
+
+ if (AlignedIdx)
+ Slideup = MIB.buildInsertSubvector(OrigVecTy, Src, Slideup, *AlignedIdx);
+
+ Slideup->getOperand(0).setReg(Dst.getReg());
+
+ MI.eraseFromParent();
+ return true;
+}
+
static unsigned getRISCVWOpcode(unsigned Opcode) {
switch (Opcode) {
default:
@@ -1552,6 +1647,8 @@ bool RISCVLegalizerInfo::legalizeCustom(
case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE:
return legalizeLoadStore(MI, Helper, MIRBuilder);
+ case TargetOpcode::G_INSERT_VECTOR_ELT:
+ return legalizeInsertVectotElt(MI, Helper, MIRBuilder);
}
llvm_unreachable("expected switch to return");
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index 4451866745194..2b8e84cb812c0 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -52,6 +52,8 @@ class RISCVLegalizerInfo : public LegalizerInfo {
MachineIRBuilder &MIB) const;
bool legalizeLoadStore(MachineInstr &MI, LegalizerHelper &Helper,
MachineIRBuilder &MIB) const;
+ bool legalizeInsertVectotElt(MachineInstr &MI, LegalizerHelper &Helper,
+ MachineIRBuilder &MIB) const;
};
} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
index f2b216be1db15..79ed68adb39c7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
@@ -111,6 +111,8 @@ class RISCVPostLegalizerCombinerImpl : public Combiner {
bool tryCombineAll(MachineInstr &I) const override;
+ bool tryCombineAllImpl(MachineInstr &I) const;
+
private:
#define GET_GICOMBINER_CLASS_MEMBERS
#include "RISCVGenPostLegalizeGICombiner.inc"
@@ -136,6 +138,45 @@ RISCVPostLegalizerCombinerImpl::RISCVPostLegalizerCombinerImpl(
{
}
+bool RISCVPostLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
+ if (tryCombineAllImpl(MI))
+ return true;
+
+ switch (MI.getOpcode()) {
+ case RISCV::G_VMV_S_VL: {
+ MachineRegisterInfo &MRI = *Helper.getBuilder().getMRI();
+ MachineOperand &Dst = MI.getOperand(0);
+ MachineOperand &Src = MI.getOperand(1);
+ MachineOperand &Elt = MI.getOperand(2);
+ MachineOperand &VL = MI.getOperand(3);
+ Register Vec = Src.getReg();
+
+ LLT VecTy = MRI.getType(Vec);
+
+ MVT VecTyMVT = getMVTForLLT(VecTy);
+ const MVT M1VT = RISCVTargetLowering::getM1VT(VecTyMVT);
+ LLT M1VecTy = getLLTForMVT(M1VT);
+
+ // Use M1 or smaller to avoid over constraining register allocation
+ if (M1VT.bitsLT(VecTyMVT)) {
+ auto M1Passthru =
+ Helper.getBuilder().buildExtractSubvector(M1VecTy, Vec, 0);
+ auto M1VMVOp = Helper.getBuilder().buildInstr(
+ RISCV::G_VMV_S_VL, {M1VecTy}, {M1Passthru, Elt, VL});
+ Helper.getBuilder().buildInsertSubvector(
+ Dst, Helper.getBuilder().buildUndef(VecTy), M1VMVOp, 0);
+
+ MI.eraseFromParent();
+ return true;
+ }
+
+ return false;
+ }
+ default:
+ return false;
+ }
+}
+
class RISCVPostLegalizerCombiner : public MachineFunctionPass {
public:
static char ID;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 1bb197cb44b5d..dbe35a452b4fe 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -522,6 +522,23 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[1] = GPRValueMapping;
break;
}
+ case RISCV::G_VMV_S_VL: {
+ OpdsMapping[0] = getVRBValueMapping(MRI.getType(MI.getOperand(2).getReg())
+ .getSizeInBits()
+ .getKnownMinValue());
+ OpdsMapping[1] = OpdsMapping[0];
+
+ // The element may be either a GPR or FPR. Preserve that behaviour.
+ if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &RISCV::FPRBRegBank)
+ OpdsMapping[2] = getFPValueMapping(
+ MRI.getType(MI.getOperand(2).getReg()).getSizeInBits());
+ else
+ OpdsMapping[2] = GPRValueMapping;
+
+ // Index needs to be a GPR.
+ OpdsMapping[3] = GPRValueMapping;
+ break;
+ }
case TargetOpcode::G_INTRINSIC: {
Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
diff --git a/llvm/lib/Target/RISCV/RISCVCombine.td b/llvm/lib/Target/RISCV/RISCVCombine.td
index a06b60d8cce07..95887bebc3792 100644
--- a/llvm/lib/Target/RISCV/RISCVCombine.td
+++ b/llvm/lib/Target/RISCV/RISCVCombine.td
@@ -35,4 +35,5 @@ def RISCVPostLegalizerCombiner
identity_combines, shift_immed_chain,
commute_constant_to_rhs, simplify_neg_minmax,
fold_fp_zero_store]> {
+ let CombineAllMethodName = "tryCombineAllImpl";
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
index bd3ecd737bede..6ee54736a071f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
@@ -169,6 +169,28 @@ def G_VMV_V_V_VL : RISCVGenericInstruction {
}
def : GINodeEquiv<G_VMV_V_V_VL, riscv_vmv_v_v_vl>;
+def G_VMV_S_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$passthru, type0:$src, type1:$vl);
+ let hasSideEffects = false;
+}
+
+// Pseudo equivalent to a RISCVISD::VMV_S_X_VL
+def G_VMV_S_X_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$passthru, type0:$src, type1:$vl);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VMV_S_X_VL, riscv_vmv_s_x_vl>;
+
+// Pseudo equivalent to a RISCVISD::VFMV_S_F_VL
+def G_VFMV_S_F_VL : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$passthru, type0:$src, type1:$vl);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VFMV_S_F_VL, riscv_vfmv_s_f_vl>;
+
// Pseudo equivalent to a RISCVISD::VSLIDEUP_VL
def G_VSLIDEUP_VL : RISCVGenericInstruction {
let OutOperandList = (outs type0:$dst);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv32.mir
index d7c0e80b11264..576304acea05a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv32.mir
@@ -11,9 +11,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -32,9 +33,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -58,8 +60,13 @@ body: |
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[COPY1]](s32), [[VMSET_VL]](<vscale x 1 x s1>), [[ADD]](s32), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%2:_(s32) = COPY $x10
%0:_(s1) = G_TRUNC %2(s32)
@@ -80,8 +87,12 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C2]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[C1]](s32), [[VMSET_VL]](<vscale x 2 x s1>), [[C3]](s32), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -100,9 +111,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -126,8 +138,13 @@ body: |
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[COPY1]](s32), [[VMSET_VL]](<vscale x 2 x s1>), [[ADD]](s32), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%2:_(s32) = COPY $x10
%0:_(s1) = G_TRUNC %2(s32)
@@ -148,8 +165,12 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C2]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[C1]](s32), [[VMSET_VL]](<vscale x 4 x s1>), [[C3]](s32), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -168,9 +189,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -193,9 +215,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(s32) = COPY $x10
%0:_(s1) = G_TRUNC %1(s32)
@@ -215,9 +238,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -236,9 +260,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -262,8 +287,13 @@ body: |
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[COPY1]](s32), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s32), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%2:_(s32) = COPY $x10
%0:_(s1) = G_TRUNC %2(s32)
@@ -284,8 +314,12 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C2]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[C1]](s32), [[VMSET_VL]](<vscale x 16 x s1>), [[C3]](s32), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -304,9 +338,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -330,8 +365,13 @@ body: |
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[COPY1]](s32), [[VMSET_VL]](<vscale x 16 x s1>), [[ADD]](s32), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%2:_(s32) = COPY $x10
%0:_(s1) = G_TRUNC %2(s32)
@@ -355,9 +395,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s32)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMV_S_VL [[COPY]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 4 x s1>) = COPY $v0
%2:_(s32) = COPY $x10
@@ -377,9 +418,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -398,9 +440,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -423,9 +466,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s32) = COPY $x10
%0:_(s8) = G_TRUNC %1(s32)
@@ -445,9 +489,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -466,9 +511,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -491,9 +537,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s32) = COPY $x10
%0:_(s8) = G_TRUNC %1(s32)
@@ -513,9 +560,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -534,9 +582,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -559,9 +608,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s32) = COPY $x10
%0:_(s8) = G_TRUNC %1(s32)
@@ -581,9 +631,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 8 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -602,9 +653,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 8 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -627,9 +679,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 8 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s32) = COPY $x10
%0:_(s8) = G_TRUNC %1(s32)
@@ -649,9 +702,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s8>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 8 x s8>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -670,9 +726,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s8>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 8 x s8>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -696,8 +755,13 @@ body: |
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[COPY1]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 16 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 16 x s8>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[COPY1]](s32), [[VMSET_VL]](<vscale x 16 x s1>), [[ADD]](s32), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[VSLIDEUP_VL]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%2:_(s32) = COPY $x10
%0:_(s8) = G_TRUNC %2(s32)
@@ -724,9 +788,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VMV_S_VL [[COPY]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(<vscale x 4 x s8>) = COPY $v8
%2:_(s32) = COPY $x10
@@ -746,9 +811,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -767,9 +833,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -792,9 +859,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %1(s32)
@@ -815,8 +883,12 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C2]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s16>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[C1]](s32), [[VMSET_VL]](<vscale x 2 x s1>), [[C3]](s32), 0
+ ; CHECK-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -835,9 +907,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -860,9 +933,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %1(s32)
@@ -882,9 +956,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -903,9 +978,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -928,9 +1004,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %1(s32)
@@ -950,9 +1027,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s16>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -971,9 +1051,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s16>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -996,9 +1079,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s16>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %1(s32)
@@ -1018,9 +1104,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s16>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -1039,9 +1128,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s16>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -1064,9 +1156,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s16>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %1(s32)
@@ -1090,9 +1185,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[COPY]], [[TRUNC]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(<vscale x 4 x s16>) = COPY $v8
%2:_(s32) = COPY $x10
@@ -1111,8 +1207,10 @@ body: |
; CHECK-LABEL: name: insertelement_nxv1i32_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s32>) = G_VMV_S_VL [[DEF]], [[C]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1129,9 +1227,9 @@ body: |
; CHECK-LABEL: name: insertelement_nxv1i32_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>)
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s32>) = G_VMV_S_VL [[DEF]], [[C]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1153,9 +1251,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s32>) = G_VMV_S_VL [[DEF]], [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(s32) = COPY $x10
%2:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
@@ -1173,8 +1272,10 @@ body: |
; CHECK-LABEL: name: insertelement_nxv2i32_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[DEF]], [[C]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1191,9 +1292,9 @@ body: |
; CHECK-LABEL: name: insertelement_nxv2i32_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[DEF]], [[C]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1215,9 +1316,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[DEF]], [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(s32) = COPY $x10
%2:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
@@ -1235,8 +1337,12 @@ body: |
; CHECK-LABEL: name: insertelement_nxv4i32_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1253,9 +1359,11 @@ body: |
; CHECK-LABEL: name: insertelement_nxv4i32_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s32>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1277,9 +1385,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s32>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(s32) = COPY $x10
%2:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
@@ -1297,8 +1408,12 @@ body: |
; CHECK-LABEL: name: insertelement_nxv8i32_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1315,9 +1430,11 @@ body: |
; CHECK-LABEL: name: insertelement_nxv8i32_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1339,9 +1456,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(s32) = COPY $x10
%2:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
@@ -1359,8 +1479,12 @@ body: |
; CHECK-LABEL: name: insertelement_nxv16i32_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1377,9 +1501,11 @@ body: |
; CHECK-LABEL: name: insertelement_nxv16i32_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1401,9 +1527,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%0:_(s32) = COPY $x10
%2:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
@@ -1425,9 +1554,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x s32>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[COPY1]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(<vscale x 4 x s32>) = COPY $v8m2
%1:_(s32) = COPY $x10
@@ -1446,8 +1578,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[DEF]], [[MV]], [[C1]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 0
@@ -1466,9 +1600,9 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C1]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>)
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[DEF]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 -1
@@ -1492,9 +1626,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[DEF]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
@@ -1515,8 +1650,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 2 x s64>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 0
@@ -1535,9 +1674,11 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C1]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 2 x s64>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 -1
@@ -1561,9 +1702,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 2 x s64>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
@@ -1584,8 +1728,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s64>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 0
@@ -1604,9 +1752,11 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C1]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s64>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 -1
@@ -1630,9 +1780,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s64>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
@@ -1653,8 +1806,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C1]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 0
@@ -1673,9 +1830,11 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C1]](s32)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 -1
@@ -1699,9 +1858,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
@@ -1727,9 +1889,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], [[MV]](s64), [[C]](s32)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x s64>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[MV]], [[C]](s32)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(<vscale x 4 x s64>) = COPY $v8m4
%2:_(s32) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv64.mir
index 4c33ddccdac95..d98e83918d809 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv64.mir
@@ -11,9 +11,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -32,9 +33,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -60,8 +62,13 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[AND]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND]], [[C2]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[AND]](s64), [[VMSET_VL]](<vscale x 1 x s1>), [[ADD]](s64), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 1 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%2:_(s64) = COPY $x10
%0:_(s1) = G_TRUNC %2(s64)
@@ -84,8 +91,12 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C2]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C2]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[C1]](s64), [[VMSET_VL]](<vscale x 2 x s1>), [[C3]](s64), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -104,9 +115,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -132,8 +144,13 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[AND]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND]], [[C2]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[AND]](s64), [[VMSET_VL]](<vscale x 2 x s1>), [[ADD]](s64), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%2:_(s64) = COPY $x10
%0:_(s1) = G_TRUNC %2(s64)
@@ -156,8 +173,12 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C2]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C2]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[C1]](s64), [[VMSET_VL]](<vscale x 4 x s1>), [[C3]](s64), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -176,9 +197,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -201,9 +223,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(s64) = COPY $x10
%0:_(s1) = G_TRUNC %1(s64)
@@ -223,9 +246,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -244,9 +268,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -272,8 +297,13 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[AND]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND]], [[C2]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[AND]](s64), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s64), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 8 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%2:_(s64) = COPY $x10
%0:_(s1) = G_TRUNC %2(s64)
@@ -296,8 +326,12 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C2]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C2]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[C1]](s64), [[VMSET_VL]](<vscale x 16 x s1>), [[C3]](s64), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 false
@@ -316,9 +350,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%1:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
%2:_(s1) = G_CONSTANT i1 true
@@ -344,8 +379,13 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[AND]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND]], [[C2]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[AND]](s64), [[VMSET_VL]](<vscale x 16 x s1>), [[ADD]](s64), 0
+ ; CHECK-NEXT: $v0 = COPY [[VSLIDEUP_VL]](<vscale x 16 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%2:_(s64) = COPY $x10
%0:_(s1) = G_TRUNC %2(s64)
@@ -371,9 +411,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s64)
- ; CHECK-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMV_S_VL [[COPY]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v0 = COPY [[VMV_S_VL]](<vscale x 4 x s1>)
; CHECK-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 4 x s1>) = COPY $v0
%2:_(s64) = COPY $x10
@@ -393,9 +434,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -414,9 +456,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -439,9 +482,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
@@ -461,9 +505,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -482,9 +527,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -507,9 +553,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
@@ -529,9 +576,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -550,9 +598,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -575,9 +624,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
@@ -597,9 +647,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 8 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -618,9 +669,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 8 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -643,9 +695,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 8 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %1(s64)
@@ -665,9 +718,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s8>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 8 x s8>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 0
@@ -686,9 +742,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s8>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 8 x s8>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
%2:_(s8) = G_CONSTANT i8 -1
@@ -712,8 +771,13 @@ body: |
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[COPY1]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 16 x s8>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 16 x s8>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[COPY1]](s64), [[VMSET_VL]](<vscale x 16 x s1>), [[ADD]](s64), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[VSLIDEUP_VL]](<vscale x 16 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%2:_(s64) = COPY $x10
%0:_(s8) = G_TRUNC %2(s64)
@@ -737,9 +801,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VMV_S_VL [[COPY]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s8>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(<vscale x 4 x s8>) = COPY $v8
%2:_(s64) = COPY $x10
@@ -759,9 +824,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -780,9 +846,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -805,9 +872,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
@@ -828,8 +896,12 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C2]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C2]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s16>) = G_VSLIDEUP_VL [[DEF]], [[VMV_S_VL]], [[C1]](s64), [[VMSET_VL]](<vscale x 2 x s1>), [[C3]](s64), 0
+ ; CHECK-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -848,9 +920,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -873,9 +946,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
@@ -895,9 +969,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -916,9 +991,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -941,9 +1017,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
@@ -963,9 +1040,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s16>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -984,9 +1064,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s16>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -1009,9 +1092,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s16>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
@@ -1031,9 +1117,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s16>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 0
@@ -1052,9 +1141,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s16>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
%2:_(s16) = G_CONSTANT i16 -1
@@ -1077,9 +1169,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s16>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 4 x s16>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %1(s64)
@@ -1103,9 +1198,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_S_VL [[COPY]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 4 x s16>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(<vscale x 4 x s16>) = COPY $v8
%2:_(s64) = COPY $x10
@@ -1125,9 +1221,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s32>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1146,9 +1243,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s32>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1171,9 +1269,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s32>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
@@ -1193,9 +1292,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1214,9 +1314,10 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1239,9 +1340,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[DEF]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 2 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
@@ -1261,9 +1363,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1282,9 +1387,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1307,9 +1415,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s32>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
@@ -1329,9 +1440,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1350,9 +1464,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1375,9 +1492,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
@@ -1397,9 +1517,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 0
@@ -1418,9 +1541,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
%2:_(s32) = G_CONSTANT i32 -1
@@ -1443,9 +1569,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 16 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(s64) = COPY $x10
%0:_(s32) = G_TRUNC %1(s64)
@@ -1469,9 +1598,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s32), [[C]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x s32>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[TRUNC]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_S_VL]](<vscale x 2 x s32>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s32>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(<vscale x 4 x s32>) = COPY $v8m2
%2:_(s64) = COPY $x10
@@ -1490,8 +1622,10 @@ body: |
; CHECK-LABEL: name: insertelement_nxv1i64_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[DEF]], [[C]], [[C1]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 0
@@ -1508,9 +1642,9 @@ body: |
; CHECK-LABEL: name: insertelement_nxv1i64_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>)
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[DEF]], [[C]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8
%1:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 -1
@@ -1532,9 +1666,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)
- ; CHECK-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[DEF]], [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: $v8 = COPY [[VMV_S_VL]](<vscale x 1 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(s64) = COPY $x10
%2:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
@@ -1552,8 +1687,12 @@ body: |
; CHECK-LABEL: name: insertelement_nxv2i64_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 2 x s64>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 0
@@ -1570,9 +1709,11 @@ body: |
; CHECK-LABEL: name: insertelement_nxv2i64_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 2 x s64>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%1:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 -1
@@ -1594,9 +1735,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)
- ; CHECK-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 2 x s64>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m2 = COPY [[INSERT_SUBVECTOR]](<vscale x 2 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(s64) = COPY $x10
%2:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
@@ -1614,8 +1758,12 @@ body: |
; CHECK-LABEL: name: insertelement_nxv4i64_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s64>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 0
@@ -1632,9 +1780,11 @@ body: |
; CHECK-LABEL: name: insertelement_nxv4i64_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s64>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%1:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 -1
@@ -1656,9 +1806,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)
- ; CHECK-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s64>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(s64) = COPY $x10
%2:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
@@ -1676,8 +1829,12 @@ body: |
; CHECK-LABEL: name: insertelement_nxv8i64_0
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C1]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 0
@@ -1694,9 +1851,11 @@ body: |
; CHECK-LABEL: name: insertelement_nxv8i64_1
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 0
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[C]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%1:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
%2:_(s64) = G_CONSTANT i64 -1
@@ -1718,9 +1877,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)
- ; CHECK-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s64)
+ ; CHECK-NEXT: [[VMV_S_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_VMV_S_VL [[EXTRACT_SUBVECTOR]], [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR [[DEF]], [[VMV_S_VL]](<vscale x 1 x s64>), 0
+ ; CHECK-NEXT: $v8m8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s64>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%0:_(s64) = COPY $x10
%2:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-fp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-fp.ll
new file mode 100644
index 0000000000000..4748d12341d80
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-fp.ll
@@ -0,0 +1,515 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zfbfmin,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \
+; RUN: -global-isel -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zfbfmin,+zvfh,+zvfbfmin,+v -target-abi=lp64d \
+; RUN: -global-isel -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv1f16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x half> %v, half %elt, i32 0
+ ret <vscale x 1 x half> %r
+}
+
+define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv1f16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
+ ret <vscale x 1 x half> %r
+}
+
+define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv1f16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
+ ret <vscale x 1 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv2f16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
+ ret <vscale x 2 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv2f16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
+ ret <vscale x 2 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv2f16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
+ ret <vscale x 2 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv4f16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
+ ret <vscale x 4 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv4f16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
+ ret <vscale x 4 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv4f16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
+ ret <vscale x 4 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv8f16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
+ ret <vscale x 8 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv8f16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v10, fa0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
+ ret <vscale x 8 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv8f16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v10, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
+ ret <vscale x 8 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv16f16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
+ ret <vscale x 16 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv16f16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v12, fa0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
+ ret <vscale x 16 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv16f16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v12, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
+ ret <vscale x 16 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv32f16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
+ ret <vscale x 32 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv32f16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v16, fa0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x half> %v, half %elt, i32 3
+ ret <vscale x 32 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv32f16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v16, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
+ ret <vscale x 32 x half> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv1f32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x float> %v, float %elt, i32 0
+ ret <vscale x 1 x float> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv1f32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x float> %v, float %elt, i32 3
+ ret <vscale x 1 x float> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv1f32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
+ ret <vscale x 1 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv2f32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x float> %v, float %elt, i32 0
+ ret <vscale x 2 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv2f32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x float> %v, float %elt, i32 3
+ ret <vscale x 2 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv2f32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
+ ret <vscale x 2 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv4f32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x float> %v, float %elt, i32 0
+ ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv4f32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v10, fa0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x float> %v, float %elt, i32 3
+ ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, float %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv4f32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v10, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
+ ret <vscale x 4 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv8f32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x float> %v, float %elt, i32 0
+ ret <vscale x 8 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv8f32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v12, fa0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x float> %v, float %elt, i32 3
+ ret <vscale x 8 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, float %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv8f32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v12, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
+ ret <vscale x 8 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv16f32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x float> %v, float %elt, i32 0
+ ret <vscale x 16 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv16f32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v16, fa0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x float> %v, float %elt, i32 3
+ ret <vscale x 16 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_idx(<vscale x 16 x float> %v, float %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv16f32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v16, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx
+ ret <vscale x 16 x float> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv1f64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x double> %v, double %elt, i32 0
+ ret <vscale x 1 x double> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv1f64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x double> %v, double %elt, i32 3
+ ret <vscale x 1 x double> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv1f64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
+ ret <vscale x 1 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv2f64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x double> %v, double %elt, i32 0
+ ret <vscale x 2 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv2f64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vfmv.s.f v10, fa0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x double> %v, double %elt, i32 3
+ ret <vscale x 2 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, double %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv2f64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v10, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
+ ret <vscale x 2 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv4f64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x double> %v, double %elt, i32 0
+ ret <vscale x 4 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv4f64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vfmv.s.f v12, fa0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x double> %v, double %elt, i32 3
+ ret <vscale x 4 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, double %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv4f64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v12, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
+ ret <vscale x 4 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv8f64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x double> %v, double %elt, i32 0
+ ret <vscale x 8 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv8f64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vfmv.s.f v16, fa0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x double> %v, double %elt, i32 3
+ ret <vscale x 8 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_idx(<vscale x 8 x double> %v, double %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv8f64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v16, fa0
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x double> %v, double %elt, i32 %idx
+ ret <vscale x 8 x double> %r
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-int-rv32.ll
new file mode 100644
index 0000000000000..7f817b97dbe4b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-int-rv32.ll
@@ -0,0 +1,952 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32d \
+; RUN: -global-isel -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv32i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv64i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv64i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv32i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv1i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv2i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv4i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv8i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv16i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv16i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa5
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
+ ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv1i64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v9, fa5
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3
+ ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1i64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa5
+; CHECK-NEXT: addi a0, a2, 1
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a2
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
+ ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa5
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv2i64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vfmv.s.f v10, fa5
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v10, fa5
+; CHECK-NEXT: addi a0, a2, 1
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a2
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa5
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
+ ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv4i64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vfmv.s.f v12, fa5
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3
+ ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4i64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v12, fa5
+; CHECK-NEXT: addi a0, a2, 1
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a2
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
+ ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa5
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0
+ ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv8i64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vfmv.s.f v16, fa5
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3
+ ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8i64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v16, fa5
+; CHECK-NEXT: addi a0, a2, 1
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a2
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx
+ ret <vscale x 8 x i64> %r
+}
+
+; Extra tests to check lowering of constant values
+define <vscale x 2 x i64> @insertelt_nxv2i64_0_c10(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: insertelt_nxv2i64_0_c10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: li a0, 10
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw zero, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa5
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 0
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_imm_c10(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: insertelt_nxv2i64_imm_c10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: li a0, 10
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw zero, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vfmv.s.f v10, fa5
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 3
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_idx_c10(<vscale x 2 x i64> %v, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i64_idx_c10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: li a1, 10
+; CHECK-NEXT: sw a1, 8(sp)
+; CHECK-NEXT: sw zero, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v10, fa5
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 %idx
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_0_cn1(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: insertelt_nxv2i64_0_cn1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a0, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
+; CHECK-NEXT: vfmv.s.f v8, fa5
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 0
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_imm_cn1(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: insertelt_nxv2i64_imm_cn1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: sw a0, 8(sp)
+; CHECK-NEXT: sw a0, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vfmv.s.f v10, fa5
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 3
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_idx_cn1(<vscale x 2 x i64> %v, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i64_idx_cn1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: sw a1, 8(sp)
+; CHECK-NEXT: sw a1, 12(sp)
+; CHECK-NEXT: fld fa5, 8(sp)
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v10, fa5
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 %idx
+ ret <vscale x 2 x i64> %r
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-int-rv64.ll
new file mode 100644
index 0000000000000..0502d0ff48d34
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/insertelt-int-rv64.ll
@@ -0,0 +1,759 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64d \
+; RUN: -global-isel -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv1i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv2i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv4i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv8i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv16i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv32i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0
+ ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv64i8_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3
+ ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv64i8_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx
+ ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv1i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv2i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv4i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv8i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv16i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0
+ ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i16_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3
+ ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv32i16_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx
+ ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv1i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv2i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv4i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv8i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0
+ ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i32_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3
+ ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 signext %elt, i32 zeroext %idx) {
+; CHECK-LABEL: insertelt_nxv16i32_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx
+ ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
+ ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv1i64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vslideup.vi v8, v9, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3
+ ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1i64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a1, a1, 32
+; CHECK-NEXT: srli a1, a1, 32
+; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
+ ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv2i64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vslideup.vi v8, v10, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a1, a1, 32
+; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: srli a1, a1, 32
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
+ ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv4i64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vslideup.vi v8, v12, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3
+ ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4i64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a1, a1, 32
+; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: srli a1, a1, 32
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
+ ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0
+ ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv8i64_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: vslideup.vi v8, v16, 3
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3
+ ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8i64_idx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a1, a1, 32
+; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: srli a1, a1, 32
+; CHECK-NEXT: addi a0, a1, 1
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
+; CHECK-NEXT: vslideup.vx v8, v16, a1
+; CHECK-NEXT: ret
+ %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx
+ ret <vscale x 8 x i64> %r
+}
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