[llvm] [X86][APX] Ignore the use of EFLAGS when ZU is enabled (PR #176645)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: Phoebe Wang (phoebewang)

<details>
<summary>Changes</summary>

Since we don't need to insert the XOR instruction.

Fixes redundant MOVXZ in https://godbolt.org/z/s9Kq6TPoW

---
Full diff: https://github.com/llvm/llvm-project/pull/176645.diff


2 Files Affected:

- (modified) llvm/lib/Target/X86/X86FixupSetCC.cpp (+2-1) 
- (modified) llvm/test/CodeGen/X86/apx/setzucc.ll (+13) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86FixupSetCC.cpp b/llvm/lib/Target/X86/X86FixupSetCC.cpp
index ef906f2e71c99..d4c7ecd270244 100644
--- a/llvm/lib/Target/X86/X86FixupSetCC.cpp
+++ b/llvm/lib/Target/X86/X86FixupSetCC.cpp
@@ -97,7 +97,8 @@ static bool fixupSetCC(MachineFunction &MF) {
       // it, itself, by definition, clobbers eflags. But it may happen that
       // FlagsDefMI also *uses* eflags, in which case the transformation is
       // invalid.
-      if (FlagsDefMI->readsRegister(X86::EFLAGS, /*TRI=*/nullptr))
+      if (!ST->hasZU() &&
+          FlagsDefMI->readsRegister(X86::EFLAGS, /*TRI=*/nullptr))
         continue;
 
       // On 32-bit, we need to be careful to force an ABCD register.
diff --git a/llvm/test/CodeGen/X86/apx/setzucc.ll b/llvm/test/CodeGen/X86/apx/setzucc.ll
index ae3154968d566..a7215164ee9e3 100644
--- a/llvm/test/CodeGen/X86/apx/setzucc.ll
+++ b/llvm/test/CodeGen/X86/apx/setzucc.ll
@@ -109,3 +109,16 @@ bb1:
 bb2:
   ret i32 0
 }
+
+define i32 @def_use_eflag(i32 %a, i32 %b, i8 %c) {
+; CHECK-LABEL: def_use_eflag:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addb $-1, %dl
+; CHECK-NEXT:    adcl %esi, %edi
+; CHECK-NEXT:    setzub %al
+; CHECK-NEXT:    retq
+  %1 = call { i8, i32 } @llvm.x86.addcarry.32(i8 %c, i32 %a, i32 %b)
+  %2 = extractvalue { i8, i32 } %1, 0
+  %3 = zext i8 %2 to i32
+  ret i32 %3
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/176645