[llvm] [AMDGPU][NFC] Pre-commit tests for f16<->i32 conversions (PR #176630)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Syadus Sefat (mssefat)

<details>
<summary>Changes</summary>

This patch adds tests showing current AMDGPU codegen for f16 to i32 and i32 to f16 conversions.

These tests will be updated in a follow-up PR with modified SOPInstructions.td that will have an effect on the tests.

---
Full diff: https://github.com/llvm/llvm-project/pull/176630.diff


1 Files Affected:

- (added) llvm/test/CodeGen/AMDGPU/scalar-f16-int-conversions.ll (+116) 


``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/scalar-f16-int-conversions.ll b/llvm/test/CodeGen/AMDGPU/scalar-f16-int-conversions.ll
new file mode 100644
index 0000000000000..a95e7c9a89648
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/scalar-f16-int-conversions.ll
@@ -0,0 +1,116 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s --check-prefix=GFX10
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1150 < %s | FileCheck %s --check-prefix=GFX11
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s --check-prefix=GFX12
+
+define amdgpu_ps void @s_fptosi_f16_to_i32(half inreg %x, ptr addrspace(1) %out) {
+; GFX10-LABEL: s_fptosi_f16_to_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v2, s0
+; GFX10-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; GFX10-NEXT:    global_store_dword v[0:1], v2, off
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_fptosi_f16_to_i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; GFX11-NEXT:    global_store_b32 v[0:1], v2, off
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_fptosi_f16_to_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_cvt_f32_f16_e32 v2, s0
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; GFX12-NEXT:    global_store_b32 v[0:1], v2, off
+; GFX12-NEXT:    s_endpgm
+  %result = fptosi half %x to i32
+  store i32 %result, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_ps void @s_fptoui_f16_to_i32(half inreg %x, ptr addrspace(1) %out) {
+; GFX10-LABEL: s_fptoui_f16_to_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v2, s0
+; GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX10-NEXT:    global_store_dword v[0:1], v2, off
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_fptoui_f16_to_i32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX11-NEXT:    global_store_b32 v[0:1], v2, off
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_fptoui_f16_to_i32:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_cvt_f32_f16_e32 v2, s0
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX12-NEXT:    global_store_b32 v[0:1], v2, off
+; GFX12-NEXT:    s_endpgm
+  %result = fptoui half %x to i32
+  store i32 %result, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_ps void @s_sitofp_i32_to_f16(i32 inreg %x, ptr addrspace(1) %out) {
+; GFX10-LABEL: s_sitofp_i32_to_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_cvt_f32_i32_e32 v2, s0
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX10-NEXT:    global_store_short v[0:1], v2, off
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_sitofp_i32_to_f16:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_cvt_f32_i32_e32 v2, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-NEXT:    global_store_b16 v[0:1], v2, off
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_sitofp_i32_to_f16:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_cvt_f32_i32_e32 v2, s0
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX12-NEXT:    global_store_b16 v[0:1], v2, off
+; GFX12-NEXT:    s_endpgm
+  %result = sitofp i32 %x to half
+  store half %result, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_ps void @s_uitofp_i32_to_f16(i32 inreg %x, ptr addrspace(1) %out) {
+; GFX10-LABEL: s_uitofp_i32_to_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s0
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX10-NEXT:    global_store_short v[0:1], v2, off
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-LABEL: s_uitofp_i32_to_f16:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_cvt_f32_u32_e32 v2, s0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-NEXT:    global_store_b16 v[0:1], v2, off
+; GFX11-NEXT:    s_endpgm
+;
+; GFX12-LABEL: s_uitofp_i32_to_f16:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_cvt_f32_u32_e32 v2, s0
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX12-NEXT:    global_store_b16 v[0:1], v2, off
+; GFX12-NEXT:    s_endpgm
+  %result = uitofp i32 %x to half
+  store half %result, ptr addrspace(1) %out
+  ret void
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/176630