[llvm] [AMDGPU] Reduce number of emitted S_SET_VGPR_MSB instructions (PR #176502)

[Tim Gymnich via llvm-commits]

https://github.com/tgymnich updated https://github.com/llvm/llvm-project/pull/176502

>From fec9f511e395bdce00c9f61f2e784cf7647460e2 Mon Sep 17 00:00:00 2001
From: Tim Gymnich <tim at gymni.ch>
Date: Fri, 16 Jan 2026 21:41:50 +0000
Subject: [PATCH 1/2] [AMDGPU] Reduce number of emitted S_SET_VGPR_MSB
 instructions

---
 llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp | 3 ++-
 llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir | 9 ++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
index 7e946018c4492..6a3e1640ccb63 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
@@ -164,6 +164,7 @@ class AMDGPULowerVGPREncoding {
 bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode, ModeTy Mask,
                                       MachineBasicBlock::instr_iterator I) {
   assert((NewMode.raw_bits() & ~Mask.raw_bits()).none());
+  assert((CurrentMode.raw_bits() & ~CurrentMask.raw_bits()).none());
 
   auto Delta = NewMode.raw_bits() ^ CurrentMode.raw_bits();
 
@@ -172,7 +173,7 @@ bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode, ModeTy Mask,
     return false;
   }
 
-  if (MostRecentModeSet && (Delta & CurrentMask.raw_bits()).none()) {
+  if (MostRecentModeSet && ((Delta & Mask.raw_bits()) & CurrentMask.raw_bits()).none()) {
     CurrentMode |= NewMode;
     CurrentMask |= Mask;
 
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
index a2b5ef7771c09..fd1b5587de8f8 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
@@ -526,7 +526,14 @@ body:             |
     $vgpr1 = V_ADD_U32_e32 undef $vgpr257, undef $vgpr1, implicit $exec
     $vgpr2 = V_ADD_U32_e32 undef $vgpr258, undef $vgpr258, implicit $exec
 
-    ; ASM: NumVgprs: 263
+    ; GCN-NEXT: s_set_vgpr_msb 0x50a
+    ; ASM-SAME:                                         ;  msbs: dst=0 src0=2 src1=2 src2=0
+    ; GCN-NEXT: v_mov_b32_e32 v8, v18 /*v530*/
+    ; GCN-NEXT: v_add_nc_u32_e32 v9, 0x1234, v19 /*v531*/
+    $vgpr8 = V_MOV_B32_e32 undef $vgpr530, implicit $exec
+    $vgpr9 = V_ADD_U32_e32 0x1234, undef $vgpr531, implicit $exec
+
+    ; ASM: NumVgprs: 532
 
 ...
 

>From 2f0d12cff312c679dd06a25c7b7b17e4dee5962d Mon Sep 17 00:00:00 2001
From: Tim Gymnich <tim at gymni.ch>
Date: Sat, 17 Jan 2026 00:21:49 +0000
Subject: [PATCH 2/2] clang format

---
 llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
index 6a3e1640ccb63..ebe8e489ddcfd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
@@ -173,7 +173,8 @@ bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode, ModeTy Mask,
     return false;
   }
 
-  if (MostRecentModeSet && ((Delta & Mask.raw_bits()) & CurrentMask.raw_bits()).none()) {
+  if (MostRecentModeSet &&
+      ((Delta & Mask.raw_bits()) & CurrentMask.raw_bits()).none()) {
     CurrentMode |= NewMode;
     CurrentMask |= Mask;