[llvm] [NFC][NVPTX] Reformat NVPTXUsage to use 80 col width (PR #176425)

[Rahul Joshi via llvm-commits]

https://github.com/jurahul updated https://github.com/llvm/llvm-project/pull/176425

>From 6f89ba9dffc8ae88ec26f6c5e037f7638e75faf4 Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Fri, 16 Jan 2026 08:42:54 -0800
Subject: [PATCH] [NFC][NVPTX] Reformat NVPTXUsage to use 80 col width

---
 llvm/docs/NVPTXUsage.rst | 1068 +++++++++++++++++++++-----------------
 1 file changed, 583 insertions(+), 485 deletions(-)

diff --git a/llvm/docs/NVPTXUsage.rst b/llvm/docs/NVPTXUsage.rst
index 874476602f14b..3256068078632 100644
--- a/llvm/docs/NVPTXUsage.rst
+++ b/llvm/docs/NVPTXUsage.rst
@@ -106,10 +106,10 @@ Function Attributes
     a runtime error or kernel launch failure. Only supported for Hopper+.
 
 ``"nvvm.blocksareclusters"``
-    This attribute implies that the grid launch configuration for the corresponding
-    kernel function is specifying the number of clusters instead of the number of thread
-    blocks. This attribute is only allowed for kernel functions and requires
-    ``nvvm.reqntid`` and ``nvvm.cluster_dim`` attributes.
+    This attribute implies that the grid launch configuration for the
+    corresponding kernel function is specifying the number of clusters instead
+    of the number of thread blocks. This attribute is only allowed for kernel
+    functions and requires ``nvvm.reqntid`` and ``nvvm.cluster_dim`` attributes.
 
 .. _address_spaces:
 
@@ -172,37 +172,43 @@ NVPTX Architecture Hierarchy and Ordering
 =========================================
 
 GPU architectures: sm_2Y/sm_3Y/sm_5Y/sm_6Y/sm_7Y/sm_8Y/sm_9Y/sm_10Y/sm_12Y
-('Y' represents version within the architecture)
-The architectures have name of form ``sm_XYz`` where ``X`` represent the generation
-number, ``Y`` represents the version within the architecture, and ``z`` represents
-the optional feature suffix.
-If ``X1Y1 <= X2Y2``, then GPU capabilities of ``sm_X1Y1`` are included in ``sm_X2Y2``.
-For example, take ``sm_90`` (9 represents ``X``, 0 represents ``Y``, and no feature
-suffix) and ``sm_103`` architectures (10 represents ``X``, 3 represents ``Y``, and no
-feature suffix). Since 90 <= 103, ``sm_90`` is compatible with ``sm_103``.
+('Y' represents version within the architecture). The architectures have name of
+the form ``sm_XYz`` where:
+
+* ``X`` represent the generation number
+* ``Y`` represents the version within the architecture, and
+* ``z`` represents the optional feature suffix.
+
+If ``X1Y1 <= X2Y2``, then GPU capabilities of ``sm_X1Y1`` are included in
+``sm_X2Y2``. For example, take ``sm_90`` (9 represents ``X``, 0 represents
+``Y``, and no feature suffix) and ``sm_103`` architectures (10 represents ``X``,
+3 represents ``Y``, and no feature suffix). Since 90 <= 103, ``sm_90`` is
+compatible with ``sm_103``.
 
 The family-specific variants have ``f`` feature suffix and they follow
 following order:
 ``sm_X{Y2}f > sm_X{Y1}f`` iff ``Y2 > Y1``
 ``sm_XY{f} > sm_{XY}{}``
 
-For example, take ``sm_100f`` (10 represents ``X``, 0 represents ``Y``, and ``f``
-represents ``z``) and ``sm_103f`` (10 represents ``X``, 3 represents ``Y``, and ``f``
-represents ``z``) architecture variants. Since ``Y1 < Y2``, ``sm_100f`` is compatible with
-``sm_103f``. Similarly based on the second rule, ``sm_90`` is compatible with ``sm_103f``.
+For example, take ``sm_100f`` (10 represents ``X``, 0 represents ``Y``, and
+``f`` represents ``z``) and ``sm_103f`` (10 represents ``X``, 3 represents
+``Y``, and ``f`` represents ``z``) architecture variants. Since ``Y1 < Y2``,
+``sm_100f`` is compatible with ``sm_103f``. Similarly based on the second rule,
+``sm_90`` is compatible with ``sm_103f``.
 
 Some counter examples, take ``sm_100f`` and ``sm_120f`` (12 represents ``X``, 0
 represents ``Y``, and ``f`` represents ``z``) architecture variants. Since both
-belongs to different family i.e. ``X1 != X2``, ``sm_100f`` is not compatible with
-``sm_120f``.
+belongs to different family i.e. ``X1 != X2``, ``sm_100f`` is not compatible
+with ``sm_120f``.
 
 The architecture-specific variants have ``a`` feature suffix and they follow
 following order:
 ``sm_XY{a} > sm_XY{f} > sm_{XY}{}``
 
-For example, take ``sm_103a`` (10 represents ``X``, 3 represents ``Y``, and ``a``
-represents ``z``), ``sm_103f``, and ``sm_103`` architecture variants. The ``sm_103`` is
-compatible with ``sm_103a`` and ``sm_103f``, and ``sm_103f`` is compatible with ``sm_103a``.
+For example, take ``sm_103a`` (10 represents ``X``, 3 represents ``Y``, and
+``a`` represents ``z``), ``sm_103f``, and ``sm_103`` architecture variants. The
+``sm_103`` is compatible with ``sm_103a`` and ``sm_103f``, and ``sm_103f`` is
+compatible with ``sm_103a``.
 
 Encoding := Arch * 10 + 2 (for 'f') + 1 (for 'a')
 Arch := X * 10 + Y
@@ -279,15 +285,14 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.read.ptx.sreg.total_smem_size``' intrinsic reads the
-PTX special register that holds the total amount of shared memory
-allocated per CTA for the kernel at launch.
+The '``@llvm.nvvm.read.ptx.sreg.total_smem_size``' intrinsic reads the PTX
+special register that holds the total amount of shared memory allocated per CTA
+for the kernel at launch.
 
-The reported value includes both statically allocated and dynamically
-requested shared memory, but excludes any shared memory reserved for
-system use. The size is expressed in units of the architecture-specific
-shared memory allocation granularity. For targets sm_8x and newer,
-this granularity is 128 bytes.
+The reported value includes both statically allocated and dynamically requested
+shared memory, but excludes any shared memory reserved for system use. The size
+is expressed in units of the architecture-specific shared memory allocation
+granularity. For targets sm_8x and newer, this granularity is 128 bytes.
 
 The '``aggr_smem_size``' variant returns the aggregate shared memory size,
 including the portion reserved for system software use.
@@ -347,9 +352,9 @@ the threads specified by the %n operand should participate in the barrier.
 
 All forms of the '``@llvm.nvvm.barrier.cta.*``' intrinsic cause the executing
 thread to wait for all non-exited threads from its warp and then marks the
-warp's arrival at the barrier. In addition to signaling its arrival at the 
+warp's arrival at the barrier. In addition to signaling its arrival at the
 barrier, the '``@llvm.nvvm.barrier.cta.red.*``' and
-'``@llvm.nvvm.barrier.cta.sync.*``' intrinsics cause the executing thread to 
+'``@llvm.nvvm.barrier.cta.sync.*``' intrinsics cause the executing thread to
 wait for non-exited threads of all other warps participating in the barrier to
 arrive. On the other hand, the '``@llvm.nvvm.barrier.cta.arrive.*``' intrinsic
 does not cause the executing thread to wait for threads of other participating
@@ -364,7 +369,7 @@ using the specified reduction operator. Once the barrier count is reached, the
 final value is returned in all threads waiting at the barrier.
 
 The reduction operations for '``@llvm.nvvm.barrier.cta.red.*``' are
-population-count ('``.popc``'), all-threads-true ('``.and``'), 
+population-count ('``.popc``'), all-threads-true ('``.and``'),
 and any-thread-true ('``.or``'). The result of '``.popc``' is the number of
 threads with a true predicate, while '``.and``' and '``.or``' indicate if all
 the threads had a true predicate or if any of the threads had a true predicate.
@@ -866,14 +871,14 @@ Overview:
 """""""""
 
 The `nvvm.fence.{semantics}.sync_restrict.*` restrict the class of memory
-operations for which the fence instruction provides the memory ordering guarantees.
-When `.sync_restrict` is restricted to `shared_cta`, then memory semantics must
-be `release` and the effect of the fence operation only applies to operations
-performed on objects in `shared_cta` space. Likewise, when `sync_restrict` is
-restricted to `shared_cluster`, then memory semantics must be `acquire` and the
-effect of the fence operation only applies to operations performed on objects in
-`shared_cluster` memory space. The scope for both operations is `cluster`. For more details,
-please refer the `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar>`__
+operations for which the fence instruction provides the memory ordering
+guarantees. When `.sync_restrict` is restricted to `shared_cta`, then memory
+semantics must be `release` and the effect of the fence operation only applies
+to operations performed on objects in `shared_cta` space. Likewise, when
+`sync_restrict` is restricted to `shared_cluster`, then memory semantics must be
+`acquire` and the effect of the fence operation only applies to operations
+performed on objects in `shared_cluster` memory space. The scope for both
+operations is `cluster`. For more details, please refer the `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar>`__
 
 '``llvm.nvvm.fence.mbarrier_init.release.cluster``'
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -891,8 +896,8 @@ Overview:
 `nvvm.fence.mbarrier_init.release.cluster` intrinsic restrict the class of
 memory operations for which the fence instruction provides the memory ordering
 guarantees. The `mbarrier_init` modifiers restricts the synchronizing effect to
-the prior `mbarrier_init` operation executed by the same thread on mbarrier objects
-in `shared_cta` memory space. For more details, please refer the `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar>`__
+the prior `mbarrier_init` operation executed by the same thread on mbarrier
+objects in `shared_cta` memory space. For more details, please refer the `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar>`__
 
 '``llvm.nvvm.fence.proxy.async_generic.acquire/release.sync_restrict``'
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -978,7 +983,14 @@ Syntax:
 Overview:
 """""""""
 
-The ``@llvm.nvvm.fence.proxy.tensormap_generic.*`` is a uni-directional fence used to establish ordering between a prior memory access performed via the generic `proxy<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#proxies>_` and a subsequent memory access performed via the tensormap proxy. ``nvvm.fence.proxy.tensormap_generic.release`` can form a release sequence that synchronizes with an acquire sequence that contains the ``nvvm.fence.proxy.tensormap_generic.acquire`` proxy fence. The following table describes the mapping between LLVM Intrinsic and the PTX instruction:
+The ``@llvm.nvvm.fence.proxy.tensormap_generic.*`` is a uni-directional fence
+used to establish ordering between a prior memory access performed via the
+generic `proxy <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#proxies>`_
+and a subsequent memory access performed via the tensormap proxy.
+``nvvm.fence.proxy.tensormap_generic.release`` can form a release sequence that
+synchronizes with an acquire sequence that contains the
+``nvvm.fence.proxy.tensormap_generic.acquire`` proxy fence. The following table
+describes the mapping between LLVM Intrinsic and the PTX instruction:
 
   ====================================================== =========================================================
   NVVM Intrinsic                                         PTX Instruction
@@ -987,7 +999,13 @@ The ``@llvm.nvvm.fence.proxy.tensormap_generic.*`` is a uni-directional fence us
   ``@llvm.nvvm.fence.proxy.tensormap_generic.acquire.*`` ``fence.proxy.tensormap::generic.acquire.* [addr], size``
   ====================================================== =========================================================
 
-The address operand ``addr`` and the operand ``size`` together specify the memory range ``[addr, addr+size)`` on which the ordering guarantees on the memory accesses across the proxies is to be provided. The only supported value for the ``size`` operand is ``128`` and must be an immediate. Generic Addressing is used unconditionally, and the address specified by the operand addr must fall within the ``.global`` state space. Otherwise, the behavior is undefined. For more information, see `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-membar>`_.
+The address operand ``addr`` and the operand ``size`` together specify the
+memory range ``[addr, addr+size)`` on which the ordering guarantees on the
+memory accesses across the proxies is to be provided. The only supported value
+for the ``size`` operand is ``128`` and must be an immediate. Generic Addressing
+is used unconditionally, and the address specified by the operand addr must fall
+within the ``.global`` state space. Otherwise, the behavior is undefined. For
+more information, see `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-membar>`_.
 
 Address Space Intrinsics
 ------------------------
@@ -1033,10 +1051,13 @@ Syntax:
 Overview:
 """""""""
 
-The '``llvm.nvvm.mapa.*``' intrinsics map a shared memory pointer ``p`` of another CTA with ``%rank`` to the current CTA.
-The ``llvm.nvvm.mapa`` form expects a generic pointer to shared memory and returns a generic pointer to shared cluster memory.
-The ``llvm.nvvm.mapa.shared.cluster`` form expects a pointer to shared memory and returns a pointer to shared cluster memory.
-They corresponds directly to the ``mapa`` and ``mapa.shared.cluster`` PTX instructions.
+The '``llvm.nvvm.mapa.*``' intrinsics map a shared memory pointer ``p`` of
+another CTA with ``%rank`` to the current CTA. The ``llvm.nvvm.mapa`` form
+expects a generic pointer to shared memory and returns a generic pointer to
+shared cluster memory. The ``llvm.nvvm.mapa.shared.cluster`` form expects a
+pointer to shared memory and returns a pointer to shared cluster memory. They
+corresponds directly to the ``mapa`` and ``mapa.shared.cluster`` PTX
+instructions.
 
 Semantics:
 """"""""""
@@ -1119,7 +1140,7 @@ Overview:
 """""""""
 
 The '``llvm.nvvm.idp2a.[us].[us]``' intrinsics performs a 2-element vector dot
-product followed by addition. They corresponds directly to the ``dp2a`` PTX 
+product followed by addition. They corresponds directly to the ``dp2a`` PTX
 instruction.
 
 Semantics:
@@ -1240,8 +1261,9 @@ Syntax:
 Overview:
 """""""""
 
-The '``llvm.nvvm.flo.u``' family of intrinsics identifies the bit position of the
-leading one, returning either it's offset from the most or least significant bit.
+The '``llvm.nvvm.flo.u``' family of intrinsics identifies the bit position of
+the leading one, returning either it's offset from the most or least significant
+bit.
 
 Semantics:
 """"""""""
@@ -1266,8 +1288,8 @@ Syntax:
 Overview:
 """""""""
 
-The '``llvm.nvvm.flo.s``' family of intrinsics identifies the bit position of the
-leading non-sign bit, returning either it's offset from the most or least
+The '``llvm.nvvm.flo.s``' family of intrinsics identifies the bit position of
+the leading non-sign bit, returning either it's offset from the most or least
 significant bit.
 
 Semantics:
@@ -1473,26 +1495,25 @@ Overview:
 """""""""
 
 The '``@llvm.nvvm.cp.async.bulk.global.to.shared.cluster``' intrinsic
-corresponds to the ``cp.async.bulk.shared::cluster.global.*`` family
-of PTX instructions. These instructions initiate an asynchronous
-copy of bulk data from global memory to shared::cluster memory.
-The 32-bit operand ``%size`` specifies the amount of memory to be
-copied and it must be a multiple of 16.
+corresponds to the ``cp.async.bulk.shared::cluster.global.*`` family of PTX
+instructions. These instructions initiate an asynchronous copy of bulk data from
+global memory to shared::cluster memory. The 32-bit operand ``%size`` specifies
+the amount of memory to be copied and it must be a multiple of 16.
 
-* The last two arguments to these intrinsics are boolean flags
-  indicating support for cache_hint and/or multicast modifiers.
-  These flag arguments must be compile-time constants. The backend
-  looks through these flags and lowers the intrinsics appropriately.
+* The last two arguments to these intrinsics are boolean flags indicating
+  support for cache_hint and/or multicast modifiers. These flag arguments must
+  be compile-time constants. The backend looks through these flags and lowers
+  the intrinsics appropriately.
 
-* The Nth argument (denoted by ``i1 %flag_ch``) when set, indicates
-  a valid cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
-  variant of the PTX instruction.
+* The Nth argument (denoted by ``i1 %flag_ch``) when set, indicates a valid
+  cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint`` variant of the
+  PTX instruction.
 
-* The [N-1]th argument (denoted by ``i1 %flag_mc``) when set, indicates
-  the presence of a multicast mask (``i16 %mc``) and generates the PTX
-  instruction with the ``.multicast::cluster`` modifier.
+* The [N-1]th argument (denoted by ``i1 %flag_mc``) when set, indicates the
+  presence of a multicast mask (``i16 %mc``) and generates the PTX instruction
+  with the ``.multicast::cluster`` modifier.
 
-For more information, refer PTX ISA
+For more information, refer PTX ISA 
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk>`_.
 
 '``llvm.nvvm.cp.async.bulk.global.to.shared.cta``'
@@ -1508,15 +1529,14 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.cp.async.bulk.global.to.shared.cta``' intrinsic
-corresponds to the ``cp.async.bulk.shared::cta.global.*`` family
-of PTX instructions. These instructions initiate an asynchronous
-copy of bulk data from global memory to shared::cta memory.
-The 32-bit operand ``%size`` specifies the amount of memory to be
-copied and it must be a multiple of 16. The last argument
-(denoted by ``i1 %flag_ch``) is a compile-time constant. When set,
-it indicates a valid cache_hint (``i64 %ch``) and generates the
-``.L2::cache_hint`` variant of the PTX instruction.
+The '``@llvm.nvvm.cp.async.bulk.global.to.shared.cta``' intrinsic corresponds to
+the ``cp.async.bulk.shared::cta.global.*`` family of PTX instructions. These
+instructions initiate an asynchronous copy of bulk data from global memory to
+shared::cta memory. The 32-bit operand ``%size`` specifies the amount of memory
+to be copied and it must be a multiple of 16. The last argument (denoted by
+``i1 %flag_ch``) is a compile-time constant. When set, it indicates a valid
+cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint`` variant of the
+PTX instruction.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk>`_.
@@ -1535,20 +1555,18 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.cp.async.bulk.shared.cta.to.global``' intrinsic
-corresponds to the ``cp.async.bulk.global.shared::cta.*`` set of PTX
-instructions. These instructions initiate an asynchronous copy from
-shared::cta to global memory. The 32-bit operand ``%size`` specifies
-the amount of memory to be copied (in bytes) and it must be a multiple
-of 16. For the ``.bytemask`` variant, the 16-bit wide mask operand
-specifies whether the i-th byte of each 16-byte wide chunk of source
-data is copied to the destination.
-
-* The ``i1 %flag_ch`` argument to these intrinsics is a boolean
-  flag indicating support for cache_hint. This flag argument must
-  be a compile-time constant. When set, it indicates a valid
-  cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
-  variant of the PTX instruction.
+The '``@llvm.nvvm.cp.async.bulk.shared.cta.to.global``' intrinsic corresponds to
+the ``cp.async.bulk.global.shared::cta.*`` set of PTX instructions. These
+instructions initiate an asynchronous copy from shared::cta to global memory.
+The 32-bit operand ``%size`` specifies the amount of memory to be copied
+(in bytes) and it must be a multiple of 16. For the ``.bytemask`` variant, the
+16-bit wide mask operand specifies whether the i-th byte of each 16-byte wide
+chunk of source data is copied to the destination.
+
+* The ``i1 %flag_ch`` argument to these intrinsics is a boolean flag indicating
+  support for cache_hint. This flag argument must be a compile-time constant.
+  When set, it indicates a valid cache_hint (``i64 %ch``) and generates the
+  ``.L2::cache_hint`` variant of the PTX instruction.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk>`_.
@@ -1566,13 +1584,12 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.cp.async.bulk.shared.cta.to.cluster``' intrinsic
-corresponds to the ``cp.async.bulk.shared::cluster.shared::cta.*``
-PTX instruction. This instruction initiates an asynchronous copy from
-shared::cta to shared::cluster memory. The destination has to be in
-the shared memory of a different CTA within the cluster. The 32-bit
-operand ``%size`` specifies the amount of memory to be copied and
-it must be a multiple of 16.
+The '``@llvm.nvvm.cp.async.bulk.shared.cta.to.cluster``' intrinsic corresponds
+to the ``cp.async.bulk.shared::cluster.shared::cta.*`` PTX instruction. This
+instruction initiates an asynchronous copy from shared::cta to shared::cluster
+memory. The destination has to be in the shared memory of a different CTA within
+the cluster. The 32-bit operand ``%size`` specifies the amount of memory to be
+copied and it must be a multiple of 16.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk>`_.
@@ -1590,17 +1607,16 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.cp.async.bulk.prefetch.L2``' intrinsic
-corresponds to the ``cp.async.bulk.prefetch.L2.*`` family
-of PTX instructions. These instructions initiate an asynchronous
-prefetch of bulk data from global memory to the L2 cache.
-The 32-bit operand ``%size`` specifies the amount of memory to be
+The '``@llvm.nvvm.cp.async.bulk.prefetch.L2``' intrinsic corresponds to the
+``cp.async.bulk.prefetch.L2.*`` family of PTX instructions. These instructions
+initiate an asynchronous prefetch of bulk data from global memory to the L2
+cache. The 32-bit operand ``%size`` specifies the amount of memory to be
 prefetched in terms of bytes and it must be a multiple of 16.
 
-* The last argument to these intrinsics is boolean flag indicating
-  support for cache_hint. These flag argument must be compile-time
-  constant. When set, it indicates a valid cache_hint (``i64 %ch``)
-  and generates the ``.L2::cache_hint`` variant of the PTX instruction.
+* The last argument to these intrinsics is boolean flag indicating support for
+  cache_hint. These flag argument must be compile-time constant. When set, it
+  indicates a valid cache_hint (``i64 %ch``) and generates the
+  ``.L2::cache_hint`` variant of the PTX instruction.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch>`_.
@@ -1634,20 +1650,21 @@ Overview:
 """""""""
 
 The '``@llvm.nvvm.prefetch.*``' and '``@llvm.nvvm.prefetchu.*``' intrinsic
-correspond to the '``prefetch.*``;' and '``prefetchu.*``' family of PTX instructions. 
-The '``prefetch.*``' instructions bring the cache line containing the
-specified address in global or local memory address space into the 
-specified cache level (L1 or L2). If the '``.tensormap``' qualifier is specified then the 
-prefetch instruction brings the cache line containing the specified address in the 
-'``.const``' or '``.param memory``' state space for subsequent use by the '``cp.async.bulk.tensor``' 
-instruction. The '`prefetchu.*``' instruction brings the cache line 
-containing the specified generic address into the specified uniform cache level.
-If no address space is specified, it is assumed to be generic address. The intrinsic 
-uses and eviction priority which can be accessed by the '``.level::eviction_priority``' modifier.
+correspond to the '``prefetch.*``;' and '``prefetchu.*``' family of PTX
+instructions. The '``prefetch.*``' instructions bring the cache line containing
+the specified address in global or local memory address space into the specified
+cache level (L1 or L2). If the '``.tensormap``' qualifier is specified then the
+prefetch instruction brings the cache line containing the specified address in
+the  '``.const``' or '``.param memory``' state space for subsequent use by the
+'``cp.async.bulk.tensor``' instruction. The '``prefetchu.*``' instruction brings
+the cache line containing the specified generic address into the specified
+uniform cache level. If no address space is specified, it is assumed to be
+generic address. The intrinsic uses and eviction priority which can be accessed
+by the '``.level::eviction_priority``' modifier.
 
 * A prefetch to a shared memory location performs no operation.
-* A prefetch into the uniform cache requires a generic address, 
-  and no operation occurs if the address maps to a const, local, or shared memory location.
+* A prefetch into the uniform cache requires a generic address, and no operation
+  occurs if the address maps to a const, local, or shared memory location.
 
 For more information, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-prefetch-prefetchu>`_.
@@ -1666,12 +1683,14 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.applypriority.*``'  applies the cache eviction priority specified by the
-.level::eviction_priority qualifier to the address range [a..a+size) in the specified cache 
-level. If no state space is specified then Generic Addressing is used. If the specified address 
-does not fall within the address window of .global state space then the behavior is undefined.
-The operand size is an integer constant that specifies the amount of data, in bytes, in the specified cache
-level on which the priority is to be applied. The only supported value for the size operand is 128.
+The '``@llvm.nvvm.applypriority.*``'  applies the cache eviction priority
+specified by the .level::eviction_priority qualifier to the address range
+[a..a+size) in the specified cache level. If no state space is specified then
+generic addressing is used. If the specified address does not fall within the
+address window of .global state space then the behavior is undefined. The
+operand size is an integer constant that specifies the amount of data, in bytes,
+in the specified cache level on which the priority is to be applied. The only
+supported value for the size operand is 128.
 
 For more information, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-applypriority>`_.
@@ -1690,18 +1709,18 @@ Syntax:
 Overview:
 """""""""
 
-The *effects* of the ``@llvm.nvvm.discard.L2*`` intrinsics are those of a non-atomic 
-non-volatile ``llvm.memset`` that writes ``undef`` to the destination 
-address range ``[%ptr, %ptr + immarg)``. The ``%ptr`` must be aligned by 128 bytes.
-Subsequent reads from the address range may read ``undef`` until the memory is overwritten 
-with a different value.
-These operations *hint* the implementation that data in the L2 cache can be destructively 
-discarded without writing it back to memory. 
-The operand ``immarg`` is an integer constant that specifies the length in bytes of the 
-address range ``[%ptr, %ptr + immarg)`` to write ``undef`` into. 
-The only supported value for the ``immarg`` operand is ``128``. 
-If generic addressing is used and the specified address does not fall within the 
-address window of global memory (``addrspace(1)``) the behavior is undefined.
+The *effects* of the ``@llvm.nvvm.discard.L2*`` intrinsics are those of a
+non-atomic non-volatile ``llvm.memset`` that writes ``undef`` to the destination
+address range ``[%ptr, %ptr + immarg)``. The ``%ptr`` must be aligned by 128
+bytes. Subsequent reads from the address range may read ``undef`` until the
+memory is overwritten with a different value. These operations *hint* the
+implementation that data in the L2 cache can be destructively discarded without
+writing it back to memory. The operand ``immarg`` is an integer constant that
+specifies the length in bytes of the address range ``[%ptr, %ptr + immarg)`` to
+write ``undef`` into. The only supported value for the ``immarg`` operand is
+``128``.  If generic addressing is used and the specified address does not fall
+within the address window of global memory (``addrspace(1)``) the behavior is
+undefined.
 
 .. code-block:: llvm
  
@@ -1734,41 +1753,39 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.cp.async.bulk.tensor.g2s.tile.[1-5]d``' intrinsics
-correspond to the ``cp.async.bulk.tensor.[1-5]d.*`` set of PTX instructions.
-These instructions initiate an asynchronous copy of tensor data from
-global memory to shared::cluster memory (indicated by the ``g2s`` prefix)
-in ``tile`` mode. In tile mode, the multi-dimensional layout of the
-source tensor is preserved at the destination. The dimension of the
-tensor data ranges from 1d to 5d with the coordinates specified
-by the ``i32 %d0 ... i32 %d4`` arguments. In ``tile.gather4`` mode,
-four rows in a 2D tensor are combined to form a single 2D destination
-tensor. The first coordinate ``i32 %x0`` denotes the column index
-followed by four coordinates indicating the four row-indices.
-So, this mode takes a total of 5 coordinates as input arguments.
-For more information on ``gather4`` mode, refer PTX ISA
+The '``@llvm.nvvm.cp.async.bulk.tensor.g2s.tile.[1-5]d``' intrinsics correspond
+to the ``cp.async.bulk.tensor.[1-5]d.*`` set of PTX instructions. These
+instructions initiate an asynchronous copy of tensor data from global memory to
+shared::cluster memory (indicated by the ``g2s`` prefix) in ``tile`` mode. In
+tile mode, the multi-dimensional layout of the source tensor is preserved at the
+destination. The dimension of the tensor data ranges from 1d to 5d with the
+coordinates specified by the ``i32 %d0 ... i32 %d4`` arguments. In
+``tile.gather4`` mode, four rows in a 2D tensor are combined to form a single 2D
+destination tensor. The first coordinate ``i32 %x0`` denotes the column index
+followed by four coordinates indicating the four row-indices. So, this mode
+takes a total of 5 coordinates as input arguments. For more information on
+``gather4`` mode, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-tiled-scatter4-gather4-modes>`_.
 
-* The last three arguments to these intrinsics are flags
-  indicating support for multicast, cache_hint and cta_group::1/2
-  modifiers. These flag arguments must be compile-time constants.
-  The backend looks through these flags and lowers the intrinsics
-  appropriately.
+* The last three arguments to these intrinsics are flags indicating support for
+  multicast, cache_hint and cta_group::1/2 modifiers. These flag arguments must
+  be compile-time constants. The backend looks through these flags and lowers
+  the intrinsics appropriately.
 
-* The argument denoted by ``i1 %flag_ch`` when set, indicates
-  a valid cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
-  variant of the PTX instruction.
+* The argument denoted by ``i1 %flag_ch`` when set, indicates a valid cache_hint
+  (``i64 %ch``) and generates the ``.L2::cache_hint`` variant of the PTX
+  instruction.
 
-* The argument denoted by ``i1 %flag_mc`` when set, indicates
-  the presence of a multicast mask (``i16 %mc``) and generates
-  the PTX instruction with the ``.multicast::cluster`` modifier.
+* The argument denoted by ``i1 %flag_mc`` when set, indicates the presence of a
+  multicast mask (``i16 %mc``) and generates the PTX instruction with the
+  ``.multicast::cluster`` modifier.
 
-* The argument denoted by ``i32 %flag_cta_group`` takes values within
-  the range [0, 3) i.e. {0,1,2}. When the value of ``%flag_cta_group``
-  is not within the range, it may raise an error from the Verifier.
-  The default value is '0' with no cta_group modifier in the
-  instruction. The values of '1' and '2' lower to ``cta_group::1``
-  and ``cta_group::2`` variants of the PTX instruction respectively.
+* The argument denoted by ``i32 %flag_cta_group`` takes values within the range
+  [0, 3) i.e. {0,1,2}. When the value of ``%flag_cta_group`` is not within the
+  range, it may raise an error from the Verifier. The default value is '0' with
+  no cta_group modifier in the instruction. The values of '1' and '2' lower to
+  ``cta_group::1`` and ``cta_group::2`` variants of the PTX instruction
+  respectively.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor>`_.
@@ -1798,21 +1815,21 @@ Overview:
 
 The '``@llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.[3-5]d``' intrinsics
 correspond to the ``cp.async.bulk.tensor.[1-5]d.*`` set of PTX instructions.
-These instructions initiate an asynchronous copy of tensor data from
-global memory to shared::cluster memory (indicated by the ``g2s`` prefix)
-in ``im2col`` mode. In im2col mode, some dimensions of the source tensor
-are unrolled into a single dimensional column at the destination. In this
-mode, the tensor has to be at least three-dimensional. Along with the tensor
-coordinates, im2col offsets are also specified (denoted by
-``i16 im2col0...i16 %im2col2``). For the ``im2col`` mode, the number of offsets
-is two less than the number of dimensions of the tensor operation. For the
-``im2col.w`` and ``im2col.w.128`` mode, the number of offsets is always 2,
-denoted by ``i16 %wHalo`` and ``i16 %wOffset`` arguments. For more information
-on ``im2col.w`` and ``im2col.w.128`` modes, refer PTX ISA
+These instructions initiate an asynchronous copy of tensor data from global
+memory to shared::cluster memory (indicated by the ``g2s`` prefix) in ``im2col``
+mode. In im2col mode, some dimensions of the source tensor are unrolled into a
+single dimensional column at the destination. In this mode, the tensor has to be
+at least three-dimensional. Along with the tensor coordinates, im2col offsets
+are also specified (denoted by ``i16 im2col0...i16 %im2col2``). For the
+``im2col`` mode, the number of offsets is two less than the number of dimensions
+of the tensor operation. For the ``im2col.w`` and ``im2col.w.128`` mode, the
+number of offsets is always 2, denoted by ``i16 %wHalo`` and ``i16 %wOffset``
+arguments. For more information on ``im2col.w`` and ``im2col.w.128`` modes,
+refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-im2col-w-w128-modes>`_.
 
-The last three arguments to these intrinsics are flags, with the same functionality
-as described in the ``tile`` mode intrinsics above.
+The last three arguments to these intrinsics are flags, with the same
+functionality as described in the ``tile`` mode intrinsics above.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor>`_.
@@ -1837,25 +1854,23 @@ Overview:
 """""""""
 
 The '``@llvm.nvvm.cp.async.bulk.tensor.g2s.cta.tile.[1-5]d``' intrinsics
-correspond to the ``cp.async.bulk.tensor.[1-5]d.shared::cta.global.*``
-set of PTX instructions. These instructions initiate an asynchronous
-copy of tensor data from global memory to shared::cta memory in
-``tile`` mode. In tile mode, the multi-dimensional layout of the
-source tensor is preserved at the destination. The dimension of the
-tensor data ranges from 1d to 5d with the coordinates specified
-by the ``i32 %d0 ... i32 %d4`` arguments. In ``tile.gather4`` mode,
-four rows in a 2D tensor are combined to form a single 2D destination
-tensor. The first coordinate ``i32 %x0`` denotes the column index
-followed by four coordinates indicating the four row-indices.
-So, this mode takes a total of 5 coordinates as input arguments.
-For more information on ``gather4`` mode, refer PTX ISA
+correspond to the ``cp.async.bulk.tensor.[1-5]d.shared::cta.global.*`` set of
+PTX instructions. These instructions initiate an asynchronous copy of tensor
+data from global memory to shared::cta memory in ``tile`` mode. In tile mode,
+the multi-dimensional layout of the source tensor is preserved at the
+destination. The dimension of the tensor data ranges from 1d to 5d with the
+coordinates specified by the ``i32 %d0 ... i32 %d4`` arguments. In
+``tile.gather4`` mode, four rows in a 2D tensor are combined to form a single 2D
+destination tensor. The first coordinate ``i32 %x0`` denotes the column index
+followed by four coordinates indicating the four row-indices. So, this mode
+takes a total of 5 coordinates as input arguments. For more information on
+``gather4`` mode, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-tiled-scatter4-gather4-modes>`_.
 
-* The last argument to these intrinsics is a boolean flag
-  indicating support for cache_hint. This flag argument must
-  be a compile-time constant. When set, it indicates a valid
-  cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
-  variant of the PTX instruction.
+* The last argument to these intrinsics is a boolean flag indicating support for
+  cache_hint. This flag argument must be a compile-time constant. When set, it
+  indicates a valid cache_hint (``i64 %ch``) and generates the
+  ``.L2::cache_hint`` variant of the PTX instruction.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor>`_.
@@ -1884,25 +1899,23 @@ Overview:
 """""""""
 
 The '``@llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.[3-5]d``' intrinsics
-correspond to the ``cp.async.bulk.tensor.[1-5]d.shared::cta.global.*``
-set of PTX instructions. These instructions initiate an asynchronous copy
-of tensor data from global memory to shared::cta memory in ``im2col`` mode.
-In im2col mode, some dimensions of the source tensor are unrolled into a
-single dimensional column at the destination. In this mode, the tensor has
-to be at least three-dimensional. Along with the tensor coordinates, im2col
-offsets are also specified (denoted by ``i16 im2col0...i16 %im2col2``).
-For the ``im2col`` mode, the number of offsets is two less than the number
-of dimensions of the tensor operation. For the ``im2col.w`` and ``im2col.w.128``
-mode, the number of offsets is always 2, denoted by ``i16 %wHalo`` and
-``i16 %wOffset`` arguments. For more information on ``im2col.w`` and
-``im2col.w.128`` modes, refer PTX ISA
+correspond to the ``cp.async.bulk.tensor.[1-5]d.shared::cta.global.*`` set of
+PTX instructions. These instructions initiate an asynchronous copy of tensor
+data from global memory to shared::cta memory in ``im2col`` mode. In im2col
+mode, some dimensions of the source tensor are unrolled into a single
+dimensional column at the destination. In this mode, the tensor has to be at
+least three-dimensional. Along with the tensor coordinates, im2col offsets are
+also specified (denoted by ``i16 im2col0...i16 %im2col2``). For the ``im2col``
+mode, the number of offsets is two less than the number of dimensions of the
+tensor operation. For the ``im2col.w`` and ``im2col.w.128`` mode, the number of
+offsets is always 2, denoted by ``i16 %wHalo`` and ``i16 %wOffset`` arguments.
+For more information on ``im2col.w`` and ``im2col.w.128`` modes, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-im2col-w-w128-modes>`_.
 
-* The last argument to these intrinsics is a boolean flag
-  indicating support for cache_hint. This flag argument must
-  be a compile-time constant. When set, it indicates a valid
-  cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
-  variant of the PTX instruction.
+* The last argument to these intrinsics is a boolean flag  indicating support
+  for cache_hint. This flag argument must be a compile-time constant. When set,
+  it indicates a valid cache_hint (``i64 %ch``) and generates the
+  ``.L2::cache_hint`` variant of the PTX instruction.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor>`_.
@@ -1926,24 +1939,22 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.cp.async.bulk.tensor.s2g.tile.[1-5]d``' intrinsics
-correspond to the ``cp.async.bulk.tensor.[1-5]d.*`` set of PTX instructions.
-These instructions initiate an asynchronous copy of tensor data from
-shared::cta to global memory (indicated by the ``s2g`` prefix)
-in ``tile`` mode. The dimension of the tensor data ranges from 1d to 5d
-with the coordinates specified by the ``i32 %d0 ... i32 %d4`` arguments.
-In ``tile.scatter4`` mode, a single 2D source tensor is divided into
-four rows in the 2D destination tensor. The first coordinate ``i32 %x0``
-denotes the column index followed by four coordinates indicating the
-four row-indices. So, this mode takes a total of 5 coordinates as input arguments.
-For more information on ``scatter4`` mode, refer PTX ISA
+The '``@llvm.nvvm.cp.async.bulk.tensor.s2g.tile.[1-5]d``' intrinsics correspond
+to the ``cp.async.bulk.tensor.[1-5]d.*`` set of PTX instructions. These
+instructions initiate an asynchronous copy of tensor data from shared::cta to
+global memory (indicated by the ``s2g`` prefix) in ``tile`` mode. The dimension
+of the tensor data ranges from 1d to 5d with the coordinates specified by the
+``i32 %d0 ... i32 %d4`` arguments. In ``tile.scatter4`` mode, a single 2D source
+tensor is divided into four rows in the 2D destination tensor. The first
+coordinate ``i32 %x0`` denotes the column index followed by four coordinates
+indicating the four row-indices. So, this mode takes a total of 5 coordinates as
+input arguments. For more information on ``scatter4`` mode, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-tiled-scatter4-gather4-modes>`_.
 
-* The last argument to these intrinsics is a boolean flag
-  indicating support for cache_hint. This flag argument must
-  be a compile-time constant. When set, it indicates a valid
-  cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
-  variant of the PTX instruction.
+* The last argument to these intrinsics is a boolean flag indicating support for
+  cache_hint. This flag argument must be a compile-time constant. When set, it
+  indicates a valid cache_hint (``i64 %ch``) and generates the
+  ``.L2::cache_hint`` variant of the PTX instruction.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor>`_.
@@ -1966,11 +1977,10 @@ Overview:
 The '``@llvm.nvvm.cp.async.bulk.tensor.s2g.im2col.[1-5]d``' intrinsics
 correspond to the ``cp.async.bulk.tensor.[1-5]d.*`` set of PTX instructions.
 These instructions initiate an asynchronous copy of tensor data from
-shared::cta to global memory (indicated by the ``s2g`` prefix)
-in ``im2col`` mode. In this mode, the tensor has to be at least
-three-dimensional. Unlike the ``g2s`` variants, there are no
-im2col_offsets for these intrinsics. The last argument to these
-intrinsics is a boolean flag, with the same functionality as
+shared::cta to global memory (indicated by the ``s2g`` prefix) in ``im2col``
+mode. In this mode, the tensor has to be at least three-dimensional. Unlike the
+``g2s`` variants, there are no im2col_offsets for these intrinsics. The last
+argument to these intrinsics is a boolean flag, with the same functionality as
 described in the ``s2g.tile`` mode intrinsics above.
 
 For more information, refer PTX ISA
@@ -1996,25 +2006,24 @@ Overview:
 """""""""
 
 The '``@llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.[1-5]d``' intrinsics
-correspond to the ``cp.async.bulk.prefetch.tensor.[1-5]d.L2.global*`` set
-of PTX instructions. These instructions initiate an asynchronous prefetch
-of tensor data from global memory to the L2 cache. In tile mode, the
-multi-dimensional layout of the source tensor is preserved at the destination.
-The dimension of the tensor data ranges from 1d to 5d with the coordinates
-specified by the ``i32 %d0 ... i32 %d4`` arguments.
+correspond to the ``cp.async.bulk.prefetch.tensor.[1-5]d.L2.global*`` set of
+PTX instructions. These instructions initiate an asynchronous prefetch of tensor
+data from global memory to the L2 cache. In tile mode, the multi-dimensional
+layout of the source tensor is preserved at the destination. The dimension of
+the tensor data ranges from 1d to 5d with the coordinates specified by the
+``i32 %d0 ... i32 %d4`` arguments.
 
 In ``tile.gather4`` mode, four rows in the 2-dimnesional source tensor are
-fetched to the L2 cache. The first coordinate ``i32 %x0`` denotes the column index
-followed by four coordinates indicating the four row-indices. So, this mode takes
-a total of 5 coordinates as input arguments.
-For more information on ``gather4`` mode, refer PTX ISA
+fetched to the L2 cache. The first coordinate ``i32 %x0`` denotes the column
+index followed by four coordinates indicating the four row-indices. So, this
+mode takes a total of 5 coordinates as input arguments. For more information
+on ``gather4`` mode, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-tiled-scatter4-gather4-modes>`_.
 
-* The last argument to these intrinsics is a boolean flag
-  indicating support for cache_hint. This flag argument must
-  be a compile-time constant. When set, it indicates a valid
-  cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
-  variant of the PTX instruction.
+* The last argument to these intrinsics is a boolean flag indicating support
+  for cache_hint. This flag argument must be a compile-time constant. When set,
+  it indicates a valid cache_hint (``i64 %ch``) and generates the
+  ``.L2::cache_hint`` variant of the PTX instruction.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor>`_.
@@ -2043,23 +2052,22 @@ Overview:
 """""""""
 
 The '``@llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.[3-5]d``' intrinsics
-correspond to the ``cp.async.bulk.prefetch.tensor.[1-5]d.L2.global*`` set
-of PTX instructions. These instructions initiate an asynchronous prefetch
-of tensor data from global memory to the L2 cache. In im2col mode, some
-dimensions of the source tensor are unrolled into a single dimensional
-column at the destination. In this mode, the tensor has to be at least
-three-dimensional. Along with the tensor coordinates, im2col offsets are
-also specified (denoted by ``i16 im2col0...i16 %im2col2``). For ``im2col``
-mode, the number of offsets is two less than the number of dimensions of
-the tensor operation. For the ``im2col.w`` and ``im2col.w.128`` modes,
-the number of offsets is always 2, denoted by ``i16 %wHalo`` and
-``i16 %wOffset`` arguments. For more information on ``im2col.w`` and
-``im2col.w.128`` modes, refer PTX ISA
+correspond to the ``cp.async.bulk.prefetch.tensor.[1-5]d.L2.global*`` set of PTX
+instructions. These instructions initiate an asynchronous prefetch of tensor
+data from global memory to the L2 cache. In im2col mode, some dimensions of the
+source tensor are unrolled into a single dimensional column at the destination.
+In this mode, the tensor has to be at least three-dimensional. Along with the
+tensor coordinates, im2col offsets are also specified (denoted by
+``i16 im2col0...i16 %im2col2``). For ``im2col`` mode, the number of offsets is
+two less than the number of dimensions of the tensor operation. For the
+``im2col.w`` and ``im2col.w.128`` modes, the number of offsets is always 2,
+denoted by ``i16 %wHalo`` and ``i16 %wOffset`` arguments. For more information
+on ``im2col.w`` and ``im2col.w.128`` modes, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-im2col-w-w128-modes>`_.
 
 
-The last argument to these intrinsics is a boolean flag, with
-the same functionality as described in the ``tile`` mode intrinsics above.
+The last argument to these intrinsics is a boolean flag, with the same
+functionality as described in the ``tile`` mode intrinsics above.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor>`_.
@@ -2090,19 +2098,18 @@ Overview:
 """""""""
 
 The '``@llvm.nvvm.cp.async.bulk.tensor.reduce.<red_op>.tile.[1-5]d``' intrinsics
-correspond to the ``cp.reduce.async.bulk.tensor.[1-5]d.*`` set of PTX instructions.
-These instructions initiate an asynchronous reduction operation of tensor data
-in global memory with the tensor data in shared{::cta} memory, using ``tile`` mode.
-The dimension of the tensor data ranges from 1d to 5d with the coordinates
-specified by the ``i32 %d0 ... i32 %d4`` arguments. The supported reduction
-operations are {add, min, max, inc, dec, and, or, xor} as described in the
-``tile.1d`` intrinsics.
-
-* The last argument to these intrinsics is a boolean flag
-  indicating support for cache_hint. This flag argument must
-  be a compile-time constant. When set, it indicates a valid
-  cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
-  variant of the PTX instruction.
+correspond to the ``cp.reduce.async.bulk.tensor.[1-5]d.*`` set of PTX
+instructions. These instructions initiate an asynchronous reduction operation of
+tensor data in global memory with the tensor data in shared{::cta} memory, using
+``tile`` mode. The dimension of the tensor data ranges from 1d to 5d with the
+coordinates specified by the ``i32 %d0 ... i32 %d4`` arguments. The supported
+reduction operations are {add, min, max, inc, dec, and, or, xor} as described in
+the ``tile.1d`` intrinsics.
+
+* The last argument to these intrinsics is a boolean flag indicating support for
+  cache_hint. This flag argument must be a compile-time constant. When set, it
+  indicates a valid cache_hint (``i64 %ch``) and generates the
+  ``.L2::cache_hint`` variant of the PTX instruction.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor>`_.
@@ -2122,14 +2129,14 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.cp.async.bulk.tensor.reduce.<red_op>.im2col.[3-5]d``' intrinsics
-correspond to the ``cp.reduce.async.bulk.tensor.[3-5]d.*`` set of PTX instructions.
-These instructions initiate an asynchronous reduction operation of tensor data
-in global memory with the tensor data in shared{::cta} memory, using ``im2col`` mode.
-In this mode, the tensor has to be at least three-dimensional. The supported reduction
-operations supported are the same as the ones in the tile mode. The last argument to
-these intrinsics is a boolean flag, with the same functionality as described in the
-``tile`` mode intrinsics above.
+The '``@llvm.nvvm.cp.async.bulk.tensor.reduce.<red_op>.im2col.[3-5]d``'
+intrinsics correspond to the ``cp.reduce.async.bulk.tensor.[3-5]d.*`` set of PTX
+instructions. These instructions initiate an asynchronous reduction operation of
+tensor data in global memory with the tensor data in shared{::cta} memory, using
+``im2col`` mode. In this mode, the tensor has to be at least three-dimensional.
+The supported reduction operations supported are the same as the ones in the
+tile mode. The last argument to these intrinsics is a boolean flag, with the
+same functionality as described in the ``tile`` mode intrinsics above.
 
 For more information, refer PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor>`_.
@@ -2238,11 +2245,17 @@ Syntax:
 Overview:
 """""""""
 
-The ``griddepcontrol`` intrinsics allows the dependent grids and prerequisite grids as defined by the runtime, to control execution in the following way:
+The ``griddepcontrol`` intrinsics allows the dependent grids and prerequisite
+grids as defined by the runtime, to control execution in the following way:
 
-``griddepcontrol.launch_dependents`` intrinsic signals that the dependents can be scheduled, before the current grid completes. The intrinsic can be invoked by multiple threads in the current CTA and repeated invocations of the intrinsic will have no additional side effects past that of the first invocation.
+``griddepcontrol.launch_dependents`` intrinsic signals that the dependents can
+be scheduled, before the current grid completes. The intrinsic can be invoked by
+multiple threads in the current CTA and repeated invocations of the intrinsic
+will have no additional side effects past that of the first invocation.
 
-``griddepcontrol.wait`` intrinsic causes the executing thread to wait until all prerequisite grids in flight have completed and all the memory operations from the prerequisite grids are performed and made visible to the current grid.
+``griddepcontrol.wait`` intrinsic causes the executing thread to wait until all
+prerequisite grids in flight have completed and all the memory operations from
+the prerequisite grids are performed and made visible to the current grid.
 
 For more information, refer 
 `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-griddepcontrol>`__.
@@ -2572,13 +2585,13 @@ Overview:
 The '``@llvm.nvvm.tcgen05.alloc.*``' intrinsics correspond to the
 ``tcgen05.alloc.cta_group*.sync.aligned.b32`` family of PTX instructions.
 The ``tcgen05.alloc`` is a potentially blocking instruction which dynamically
-allocates the specified number of columns in the Tensor Memory and writes
-the address of the allocated Tensor Memory into shared memory at the
-location specified by ``%dst``. The 32-bit operand ``%ncols`` specifies
-the number of columns to be allocated and it must be a power-of-two.
-The ``.shared`` variant explicitly uses shared memory address space for
-the ``%dst`` operand. The ``.cg1`` and ``.cg2`` variants generate
-``cta_group::1`` and ``cta_group::2`` variants of the instruction respectively.
+allocates the specified number of columns in the Tensor Memory and writes the
+address of the allocated Tensor Memory into shared memory at the location
+specified by ``%dst``. The 32-bit operand ``%ncols`` specifies the number of
+columns to be allocated and it must be a power-of-two. The ``.shared`` variant
+explicitly uses shared memory address space for the ``%dst`` operand. The
+``.cg1`` and ``.cg2`` variants generate ``cta_group::1`` and ``cta_group::2``
+variants of the instruction respectively.
 
 For more information, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-memory-allocation-and-management-instructions>`_.
@@ -2622,14 +2635,13 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.tcgen05.relinq.alloc.permit.*``' intrinsics correspond
-to the ``tcgen05.relinquish_alloc_permit.*`` set of PTX instructions.
-This instruction specifies that the CTA of the executing thread is
-relinquishing the right to allocate Tensor Memory. So, it is illegal
-for a CTA to perform ``tcgen05.alloc`` after any of its constituent
-threads execute ``tcgen05.relinquish_alloc_permit``. The ``.cg1``
-and ``.cg2`` variants generate ``cta_group::1`` and ``cta_group::2``
-flavors of the instruction respectively.
+The '``@llvm.nvvm.tcgen05.relinq.alloc.permit.*``' intrinsics correspond to the
+``tcgen05.relinquish_alloc_permit.*`` set of PTX instructions. This instruction
+specifies that the CTA of the executing thread is relinquishing the right to
+allocate Tensor Memory. So, it is illegal for a CTA to perform ``tcgen05.alloc``
+after any of its constituent threads execute
+``tcgen05.relinquish_alloc_permit``. The ``.cg1`` and ``.cg2`` variants generate
+``cta_group::1`` and ``cta_group::2`` flavors of the instruction respectively.
 
 For more information, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-memory-allocation-and-management-instructions>`_.
@@ -2653,10 +2665,11 @@ Overview:
 The '``@llvm.nvvm.tcgen05.commit.*``' intrinsics correspond to the
 ``tcgen05.commit.{cg1/cg2}.mbarrier::arrive::one.*`` set of PTX instructions.
 The ``tcgen05.commit`` is an asynchronous instruction which makes the mbarrier
-object (``%mbar``) track the completion of all prior asynchronous tcgen05 operations.
-The ``.mc`` variants allow signaling on the mbarrier objects of multiple CTAs
-(specified by ``%mc``) in the cluster. The ``.cg1`` and ``.cg2`` variants generate
-``cta_group::1`` and ``cta_group::2`` flavors of the instruction respectively.
+object (``%mbar``) track the completion of all prior asynchronous tcgen05
+operations. The ``.mc`` variants allow signaling on the mbarrier objects of
+multiple CTAs (specified by ``%mc``) in the cluster. The ``.cg1`` and ``.cg2``
+variants generate ```cta_group::1`` and ``cta_group::2`` flavors of the
+instruction respectively.
 
 For more information, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen-async-sync-operations-commit>`_.
@@ -2675,13 +2688,12 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.tcgen05.wait.ld/st``' intrinsics correspond to
-the ``tcgen05.wait::{ld/st}.sync.aligned`` pair of PTX instructions.
-The ``tcgen05.wait::ld`` causes the executing thread to block until
-all prior ``tcgen05.ld`` operations issued by the executing thread
-have completed. The ``tcgen05.wait::st`` causes the executing thread
-to block until all prior ``tcgen05.st`` operations issued by the
-executing thread have completed.
+The '``@llvm.nvvm.tcgen05.wait.ld/st``' intrinsics correspond to the
+``tcgen05.wait::{ld/st}.sync.aligned`` pair of PTX instructions. The
+``tcgen05.wait::ld`` causes the executing thread to block until all prior
+``tcgen05.ld`` operations issued by the executing thread have completed. The
+``tcgen05.wait::st`` causes the executing thread to block until all prior
+``tcgen05.st`` operations issued by the executing thread have completed.
 
 For more information, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instructions-tcgen05-wait>`_.
@@ -2700,10 +2712,9 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.tcgen05.fence.*``' intrinsics correspond to
-the ``tcgen05.fence::{before/after}_thread_sync`` pair of PTX instructions.
-These instructions act as code motion fences for asynchronous tcgen05
-operations.
+The '``@llvm.nvvm.tcgen05.fence.*``' intrinsics correspond to the
+``tcgen05.fence::{before/after}_thread_sync`` pair of PTX instructions. These
+instructions act as code motion fences for asynchronous tcgen05 operations.
 
 For more information, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tensorcore-5th-generation-instructions-tcgen05-fence>`_.
@@ -2722,12 +2733,12 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.tcgen05.shift.{cg1/cg2}``' intrinsics correspond to
-the ``tcgen05.shift.{cg1/cg2}`` PTX instructions. The ``tcgen05.shift``
-is an asynchronous instruction which initiates the shifting of 32-byte
-elements downwards across all the rows, except the last, by one row.
-The address operand ``%tmem_addr`` specifies the base address of the
-matrix in the Tensor Memory whose rows must be down shifted.
+The '``@llvm.nvvm.tcgen05.shift.{cg1/cg2}``' intrinsics correspond to the
+``tcgen05.shift.{cg1/cg2}`` PTX instructions. The ``tcgen05.shift`` is an
+asynchronous instruction which initiates the shifting of 32-byte elements
+downwards across all the rows, except the last, by one row. The address operand
+``%tmem_addr`` specifies the base address of the matrix in the Tensor Memory
+whose rows must be down shifted.
 
 For more information, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instructions-tcgen05-shift>`_.
@@ -2764,31 +2775,32 @@ Syntax:
 Overview:
 """""""""
 
-The '``@llvm.nvvm.tcgen05.cp.{shape}.{src_fmt}.{cg1/cg2}``' intrinsics
-correspond to the ``tcgen05.cp.*`` family of PTX instructions.
-The ``tcgen05.cp`` instruction initiates an asynchronous copy operation from
-shared memory to the location specified by ``%tmem_addr`` in Tensor Memory.
-The 64-bit register operand ``%sdesc`` is the matrix descriptor representing
-the source matrix in shared memory that needs to be copied.
+The '``@llvm.nvvm.tcgen05.cp.{shape}.{src_fmt}.{cg1/cg2}``' intrinsics 
+correspond to the ``tcgen05.cp.*`` family of PTX instructions. The
+``tcgen05.cp`` instruction initiates an asynchronous copy operation from shared
+memory to the location specified by ``%tmem_addr`` in Tensor Memory. The 64-bit
+register operand ``%sdesc`` is the matrix descriptor representing the source
+matrix in shared memory that needs to be copied.
 
 The valid shapes for the copy operation are:
-{128x256b, 4x256b, 128x128b, 64x128b_warpx2_02_13, 64x128b_warpx2_01_23, 32x128b_warpx4}.
+{128x256b, 4x256b, 128x128b, 64x128b_warpx2_02_13, 64x128b_warpx2_01_23,
+32x128b_warpx4}.
 
 Shapes ``64x128b`` and ``32x128b`` require dedicated multicast qualifiers,
 which are appended to the corresponding intrinsic names.
 
-Optionally, the data can be decompressed from the source format in the shared memory
-to the destination format in Tensor Memory during the copy operation. Currently,
-only ``.b8x16`` is supported as destination format. The valid source formats are
-``.b6x16_p32`` and ``.b4x16_p64``.
+Optionally, the data can be decompressed from the source format in the shared
+memory to the destination format in Tensor Memory during the copy operation.
+Currently, only ``.b8x16`` is supported as destination format. The valid source
+formats are ``.b6x16_p32`` and ``.b4x16_p64``.
 
-When the source format is ``.b6x16_p32``, a contiguous set of 16 elements of 6-bits
-each followed by four bytes of padding (``_p32``) in shared memory is decompressed
-into 16 elements of 8-bits (``.b8x16``) each in the Tensor Memory.
+When the source format is ``.b6x16_p32``, a contiguous set of 16 elements of
+6-bits each followed by four bytes of padding (``_p32``) in shared memory is
+decompressed into 16 elements of 8-bits (``.b8x16``) each in the Tensor Memory.
 
-When the source format is ``.b4x16_p64``, a contiguous set of 16 elements of 4-bits
-each followed by eight bytes of padding (``_p64``) in shared memory is decompressed
-into 16 elements of 8-bits (``.b8x16``) each in the Tensor Memory.
+When the source format is ``.b4x16_p64``, a contiguous set of 16 elements of
+4-bits each followed by eight bytes of padding (``_p64``) in shared memory is
+decompressed into 16 elements of 8-bits (``.b8x16``) each in the Tensor Memory.
 
 For more information on the decompression schemes, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/#optional-decompression>`_.
@@ -2811,25 +2823,29 @@ Syntax:
 Overview:
 """""""""
 
-This group of intrinsics asynchronously load data from the Tensor Memory at the location specified
-by the 32-bit address operand `tmem_addr` into the destination registers, collectively across all threads
-of the warps.
+This group of intrinsics asynchronously load data from the Tensor Memory at the
+ocation specified by the 32-bit address operand `tmem_addr` into the destination
+registers, collectively across all threads of the warps.
 
-All the threads in the warp must specify the same value of `tmem_addr`, which must be the base address
-of the collective load operation. Otherwise, the behavior is undefined.
+All the threads in the warp must specify the same value of `tmem_addr`, which
+must be the base address of the collective load operation. Otherwise, the
+behavior is undefined.
 
-The `shape` qualifier and the `num` qualifier together determines the total dimension of the data ('n') which
-is loaded from the Tensor Memory. The `shape` qualifier indicates the base dimension of data. The `num` qualifier
-indicates the repeat factor on the base dimension resulting in the total dimension of the data that is accessed.
+The `shape` qualifier and the `num` qualifier together determines the total
+dimension of the data ('n') which is loaded from the Tensor Memory. The `shape`
+qualifier indicates the base dimension of data. The `num` qualifier indicates
+the repeat factor on the base dimension resulting in the total dimension of the
+data that is accessed.
 
 Allowed values for the 'num' are `x1, x2, x4, x8, x16, x32, x64, x128`.
 
-Allowed values for the 'shape' in the first intrinsic are `16x64b, 16x128b, 16x256b, 32x32b`.
+Allowed values for the 'shape' in the first intrinsic are
+`16x64b, 16x128b, 16x256b, 32x32b`.
 
 Allowed value for the 'shape' in the second intrinsic is `16x32bx2`.
 
-The result of the intrinsic is a vector consisting of one or more 32-bit registers derived from `shape` and
-`num` as shown below.
+The result of the intrinsic is a vector consisting of one or more 32-bit
+registers derived from `shape` and `num` as shown below.
 
 =========== =========================  ==========  ==========
  num/shape     16x32bx2/16x64b/32x32b    16x128b    16x256b
@@ -2844,7 +2860,9 @@ The result of the intrinsic is a vector consisting of one or more 32-bit registe
  x128               128                    NA          NA
 =========== =========================  ==========  ==========
 
-The last argument `i1 %pack` is a compile-time constant which when set, indicates that the adjacent columns are packed into a single 32-bit element during the load
+The last argument `i1 %pack` is a compile-time constant which when set,
+indicates that the adjacent columns are packed into a single 32-bit element
+during the load.
 
 For more information, refer to the
 `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instructions-tcgen05-ld>`__.
@@ -2865,28 +2883,39 @@ Syntax:
 Overview:
 """""""""
 
-This group of intrinsics asynchronously store data from the source vector into the Tensor Memory at the location
-specified by the 32-bit address operand 'tmem_addr` collectively across all threads of the warps.
+This group of intrinsics asynchronously store data from the source vector into
+the Tensor Memory at the location specified by the 32-bit address operand
+'tmem_addr` collectively across all threads of the warps.
 
-All the threads in the warp must specify the same value of `tmem_addr`, which must be the base address of the
-collective load operation. Otherwise, the behavior is undefined.
+All the threads in the warp must specify the same value of `tmem_addr`, which
+must be the base address of the collective load operation. Otherwise, the
+behavior is undefined.
 
-The `shape` qualifier and the `num` qualifier together determines the total dimension of the data ('n') which
-is loaded from the Tensor Memory. The `shape` qualifier indicates the base dimension of data. The `num` qualifier
-indicates the repeat factor on the base dimension resulting in the total dimension of the data that is accessed.
+The `shape` qualifier and the `num` qualifier together determines the total
+dimension of the data ('n') which is loaded from the Tensor Memory. The `shape`
+qualifier indicates the base dimension of data. The `num` qualifier indicates
+the repeat factor on the base dimension resulting in the total dimension of the
+data that is accessed.
 
 Allowed values for the 'num' are `x1, x2, x4, x8, x16, x32, x64, x128`.
 
-Allowed values for the 'shape' in the first intrinsic are `16x64b, 16x128b, 16x256b, 32x32b`.
+Allowed values for the 'shape' in the first intrinsic are
+`16x64b, 16x128b, 16x256b, 32x32b`.
 
 Allowed value for the 'shape' in the second intrinsic is `16x32bx2`.
 
-`args` argument is a vector consisting of one or more 32-bit registers derived from `shape` and
-`num` as listed in the table listed in the `tcgen05.ld` section.
+`args` argument is a vector consisting of one or more 32-bit registers derived
+from `shape` and `num` as listed in the table listed in the `tcgen05.ld`
+section.
 
-Each shape support an `unpack` mode to allow a 32-bit element in the register to be unpacked into two 16-bit elements and store them in adjacent columns. `unpack` mode can be enabled by setting the `%unpack` operand to 1 and can be disabled by setting it to 0.
+Each shape support an `unpack` mode to allow a 32-bit element in the register to
+be unpacked into two 16-bit elements and store them in adjacent columns.
+`unpack` mode can be enabled by setting the `%unpack` operand to 1 and can be
+disabled by setting it to 0.
 
-The last argument `i1 %unpack` is a compile-time constant which when set, indicates that a 32-bit element in the register to be unpacked into two 16-bit elements and store them in adjacent columns.
+The last argument `i1 %unpack` is a compile-time constant which when set,
+indicates that a 32-bit element in the register to be unpacked into two 16-bit
+elements and store them in adjacent columns.
 
 For more information, refer to the
 `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instructions-tcgen05-st>`__.
@@ -2905,11 +2934,13 @@ accumulation of the form: `D =  A * B + D` where:
   - the `D` matrix is of the shape `M x N`, in `Tensor Memory`
 
 Optionally an input predicate can be used to disable the input (`%enable_inp_d`)
-from the accumulator matrix and the following operation can be performed as `D = A * B`
+from the accumulator matrix and the following operation can be performed as
+`D = A * B`
 
-The matrix multiplication and accumulation operations are categorized into various
-kinds based on input types and the throughput of the multiplication operation.
-The following table shows the different kinds of MMA operations that are supported:
+The matrix multiplication and accumulation operations are categorized into
+various kinds based on input types and the throughput of the multiplication
+operation. The following table shows the different kinds of MMA operations
+that are supported:
 
 +------------+--------------------------------------------+
 | .kind      | Supported Input Types                      |
@@ -2930,26 +2961,30 @@ The following table shows the different kinds of MMA operations that are support
 |            | (with common scaling factor)               |
 +------------+--------------------------------------------+
 
-`tcgen05.mma.sp` supports sparse variant of `A` with shape `M x K` stored in packed
-form as `M X (K / 2)` in memory. The `%spmetadata` specifies the mapping of the
-`K / 2` non-zero elements to the `K` elements before performing the MMA operation.
+`tcgen05.mma.sp` supports sparse variant of `A` with shape `M x K` stored in
+packed form as `M X (K / 2)` in memory. The `%spmetadata` specifies the mapping
+of the `K / 2` non-zero elements to the `K` elements before performing the MMA
+operation.
 
 `tcgen05.mma.block_scale` perform matrix multiplication with block scaling
 `D = (A * scale_A)  * (B * scale_B) + D` where scaling of input matrices from
-memory to form the matrix `A` and matrix `B` before performing the MMA operation.
-Scale factors for `A` and `B` matrices need to be duplicated to all 32 lane partitions
-of tensor memory. The shape of `%scale_a` and `%scale_b` matrices depend on the
-`.scale_vectorsize` described in `here <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-mma-scale-valid-comb>`__
+memory to form the matrix `A` and matrix `B` before performing the MMA
+operation. Scale factors for `A` and `B` matrices need to be duplicated to all
+32 lane partitions of tensor memory. The shape of `%scale_a` and `%scale_b`
+matrices depend on the `.scale_vectorsize` described in
+`here <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-mma-scale-valid-comb>`__
 
-The sparsity metadata (`%spmetadata`) as well as the block-scale inputs for `A / B`
-matrices (`%scale_a` and `%scale_b`) reside in Tensor Memory.
+The sparsity metadata (`%spmetadata`) as well as the block-scale inputs for
+`A / B` matrices (`%scale_a` and `%scale_b`) reside in Tensor Memory.
 
-To facilitate opportunistic re-use of `A / B` matrix data across a sequence of MMA
-operations, the `A/B` matrices are loaded into a collector buffer
-(`%collector_usage_a_op_flag`, `%collector_usage_b_buffer_flag`, and `%collector_usage_b_op_flag`).
-The flag value of the collector_usage flag in the intrinsic specifies the nature of the re-use
+To facilitate opportunistic re-use of `A / B` matrix data across a sequence of
+MMA operations, the `A/B` matrices are loaded into a collector buffer
+(`%collector_usage_a_op_flag`, `%collector_usage_b_buffer_flag`, and
+`%collector_usage_b_op_flag`). The flag value of the collector_usage flag in the
+intrinsic specifies the nature of the re-use
 
-There are three kinds of matrix descriptors used by the tcgen05 family of instructions:
+There are three kinds of matrix descriptors used by the tcgen05 family of
+instructions:
 
 +----------------------------+-----------------------------------------------------------------------------------------------------------+-------------+
 | Descriptor                 | Description                                                                                               | Size (bits) |
@@ -2970,38 +3005,40 @@ There are three kinds of matrix descriptors used by the tcgen05 family of instru
 |                            | `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__      |             |
 +----------------------------+-----------------------------------------------+-------------+---------------------------------------------+-------------+
 
-`tcgen05.mma` can be used for general matrix multiplication or for convolution operations.
-In case of convolutions, the `activations` can be stored in either matrix `A` or matrix `B`
-while the `weights` will be stored in the other matrix
-
-`tcgen05.mma` has an optional collector qualifier to specify when an `A` or `B` matrix
-is new to the sequence and should be loaded, unchanged within the sequence and,
-should be reused, or the last use in the sequence and should be discarded.
-The collector qualifier is used to give the TensorCore permission to reuse a
-previously loaded `A` or `B` matrix; however reuse is opportunistic in that the
-TensorCore may reload a matrix even when it has permission to reuse that matrix.
-Thus, the source memory of an A or B matrix must not be modified while the MMA
-instruction using those matrices has not completed - regardless of collector
-qualifier permissions.
-
-The `cta_group::1` specifies that the operation is performed on the Tensor Memory
-of the executing thread’s CTA only. The `cta_group::2` specifies that the MMA
-operation is performed on the Tensor Memory of the executing thread’s CTA and its peer CTA.
-
-The vector operand `%disable_output_lane` specifies the lane(s) in the Tensor Memory
-that should be not be updated with the resultant matrix D. Elements of the vector operand
-disable-output-lane forms a mask where each bit corresponds to a lane of the Tensor Memory,
-with least significant bit of the first element of the vector (leftmost in syntax)
-corresponding to the lane 0 of the Tensor Memory. If a bit in the mask is 1, then
-the corresponding lane in the Tensor Memory for the resultant matrix D will not be
-updated
+`tcgen05.mma` can be used for general matrix multiplication or for convolution
+operations. In case of convolutions, the `activations` can be stored in either
+matrix `A` or matrix `B` while the `weights` will be stored in the other matrix
+
+`tcgen05.mma` has an optional collector qualifier to specify when an `A` or `B`
+matrix is new to the sequence and should be loaded, unchanged within the
+sequence and, should be reused, or the last use in the sequence and should be
+discarded. The collector qualifier is used to give the TensorCore permission to
+reuse a previously loaded `A` or `B` matrix; however reuse is opportunistic in
+that the TensorCore may reload a matrix even when it has permission to reuse
+that matrix. Thus, the source memory of an A or B matrix must not be modified
+while the MMA instruction using those matrices has not completed - regardless of
+collector qualifier permissions.
+
+The `cta_group::1` specifies that the operation is performed on the Tensor
+Memory of the executing thread’s CTA only. The `cta_group::2` specifies that the
+MMA operation is performed on the Tensor Memory of the executing thread’s CTA
+and its peer CTA.
+
+The vector operand `%disable_output_lane` specifies the lane(s) in the Tensor
+Memory that should be not be updated with the resultant matrix D. Elements of
+the vector operand disable-output-lane forms a mask where each bit corresponds
+to a lane of the Tensor Memory, with least significant bit of the first element
+of the vector (leftmost in syntax) corresponding to the lane 0 of the Tensor
+Memory. If a bit in the mask is 1, then the corresponding lane in the Tensor
+Memory for the resultant matrix D will not be updated
 
 Intrinsic Design:
 ^^^^^^^^^^^^^^^^^
 
 Given the broad feature set of `tcgen05.mma` instruction modeling these
 through intrinsics is highly complex, and the following table outlines the large
-number of intrinsics required to fully support the `tcgen05.mma` instruction set.
+number of intrinsics required to fully support the `tcgen05.mma` instruction
+set.
 
 +------------------------------------+---------------------------------------------------------------------------------------------------+----------------+
 | variant                            | Configuration                                                                                     | Total Variants |
@@ -3030,10 +3067,10 @@ number of intrinsics required to fully support the `tcgen05.mma` instruction set
 +------------------------------------+---------------------------------------------------------------------------------------------------+----------------+
 
 
-To reduce the number of possible intrinsic variations, we've modeled the `tcgen05.mma`
-instructions using flag operands. We've added range checks to these flags to prevent
-invalid values. We also expanded some flags back into intrinsic modifiers to avoid
-supporting invalid combinations of features.
+To reduce the number of possible intrinsic variations, we've modeled the
+`tcgen05.mma` instructions using flag operands. We've added range checks to
+these flags to prevent invalid values. We also expanded some flags back into
+intrinsic modifiers to avoid supporting invalid combinations of features.
 
 
 '``llvm.nvvm.tcgen05.mma.*``'
@@ -3062,29 +3099,31 @@ Syntax:
 Overview:
 """""""""
 
-`nvvm.tcgen05.mma` is an asynchronous intrinsic which initiates an `M x N x K` matrix
-multiply and accumulate operation, `D = A * B + D` where the `A` matrix is `M x K`,
-the `B` matrix is `K x N`, and the `D` matrix is `M x N`. The operation of the form
-`D = A*B` is issued when the input predicate argument `%enable_inp_d` is false.
-The optional immediate argument `%scale_d_imm` can be specified to scale the input
-matrix `D` as follows: `D = A * B + D * (2 ^ - %scale_d_imm)`. The valid range of
-values for argument `%scale_d_imm` is `[0, 15]`. The 32-bit register operand idesc
-is the instruction descriptor as described in `Instruction descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__
-
-`nvvm.tcgen05.mma` has single thread semantics, unlike the collective instructions
-`nvvm.mma.sync` or the PTX `wgmma.mma_async` instruction. So, a single thread issuing
-the `nvvm.tcgen05.mma` will result in the initiation of the whole matrix and accumulate
-operation
+`nvvm.tcgen05.mma` is an asynchronous intrinsic which initiates an `M x N x K`
+matrix multiply and accumulate operation, `D = A * B + D` where the `A` matrix
+is `M x K`, the `B` matrix is `K x N`, and the `D` matrix is `M x N`. The
+operation of the form `D = A*B` is issued when the input predicate argument
+`%enable_inp_d` is false. The optional immediate argument `%scale_d_imm` can be
+specified to scale the input matrix `D` as follows:
+`D = A * B + D * (2 ^ - %scale_d_imm)`. The valid range of values for argument
+`%scale_d_imm` is `[0, 15]`. The 32-bit register operand idesc is the
+instruction descriptor as described in
+`Instruction descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__
+
+`nvvm.tcgen05.mma` has single thread semantics, unlike the collective
+instructions `nvvm.mma.sync` or the PTX `wgmma.mma_async` instruction. So, a
+single thread issuing the `nvvm.tcgen05.mma` will result in the initiation of
+the whole matrix and accumulate operation
 
 When `.sp` is specifed, the dimension of A matrix is `M x (K/2)` and requires
 specifying an additional `%spmetadata` argument
 
-`.ashift` shifts the rows of the A matrix down by one row, except for the last row
-in the Tensor Memory. `.ashift` is only allowed with M = 128 or M = 256.
+`.ashift` shifts the rows of the A matrix down by one row, except for the last
+row in the Tensor Memory. `.ashift` is only allowed with M = 128 or M = 256.
 
-The `%collector_usage_a_op_flag` flag specifies the usage of collector buffer for
-matrix `A`. It is illegal to specify either of `USE` or `FILL` for `%collector_usage_a_op_flag`
-along with `.ashift`
+The `%collector_usage_a_op_flag` flag specifies the usage of collector buffer
+for matrix `A`. It is illegal to specify either of `USE` or `FILL` for
+`%collector_usage_a_op_flag` along with `.ashift`
 
 For more information, refer to the
 `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-mma-instructions-mma>`__
@@ -3162,13 +3201,26 @@ Syntax:
 
 Overview:
 """""""""
-`nvvm.tcgen05.mma.block_scale` is an asynchronous intrinsic which initiates an `M x N x K` matrix multiply and accumulate operation, `D = (A * scale_a)  * (B * scale_b) + D` where the `A` matrix is `M x K`, the `B` matrix is `K x N`, and the `D` matrix is `M x N`. The matrices `A` and `B` are scaled with `%scale_A` and `%scale_B` matrices respectively before performing the matrix multiply and accumulate operation. The operation of the form `D = A*B` is issued when the input predicate argument `%enable_inp_d` is false. The 32-bit register operand idesc is the instruction descriptor as described in `Instruction descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__
-
-`nvvm.tcgen05.mma.block_scale` has single thread semantics, unlike the collective instructions `nvvm.mma.sync` or the PTX `wgmma.mma_async` instruction. So, a single thread issuing the `nvvm.tcgen05.mma.block_scale` will result in the initiation of the whole matrix multiply and accumulate operation
-
-When `.sp` is specified, the dimension of A matrix is `M x (K / 2)` and requires specifying an additional `%spmetadata` argument
+`nvvm.tcgen05.mma.block_scale` is an asynchronous intrinsic which initiates
+an `M x N x K` matrix multiply and accumulate operation
+`D = (A * scale_a)  * (B * scale_b) + D` where the `A` matrix is `M x K`, the
+`B` matrix is `K x N`, and the `D` matrix is `M x N`. The matrices `A` and `B`
+are scaled with `%scale_A` and `%scale_B` matrices respectively before
+performing the matrix multiply and accumulate operation. The operation of the
+form `D = A*B` is issued when the input predicate argument `%enable_inp_d` is
+false. The 32-bit register operand idesc is the instruction descriptor as
+described in `Instruction descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__
+
+`nvvm.tcgen05.mma.block_scale` has single thread semantics, unlike the
+collective instructions `nvvm.mma.sync` or the PTX `wgmma.mma_async`
+instruction. So, a single thread issuing the `nvvm.tcgen05.mma.block_scale` will
+result in the initiation of the whole matrix multiply and accumulate operation.
+
+When `.sp` is specified, the dimension of A matrix is `M x (K / 2)` and requires
+specifying an additional `%spmetadata` argument
 
-The `%collector_usage_a_op_flag` flag specifies the usage of collector buffer for matrix `A`
+The `%collector_usage_a_op_flag` flag specifies the usage of collector buffer
+for matrix `A`
 
 For more information, refer to the
 `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-mma-instructions-mma>`__
@@ -3229,17 +3281,40 @@ Syntax:
 Overview:
 """""""""
 
-`nvvm.tcgen05.mma.disable_output_lane` is an asynchronous intrinsic which initiates an `M x N x K` matrix multiply and accumulate operation, `D = A * B + D` where the `A` matrix is `M x K`, the `B` matrix is `K x N`, and the `D` matrix is `M x N`. The operation of the form `D = A*B` is issued when the input predicate argument `%enable_inp_d` is false. The optional immediate argument `%scale_d_imm` can be specified to scale the input matrix `D` as follows: `D = A*B+D * (2 ^ - %scale_d_imm)`. The valid range of values for argument `%scale_d_imm` is `[0, 15]`. The 32-bit register operand idesc is the instruction descriptor as described in `Instruction descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__
-
-The vector operand `%disable_output_lane` specifies the lane(s) in the Tensor Memory that should be not be updated with the resultant matrix `D`. Elements of the vector operand `%disable_output_lane` forms a mask where each bit corresponds to a lane of the Tensor Memory, with least significant bit of the first element of the vector corresponding to the `lane 0` of the Tensor Memory. If a bit in the mask is 1, then the corresponding lane in the Tensor Memory for the resultant matrix `D` will not be updated
-
-`nvvm.tcgen05.mma.disable_output_lane` has single thread semantics, unlike the collective instructions `nvvm.mma.sync` or the PTX `wgmma.mma_async` instruction. So, a single thread issuing the `nvvm.tcgen05.mma.disable_output_lane` will result in the initiation of the whole matrix multiply and accumulate operation
-
-When `.sp` is specifed, the dimension of A matrix is `M x (K / 2)` and requires specifiying an additional `%spmetadata` argument
-
-`.ashift` shifts the rows of the A matrix down by one row, except for the last row in the Tensor Memory. `.ashift` is only allowed with M = 128 or M = 256.
-
-The `%collector_usage_a_op_flag` flag specifies the usage of collector buffer for matrix `A`. It is illegal to specify either of `USE` or `FILL` for `%collector_usage_a_op_flag` along with `.ashift`
+`nvvm.tcgen05.mma.disable_output_lane` is an asynchronous intrinsic which
+initiates an `M x N x K` matrix multiply and accumulate operation
+`D = A * B + D` where the `A` matrix is `M x K`, the `B` matrix is `K x N`, and
+the `D` matrix is `M x N`. The operation of the form `D = A*B` is issued when
+the input predicate argument `%enable_inp_d` is false. The optional immediate
+argument `%scale_d_imm` can be specified to scale the input matrix `D` as
+follows: `D = A*B+D * (2 ^ - %scale_d_imm)`. The valid range of values for
+argument `%scale_d_imm` is `[0, 15]`. The 32-bit register operand idesc is the
+instruction descriptor as described in
+`Instruction descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__
+
+The vector operand `%disable_output_lane` specifies the lane(s) in the Tensor
+Memory that should be not be updated with the resultant matrix `D`. Elements of
+the vector operand `%disable_output_lane` forms a mask where each bit
+corresponds to a lane of the Tensor Memory, with least significant bit of the
+first element of the vector corresponding to the `lane 0` of the Tensor Memory.
+If a bit in the mask is 1, then the corresponding lane in the Tensor Memory for
+the resultant matrix `D` will not be updated
+
+`nvvm.tcgen05.mma.disable_output_lane` has single thread semantics, unlike the
+collective instructions `nvvm.mma.sync` or the PTX `wgmma.mma_async`
+instruction. So, a single thread issuing the
+`nvvm.tcgen05.mma.disable_output_lane` will result in the initiation of the
+whole matrix multiply and accumulate operation
+
+When `.sp` is specifed, the dimension of A matrix is `M x (K / 2)` and requires
+specifiying an additional `%spmetadata` argument.
+
+ `.ashift` shifts the rows of the A matrix down by one row, except for the last
+ row in the Tensor Memory. `.ashift` is only allowed with M = 128 or M = 256.
+
+The `%collector_usage_a_op_flag` flag specifies the usage of collector buffer
+for matrix `A`. It is illegal to specify either of `USE` or `FILL` for
+`%collector_usage_a_op_flag` along with `.ashift`
 
 For more information, refer to the `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-mma-instructions-mma>`__
 
@@ -3301,15 +3376,33 @@ Syntax:
 Overview:
 """""""""
 
-`nvvm.tcgen05.mma.ws` is an asynchronous intrinsic which initiates an `M x N x K` weight stationary convolution matrix multiply and accumulate operation, `D = A * B + D` where the `A` matrix is `M x K`, the `B` matrix is `K x N`, and the `D` matrix is `M x N`. The operation of the form `D = A*B` is issued when the input predicate argument `%enable_inp_d` is false. The optional immediate argument `%scale_d_imm` can be specified to scale the input matrix `D` as follows: `D = A*B+D * (2 ^ - %scale_d_imm)`. The valid range of values for argument `%scale_d_imm` is `[0, 15]`. The 32-bit register operand idesc is the instruction descriptor as described in `Instruction descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__
-
-`nvvm.tcgen05.mma` has single thread semantics, unlike the collective instructions `nvvm.mma.sync` or the PTX `wgmma.mma_async` instruction. So, a single thread issuing the `nvvm.tcgen05.mma` will result in the initiation of the whole matrix multiply and accumulate operation
-
-When `.sp` is specifed, the dimension of A matrix is `M x (K / 2)` and requires specifiying an additional `%spmetadata` argument
-
-The operand `%zero_col_mask` is a 64-bit register which specifies the `Zero-Column Mask Descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-zero-column-mask-descriptor>`__. The zero-column mask descriptor is used to generate a mask that specifies which columns of `B` matrix will have zero value for the matrix multiply and accumulate operation regardless of the values present in the shared memory.
-
-The `%collector_usage_b_buffer_flag` and `%collector_usage_b_op_flag` together flag specifies the usage of collector buffer for Matrix `B`
+`nvvm.tcgen05.mma.ws` is an asynchronous intrinsic which initiates an
+`M x N x K` weight stationary convolution matrix multiply and accumulate
+operation, `D = A * B + D` where the `A` matrix is `M x K`, the `B` matrix is
+`K x N`, and the `D` matrix is `M x N`. The operation of the form `D = A*B` is
+issued when the input predicate argument `%enable_inp_d` is false. The optional
+immediate argument `%scale_d_imm` can be specified to scale the input matrix `D`
+as follows: `D = A*B+D * (2 ^ - %scale_d_imm)`. The valid range of values for
+argument `%scale_d_imm` is `[0, 15]`. The 32-bit register operand idesc is the
+instruction descriptor as described in
+`Instruction descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-instruction-descriptor>`__
+
+`nvvm.tcgen05.mma` has single thread semantics, unlike the collective
+instructions `nvvm.mma.sync` or the PTX `wgmma.mma_async` instruction. So, a
+single thread issuing the `nvvm.tcgen05.mma` will result in the initiation of
+the whole matrix multiply and accumulate operation
+
+When `.sp` is specifed, the dimension of A matrix is `M x (K / 2)` and requires
+specifiying an additional `%spmetadata` argument
+
+The operand `%zero_col_mask` is a 64-bit register which specifies the
+`Zero-Column Mask Descriptor <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-zero-column-mask-descriptor>`__.
+The zero-column mask descriptor is used to generate a mask that specifies which
+columns of `B` matrix will have zero value for the matrix multiply and
+accumulate operation regardless of the values present in the shared memory.
+
+The `%collector_usage_b_buffer_flag` and `%collector_usage_b_op_flag` together
+flag specifies the usage of collector buffer for Matrix `B`.
 
 For more information, refer to the
 `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-mma-instructions-mma-ws>`__
@@ -3377,9 +3470,11 @@ The integer immediate operand `%initval` specifies the initialization value for
 the memory locations. The only numeric value allowed is 0.
 
 The ``@llvm.nvvm.st.bulk.shared.cta`` and ``@llvm.nvvm.st.bulk`` intrinsics are 
-similar but the latter uses generic addressing (see `Generic Addressing <https://docs.nvidia.com/cuda/parallel-thread-execution/#generic-addressing>`__).
+similar but the latter uses generic addressing (see `Generic Addressing
+<https://docs.nvidia.com/cuda/parallel-thread-execution/#generic-addressing>`__).
 
-For more information, refer `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st-bulk>`__.
+For more information, refer `PTX ISA
+<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st-bulk>`__.
 
 
 clusterlaunchcontrol Intrinsics
@@ -3400,21 +3495,22 @@ Overview:
 """""""""
 
 The ``clusterlaunchcontrol.try_cancel`` intrinsics requests atomically cancelling
-the launch of a cluster that has not started running yet. It asynchronously non-atomically writes
-a 16-byte opaque response to shared memory, pointed to by 16-byte-aligned ``addr`` indicating whether the
-operation succeeded or failed. ``addr`` and 8-byte-aligned ``mbar`` must refer to ``shared::cta``
-otherwise the behavior is undefined. The completion of the asynchronous operation
-is tracked using the mbarrier completion mechanism at ``.cluster`` scope referenced
-by the shared memory pointer, ``mbar``. On success, the opaque response contains
-the CTA id of the first CTA of the canceled cluster; no other successful response
-from other ``clusterlaunchcontrol.try_cancel`` operations from the same grid will
-contain that id.
-
-The ``multicast`` variant specifies that the response is asynchronously non-atomically written to
-the corresponding shared memory location of each CTA in the requesting cluster.
-The completion of the write of each local response is tracked by independent
-mbarriers at the corresponding shared memory location of each CTA in the
-cluster.
+the launch of a cluster that has not started running yet. It asynchronously
+non-atomically writes a 16-byte opaque response to shared memory, pointed to by
+16-byte-aligned ``addr`` indicating whether the operation succeeded or failed.
+``addr`` and 8-byte-aligned ``mbar`` must refer to ``shared::cta`` otherwise the
+behavior is undefined. The completion of the asynchronous operation is tracked
+using the mbarrier completion mechanism at ``.cluster`` scope referenced by the
+shared memory pointer, ``mbar``. On success, the opaque response contains the
+CTA id of the first CTA of the canceled cluster; no other successful response
+from other ``clusterlaunchcontrol.try_cancel`` operations from the same grid
+will contain that id.
+
+The ``multicast`` variant specifies that the response is asynchronously
+non-atomically written to the corresponding shared memory location of each CTA
+in the requesting cluster. The completion of the write of each local response is
+tracked by independent mbarriers at the corresponding shared memory location of
+each CTA in theccluster.
 
 For more information, refer `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/?a#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-try-cancel>`__.
 
@@ -3431,16 +3527,17 @@ Syntax:
 Overview:
 """""""""
 
-The ``llvm.nvvm.clusterlaunchcontrol.query_cancel.is_canceled`` intrinsic decodes the opaque response written by the
+The ``llvm.nvvm.clusterlaunchcontrol.query_cancel.is_canceled`` intrinsic
+decodes the opaque response written by the
 ``llvm.nvvm.clusterlaunchcontrol.try_cancel`` operation.
 
-The intrinsic returns ``0`` (false) if the request failed. If the request succeeded,
-it returns ``1`` (true). A true result indicates that:
+The intrinsic returns ``0`` (false) if the request failed. If the request
+succeeded, it returns ``1`` (true). A true result indicates that:
 
 - the thread block cluster whose first CTA id matches that of the response
   handle will not run, and
-- no other successful response of another ``try_cancel`` request in the grid will contain
-  the first CTA id of that cluster
+- no other successful response of another ``try_cancel`` request in the grid
+  will contain the first CTA id of that cluster
 
 For more information, refer `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/?a#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-query-cancel>`__.
 
@@ -3466,8 +3563,9 @@ used to decode the successful opaque response written by the
 
 If the request succeeded:
 
-- ``llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.{x,y,z}`` returns
-  the coordinate of the first CTA in the canceled cluster, either x, y, or z.
+- ``llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.{x,y,z}``
+  returns the coordinate of the first CTA in the canceled cluster, either x, y,
+  or z.
 
 If the request failed, the behavior of these intrinsics is undefined.
 
@@ -3489,9 +3587,9 @@ Syntax:
 Overview:
 """""""""
 
-The '``llvm.nvvm.pm.event.mask``' intrinsic triggers one or more
-performance monitor events. Each bit in the 16-bit immediate operand
-``%mask_val`` controls an event.
+The '``llvm.nvvm.pm.event.mask``' intrinsic triggers one or more performance
+monitor events. Each bit in the 16-bit immediate operand `%mask_val`` controls
+an event.
 
 For more information on the pmevent instructions, refer to the PTX ISA
 `<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#miscellaneous-instructions-pmevent>`_.