[llvm] [AArch64] Increase allocation priority of restricted ZReg classes (PR #176419)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 16 08:12:57 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Momchil Velikov (momchil-velikov)
<details>
<summary>Changes</summary>
Some SVE instructions require Z-register operands from a restricted ranges, e.g. `z0`-`z7` or `z0`-`z15`. When all the registers in a restricted range are allocated, the register allocator may generate spills/reloads even though there are still registers available from the unrestricted range and an existing unrestricted allocation can be "renamed" to use one of these registers.
The issue is further exacerbated by the fact that the register allocator tends to allocate lower-numbered registers first, thus unnecessarily consuming the restricted registers early on.
To mitigate this, increase the allocation priority of the restricted ZReg classes so that they are allocated first. This increases the likelihood that registers from the restricted ranges are available when needed.
The test case is derived from an ACLE program that uses SVE to do tiled matrix multiplication of 293x768 by 768x50257 matrices using tile size of 8x(vscale * 8). This ACLE program is in turn derived from and intended to represent a MLIR-generated matrix multiplication kernel.
We have observed about 23% improvement in the ACLE kernel's execution time on Graviton 4 when this change is applied with no notable regressions on SPEC benchmarks.
---
Patch is 34.38 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/176419.diff
2 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.td (+2)
- (added) llvm/test/CodeGen/AArch64/zreg-alloc-prio.mir (+511)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index cd94a2590c6d2..fd4a9401f95f9 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -1194,9 +1194,11 @@ def ZPR : ZPRClass<0, 31> {
}
def ZPR_4b : ZPRClass<0, 15> { // Restricted 4 bit SVE vector register class.
let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 16>";
+ let AllocationPriority = 1;
}
def ZPR_3b : ZPRClass<0, 7> { // Restricted 3 bit SVE vector register class.
let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 8>";
+ let AllocationPriority = 2;
}
class ZPRAsmOperand<string name, int Width, string RegClassSuffix = "">
diff --git a/llvm/test/CodeGen/AArch64/zreg-alloc-prio.mir b/llvm/test/CodeGen/AArch64/zreg-alloc-prio.mir
new file mode 100644
index 0000000000000..38a79ac528fc8
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/zreg-alloc-prio.mir
@@ -0,0 +1,511 @@
+# RUN: llc %s --run-pass=greedy -o - | FileCheck %s
+--- |
+ target triple = "aarch64-linux"
+
+ define void @f(ptr %A, ptr %B, ptr %C) #0 {
+ entry:
+ %splitgep11 = getelementptr i8, ptr %C, i64 1005140
+ %splitgep10 = getelementptr i8, ptr %C, i64 804112
+ %splitgep9 = getelementptr i8, ptr %C, i64 603084
+ %splitgep8 = getelementptr i8, ptr %C, i64 402056
+ %splitgep7 = getelementptr i8, ptr %C, i64 201028
+ %vs = tail call i64 @llvm.vscale.i64()
+ %0 = shl i64 %vs, 4
+ %1 = add i64 %0, 603084
+ %2 = add i64 %0, 402056
+ %3 = add i64 %0, 201021
+ br label %loop
+
+ loop: ; preds = %loop, %entry
+ %lsr.iv = phi i64 [ %lsr.iv.next, %loop ], [ -4, %entry ]
+ %A.addr = phi ptr [ %A, %entry ], [ %A.addr.next, %loop ]
+ %acc00 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc00.t3, %loop ]
+ %acc01 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc01.t3, %loop ]
+ %acc10 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc10.t3, %loop ]
+ %acc11 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc11.t3, %loop ]
+ %acc20 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc20.t3, %loop ]
+ %acc21 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc21.t3, %loop ]
+ %acc30 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc30.t3, %loop ]
+ %acc31 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc31.t3, %loop ]
+ %acc40 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc40.t3, %loop ]
+ %acc41 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc41.t3, %loop ]
+ %acc50 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc50.t3, %loop ]
+ %acc51 = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %acc51.t3, %loop ]
+ %B.addr = phi ptr [ %B, %entry ], [ %splitgep6, %loop ]
+ %splitgep6 = getelementptr i8, ptr %B.addr, i64 804112
+ %splitgep5 = getelementptr i8, ptr %B.addr, i64 603084
+ %splitgep4 = getelementptr i8, ptr %B.addr, i64 402056
+ %splitgep = getelementptr i8, ptr %B.addr, i64 201021
+ %A0.n = load <4 x float>, ptr %A.addr, align 4
+ %A0.z = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %A0.n, i64 0)
+ %A0.b = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %A0.z, i64 0)
+ %A.addr.1 = getelementptr i8, ptr %A.addr, i64 3072
+ %A1.n = load <4 x float>, ptr %A.addr.1, align 4
+ %A1.z = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %A1.n, i64 0)
+ %A1.b = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %A1.z, i64 0)
+ %A.addr.2 = getelementptr i8, ptr %A.addr, i64 6144
+ %A2.n = load <4 x float>, ptr %A.addr.2, align 4
+ %A2.z = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %A2.n, i64 0)
+ %A2.b = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %A2.z, i64 0)
+ %A.addr.3 = getelementptr i8, ptr %A.addr, i64 9216
+ %A3.n = load <4 x float>, ptr %A.addr.3, align 4
+ %A3.z = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %A3.n, i64 0)
+ %A3.b = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %A3.z, i64 0)
+ %A.addr.4 = getelementptr i8, ptr %A.addr, i64 12288
+ %A4.n = load <4 x float>, ptr %A.addr.4, align 4
+ %A4.z = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %A4.n, i64 0)
+ %A4.b = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %A4.z, i64 0)
+ %A.addr.5 = getelementptr i8, ptr %A.addr, i64 15360
+ %A5.n = load <4 x float>, ptr %A.addr.5, align 4
+ %A5.z = tail call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> undef, <4 x float> %A5.n, i64 0)
+ %A5.b = tail call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %A5.z, i64 0)
+ %B00 = load <vscale x 4 x float>, ptr %B.addr, align 16
+ %4 = tail call i64 @llvm.vscale.i64()
+ %5 = shl i64 %4, 4
+ %scevgep3 = getelementptr i8, ptr %B.addr, i64 %5
+ %B01 = load <vscale x 4 x float>, ptr %scevgep3, align 16
+ %acc00.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc00, <vscale x 4 x float> %B00, <vscale x 4 x float> %A0.b, i32 0)
+ %acc01.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc01, <vscale x 4 x float> %B01, <vscale x 4 x float> %A0.b, i32 0)
+ %acc10.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc10, <vscale x 4 x float> %B00, <vscale x 4 x float> %A1.b, i32 0)
+ %acc11.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc11, <vscale x 4 x float> %B01, <vscale x 4 x float> %A1.b, i32 0)
+ %acc20.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc20, <vscale x 4 x float> %B00, <vscale x 4 x float> %A2.b, i32 0)
+ %acc21.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc21, <vscale x 4 x float> %B01, <vscale x 4 x float> %A2.b, i32 0)
+ %acc30.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc30, <vscale x 4 x float> %B00, <vscale x 4 x float> %A3.b, i32 0)
+ %acc31.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc31, <vscale x 4 x float> %B01, <vscale x 4 x float> %A4.b, i32 0)
+ %acc40.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc40, <vscale x 4 x float> %B00, <vscale x 4 x float> %A5.b, i32 0)
+ %acc41.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc41, <vscale x 4 x float> %B01, <vscale x 4 x float> %A5.b, i32 0)
+ %acc50.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc50, <vscale x 4 x float> %B00, <vscale x 4 x float> %A5.b, i32 0)
+ %acc51.t0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc51, <vscale x 4 x float> %B01, <vscale x 4 x float> %A5.b, i32 0)
+ %B10 = load <vscale x 4 x float>, ptr %splitgep, align 16
+ %scevgep2 = getelementptr i8, ptr %B.addr, i64 %3
+ %B11 = load <vscale x 4 x float>, ptr %scevgep2, align 16
+ %acc00.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc00.t0, <vscale x 4 x float> %B10, <vscale x 4 x float> %A0.b, i32 1)
+ %acc01.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc01.t0, <vscale x 4 x float> %B11, <vscale x 4 x float> %A0.b, i32 1)
+ %acc10.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc10.t0, <vscale x 4 x float> %B10, <vscale x 4 x float> %A1.b, i32 1)
+ %acc11.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc11.t0, <vscale x 4 x float> %B11, <vscale x 4 x float> %A1.b, i32 1)
+ %acc20.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc20.t0, <vscale x 4 x float> %B10, <vscale x 4 x float> %A2.b, i32 1)
+ %acc21.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc21.t0, <vscale x 4 x float> %B11, <vscale x 4 x float> %A2.b, i32 1)
+ %acc30.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc30.t0, <vscale x 4 x float> %B10, <vscale x 4 x float> %A3.b, i32 1)
+ %acc31.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc31.t0, <vscale x 4 x float> %B11, <vscale x 4 x float> %A3.b, i32 1)
+ %acc40.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc40.t0, <vscale x 4 x float> %B10, <vscale x 4 x float> %A4.b, i32 1)
+ %acc41.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc41.t0, <vscale x 4 x float> %B11, <vscale x 4 x float> %A4.b, i32 1)
+ %acc50.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc50.t0, <vscale x 4 x float> %B10, <vscale x 4 x float> %A5.b, i32 1)
+ %acc51.t1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc51.t0, <vscale x 4 x float> %B11, <vscale x 4 x float> %A5.b, i32 1)
+ %B20 = load <vscale x 4 x float>, ptr %splitgep4, align 16
+ %scevgep1 = getelementptr i8, ptr %B.addr, i64 %2
+ %B21 = load <vscale x 4 x float>, ptr %scevgep1, align 16
+ %acc00.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc00.t1, <vscale x 4 x float> %B20, <vscale x 4 x float> %A0.b, i32 2)
+ %acc01.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc01.t1, <vscale x 4 x float> %B21, <vscale x 4 x float> %A0.b, i32 2)
+ %acc10.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc10.t1, <vscale x 4 x float> %B20, <vscale x 4 x float> %A1.b, i32 2)
+ %acc11.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc11.t1, <vscale x 4 x float> %B21, <vscale x 4 x float> %A1.b, i32 2)
+ %acc20.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc20.t1, <vscale x 4 x float> %B20, <vscale x 4 x float> %A2.b, i32 2)
+ %acc21.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc21.t1, <vscale x 4 x float> %B21, <vscale x 4 x float> %A2.b, i32 2)
+ %acc30.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc30.t1, <vscale x 4 x float> %B20, <vscale x 4 x float> %A3.b, i32 2)
+ %acc31.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc31.t1, <vscale x 4 x float> %B21, <vscale x 4 x float> %A3.b, i32 2)
+ %acc40.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc40.t1, <vscale x 4 x float> %B20, <vscale x 4 x float> %A4.b, i32 2)
+ %acc41.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc41.t1, <vscale x 4 x float> %B21, <vscale x 4 x float> %A4.b, i32 2)
+ %acc50.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc50.t1, <vscale x 4 x float> %B20, <vscale x 4 x float> %A5.b, i32 2)
+ %acc51.t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc51.t1, <vscale x 4 x float> %B21, <vscale x 4 x float> %A5.b, i32 2)
+ %B30 = load <vscale x 4 x float>, ptr %splitgep5, align 16
+ %scevgep = getelementptr i8, ptr %B.addr, i64 %1
+ %B31 = load <vscale x 4 x float>, ptr %scevgep, align 16
+ %acc00.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc00.t2, <vscale x 4 x float> %B30, <vscale x 4 x float> %A0.b, i32 3)
+ %acc01.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc01.t2, <vscale x 4 x float> %B31, <vscale x 4 x float> %A0.b, i32 3)
+ %acc10.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc10.t2, <vscale x 4 x float> %B30, <vscale x 4 x float> %A1.b, i32 3)
+ %acc11.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc11.t2, <vscale x 4 x float> %B31, <vscale x 4 x float> %A1.b, i32 3)
+ %acc20.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc20.t2, <vscale x 4 x float> %B30, <vscale x 4 x float> %A2.b, i32 3)
+ %acc21.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc21.t2, <vscale x 4 x float> %B31, <vscale x 4 x float> %A2.b, i32 3)
+ %acc30.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc30.t2, <vscale x 4 x float> %B30, <vscale x 4 x float> %A3.b, i32 3)
+ %acc31.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc31.t2, <vscale x 4 x float> %B31, <vscale x 4 x float> %A3.b, i32 3)
+ %acc40.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc40.t2, <vscale x 4 x float> %B30, <vscale x 4 x float> %A4.b, i32 3)
+ %acc41.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc41.t2, <vscale x 4 x float> %B31, <vscale x 4 x float> %A4.b, i32 3)
+ %acc50.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc50.t2, <vscale x 4 x float> %B30, <vscale x 4 x float> %A5.b, i32 3)
+ %acc51.t3 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmla.lane.nxv4f32(<vscale x 4 x float> %acc51.t2, <vscale x 4 x float> %B31, <vscale x 4 x float> %A5.b, i32 3)
+ %A.addr.next = getelementptr i8, ptr %A.addr, i64 16
+ %lsr.iv.next = add nsw i64 %lsr.iv, 4
+ %cmp = icmp ult i64 %lsr.iv.next, 761
+ br i1 %cmp, label %loop, label %exit
+
+ exit: ; preds = %loop
+ store <vscale x 4 x float> %acc00.t3, ptr %C, align 16
+ %6 = tail call i64 @llvm.vscale.i64()
+ %7 = shl nuw nsw i64 %6, 2
+ %C01 = getelementptr inbounds nuw float, ptr %C, i64 %7
+ store <vscale x 4 x float> %acc01.t3, ptr %C01, align 16
+ store <vscale x 4 x float> %acc10.t3, ptr %splitgep7, align 16
+ %8 = tail call i64 @llvm.vscale.i64()
+ %9 = shl nuw nsw i64 %8, 2
+ %C11 = getelementptr inbounds nuw float, ptr %splitgep7, i64 %9
+ store <vscale x 4 x float> %acc11.t3, ptr %C11, align 16
+ store <vscale x 4 x float> %acc20.t3, ptr %splitgep8, align 16
+ %10 = tail call i64 @llvm.vscale.i64()
+ %11 = shl nuw nsw i64 %10, 2
+ %C21 = getelementptr inbounds nuw float, ptr %splitgep8, i64 %11
+ store <vscale x 4 x float> %acc21.t3, ptr %C21, align 16
+ store <vscale x 4 x float> %acc30.t3, ptr %splitgep9, align 16
+ %12 = tail call i64 @llvm.vscale.i64()
+ %13 = shl nuw nsw i64 %12, 2
+ %C31 = getelementptr inbounds nuw float, ptr %splitgep9, i64 %13
+ store <vscale x 4 x float> %acc31.t3, ptr %C31, align 16
+ store <vscale x 4 x float> %acc40.t3, ptr %splitgep10, align 16
+ %14 = tail call i64 @llvm.vscale.i64()
+ %15 = shl nuw nsw i64 %14, 2
+ %C41 = getelementptr inbounds nuw float, ptr %splitgep10, i64 %15
+ store <vscale x 4 x float> %acc41.t3, ptr %C41, align 16
+ store <vscale x 4 x float> %acc50.t3, ptr %splitgep11, align 16
+ %16 = tail call i64 @llvm.vscale.i64()
+ %17 = shl nuw nsw i64 %16, 2
+ %C51 = getelementptr inbounds nuw float, ptr %splitgep11, i64 %17
+ store <vscale x 4 x float> %acc51.t3, ptr %C51, align 16
+ ret void
+ }
+
+ attributes #0 = { "target-features"="+sve" }
+...
+---
+name: f
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+noPhis: true
+isSSA: false
+noVRegs: false
+hasFakeUses: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+ - { id: 0, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 1, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 2, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 3, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 4, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 5, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 6, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 7, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 8, class: gpr64sp, preferred-register: '', flags: [ ] }
+ - { id: 9, class: gpr64sp, preferred-register: '', flags: [ ] }
+ - { id: 10, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 11, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 12, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 13, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 14, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 15, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 16, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 17, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 18, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 19, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 20, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 21, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 22, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 23, class: gpr64, preferred-register: '', flags: [ ] }
+ - { id: 24, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 25, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 26, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 27, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 28, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 29, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 30, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 31, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 32, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 33, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 34, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 35, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 36, class: gpr64sp, preferred-register: '', flags: [ ] }
+ - { id: 37, class: gpr64sp, preferred-register: '', flags: [ ] }
+ - { id: 38, class: gpr64, preferred-register: '', flags: [ ] }
+ - { id: 39, class: gpr64, preferred-register: '', flags: [ ] }
+ - { id: 40, class: gpr64common, preferred-register: '', flags: [ ] }
+ - { id: 41, class: gpr64, preferred-register: '', flags: [ ] }
+ - { id: 42, class: zpr, preferred-register: '', flags: [ ] }
+ - { id: 43, class: gpr32, preferred-register: '', flags: [ ] }
+ - { id: 44, class: gpr64, preferred-register: '', flags: [ ] }
+ - { id: 45, class: gpr64, preferred-register: '', flags: [ ] }
+ - { id: 46, class: gpr32, preferred-register: '', flags: [ ] }
+ - { id: 47, class: gpr64, preferred-register: '', flags: [ ] }
+ - { id: 48, class: gpr64, preferred-register: '', flags: [ ] }
+ - { id: 49, class: gpr32, preferred-register: '', flags: [ ] ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/176419
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