[llvm] 1056e32 - [LV] Precommit additional early-exit tests from #174864.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 16 07:18:28 PST 2026
Author: Florian Hahn
Date: 2026-01-16T15:18:20Z
New Revision: 1056e32785562c16d40a52dcd2a0d4a8a4d39bfb
URL: https://github.com/llvm/llvm-project/commit/1056e32785562c16d40a52dcd2a0d4a8a4d39bfb
DIFF: https://github.com/llvm/llvm-project/commit/1056e32785562c16d40a52dcd2a0d4a8a4d39bfb.diff
LOG: [LV] Precommit additional early-exit tests from #174864.
Pre-commit tests from https://github.com/llvm/llvm-project/pull/174864.
Added:
Modified:
llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopVectorize/early_exit_legality.ll b/llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
index 6954d04f53f04..81b10e02107ff 100644
--- a/llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
+++ b/llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
@@ -593,6 +593,45 @@ loop.end:
}
+; Two early exits on parallel branches (neither dominates the other).
+define i64 @uncountable_exits_on_parallel_branches() {
+; CHECK-LABEL: LV: Checking a loop in 'uncountable_exits_on_parallel_branches'
+; CHECK: LV: Not vectorizing: Loop has too many uncountable exits.
+entry:
+ %p1 = alloca [1024 x i8]
+ %p2 = alloca [1024 x i8]
+ call void @init_mem(ptr %p1, i64 1024)
+ call void @init_mem(ptr %p2, i64 1024)
+ br label %header
+
+header:
+ %index = phi i64 [ %index.next, %latch ], [ 3, %entry ]
+ %arrayidx = getelementptr inbounds i8, ptr %p1, i64 %index
+ %ld1 = load i8, ptr %arrayidx, align 1
+ %branch.cond = icmp sgt i8 %ld1, 0
+ br i1 %branch.cond, label %left, label %right
+
+left:
+ %arrayidx.left = getelementptr inbounds i8, ptr %p2, i64 %index
+ %ld.left = load i8, ptr %arrayidx.left, align 1
+ %cmp.left = icmp eq i8 %ld1, %ld.left
+ br i1 %cmp.left, label %loop.end, label %latch
+
+right:
+ %cmp.right = icmp ult i8 %ld1, 34
+ br i1 %cmp.right, label %loop.end, label %latch
+
+latch:
+ %index.next = add i64 %index, 1
+ %exitcond = icmp ne i64 %index.next, 67
+ br i1 %exitcond, label %header, label %loop.end
+
+loop.end:
+ %retval = phi i64 [ %index, %left ], [ 100, %right ], [ 43, %latch ]
+ ret i64 %retval
+}
+
+
declare i32 @foo(i32) readonly
declare <vscale x 4 x i32> @foo_vec(<vscale x 4 x i32>)
diff --git a/llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll b/llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
index 8bf41b5d873eb..75cdfe2b9cdd5 100644
--- a/llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
+++ b/llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -S < %s -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 | FileCheck %s
declare void @init_mem(ptr, i64)
@@ -14,22 +14,22 @@ define i64 @two_early_exits_same_exit() {
; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
; CHECK: [[LOOP_HEADER]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]
-; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IV]]
+; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[GEP_A]], align 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD1]], 42
; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
-; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[LD1]], [[LD2]]
; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDEX_NEXT]], 67
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[LOOP_HEADER]], label %[[EXIT]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[INDEX]], %[[LOOP_HEADER]] ], [ 100, %[[EARLY_EXIT_0]] ], [ 43, %[[LOOP_LATCH]] ]
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[IV]], %[[LOOP_HEADER]] ], [ 100, %[[EARLY_EXIT_0]] ], [ 43, %[[LOOP_LATCH]] ]
; CHECK-NEXT: ret i64 [[RETVAL]]
;
entry:
@@ -71,10 +71,10 @@ define i64 @two_early_exits_
diff erent_exits() {
; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
; CHECK: [[LOOP_HEADER]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]
-; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
-; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IV]]
+; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[GEP_A]], align 1
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD1]], [[LD2]]
; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT1:.*]], label %[[EARLY_EXIT_0:.*]]
@@ -82,11 +82,11 @@ define i64 @two_early_exits_
diff erent_exits() {
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i8 [[LD1]], 34
; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT2:.*]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDEX_NEXT]], 67
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[LOOP_HEADER]], label %[[EXIT:.*]]
; CHECK: [[EXIT1]]:
-; CHECK-NEXT: [[RET2:%.*]] = phi i64 [ [[INDEX]], %[[LOOP_HEADER]] ]
+; CHECK-NEXT: [[RET2:%.*]] = phi i64 [ [[IV]], %[[LOOP_HEADER]] ]
; CHECK-NEXT: ret i64 [[RET2]]
; CHECK: [[EXIT2]]:
; CHECK-NEXT: [[RET3:%.*]] = phi i64 [ 100, %[[EARLY_EXIT_0]] ]
@@ -131,6 +131,73 @@ exit:
ret i64 43
}
+define i64 @two_early_exits_
diff erent_exits_second_load_not_deref(ptr %B) {
+; CHECK-LABEL: define i64 @two_early_exits_
diff erent_exits_second_load_not_deref(
+; CHECK-SAME: ptr [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[A:%.*]] = alloca [1024 x i8], align 1
+; CHECK-NEXT: call void @init_mem(ptr [[A]], i64 1024)
+; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
+; CHECK: [[LOOP_HEADER]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IV]]
+; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[GEP_A]], align 1
+; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IV]]
+; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[GEP_B]], align 1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
+; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT1:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK: [[EARLY_EXIT_0]]:
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i8 [[LD_A]], 34
+; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT2:.*]], label %[[LOOP_LATCH]]
+; CHECK: [[LOOP_LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp ne i64 [[IV_NEXT]], 67
+; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_HEADER]], label %[[EXIT:.*]]
+; CHECK: [[EXIT1]]:
+; CHECK-NEXT: [[RET1:%.*]] = phi i64 [ [[IV]], %[[LOOP_HEADER]] ]
+; CHECK-NEXT: ret i64 [[RET1]]
+; CHECK: [[EXIT2]]:
+; CHECK-NEXT: [[RET2:%.*]] = phi i64 [ 100, %[[EARLY_EXIT_0]] ]
+; CHECK-NEXT: ret i64 [[RET2]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret i64 43
+;
+entry:
+ %A = alloca [1024 x i8]
+ call void @init_mem(ptr %A, i64 1024)
+ br label %loop.header
+
+loop.header:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ %gep.A = getelementptr inbounds i8, ptr %A, i64 %iv
+ %ld.A = load i8, ptr %gep.A, align 1
+ %gep.B = getelementptr inbounds i8, ptr %B, i64 %iv
+ %ld.B = load i8, ptr %gep.B, align 1
+ %cmp1 = icmp eq i8 %ld.A, %ld.B
+ br i1 %cmp1, label %exit1, label %early.exit.0
+
+early.exit.0:
+ %cmp2 = icmp ult i8 %ld.A, 34
+ br i1 %cmp2, label %exit2, label %loop.latch
+
+loop.latch:
+ %iv.next = add i64 %iv, 1
+ %ec = icmp ne i64 %iv.next, 67
+ br i1 %ec, label %loop.header, label %exit
+
+exit1:
+ %ret1 = phi i64 [ %iv, %loop.header ]
+ ret i64 %ret1
+
+exit2:
+ %ret2 = phi i64 [ 100, %early.exit.0 ]
+ ret i64 %ret2
+
+exit:
+ ret i64 43
+}
+
+
define i64 @three_early_exits_same_exit() {
; CHECK-LABEL: define i64 @three_early_exits_same_exit() {
; CHECK-NEXT: [[ENTRY:.*]]:
@@ -143,11 +210,11 @@ define i64 @three_early_exits_same_exit() {
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 3, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[TMP0]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], 42
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i8 [[LD_A]], 42
+; CHECK-NEXT: br i1 [[TMP8]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[TMP1]], align 1
+; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[GEP_B]], align 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT]], label %[[EARLY_EXIT_1:.*]]
; CHECK: [[EARLY_EXIT_1]]:
@@ -209,16 +276,16 @@ define i64 @four_early_exits_same_exit() {
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 3, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[TMP0]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], 42
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i8 [[LD_A]], 42
+; CHECK-NEXT: br i1 [[TMP11]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[TMP1]], align 1
+; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[GEP_B]], align 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT]], label %[[EARLY_EXIT_1:.*]]
; CHECK: [[EARLY_EXIT_1]]:
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[P3]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[LD_C:%.*]] = load i8, ptr [[TMP2]], align 1
+; CHECK-NEXT: [[GEP_C:%.*]] = getelementptr inbounds i8, ptr [[P3]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[LD_C:%.*]] = load i8, ptr [[GEP_C]], align 1
; CHECK-NEXT: [[CMP3:%.*]] = icmp eq i8 [[LD_B]], [[LD_C]]
; CHECK-NEXT: br i1 [[CMP3]], label %[[EXIT]], label %[[EARLY_EXIT_2:.*]]
; CHECK: [[EARLY_EXIT_2]]:
@@ -288,8 +355,8 @@ define i64 @two_early_exits_with_live_out_values() {
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[TMP0]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]
; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[TMP1]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
+; CHECK-NEXT: br i1 [[TMP7]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
; CHECK-NEXT: [[SUM:%.*]] = add i8 [[LD_A]], [[LD_B]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i8 [[SUM]], 34
@@ -348,10 +415,10 @@ define i64 @two_early_exits_negated_condition() {
; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
; CHECK: [[LOOP_HEADER]]:
-; CHECK-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 3, %[[ENTRY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[TMP0]], align 1
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 3, %[[ENTRY]] ]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IV]]
+; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[GEP_A]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[TMP1]], align 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 [[LD_A]], [[LD_B]]
; CHECK-NEXT: br i1 [[CMP1]], label %[[EARLY_EXIT_0:.*]], label %[[EXIT:.*]]
@@ -359,11 +426,11 @@ define i64 @two_early_exits_negated_condition() {
; CHECK-NEXT: [[CMP2:%.*]] = icmp uge i8 [[LD_A]], 34
; CHECK-NEXT: br i1 [[CMP2]], label %[[LOOP_LATCH]], label %[[EXIT]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[OFFSET_IDX]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp ne i64 [[IV_NEXT]], 128
; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_HEADER]], label %[[EXIT]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[OFFSET_IDX]], %[[LOOP_HEADER]] ], [ 100, %[[EARLY_EXIT_0]] ], [ 43, %[[LOOP_LATCH]] ]
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[IV]], %[[LOOP_HEADER]] ], [ 100, %[[EARLY_EXIT_0]] ], [ 43, %[[LOOP_LATCH]] ]
; CHECK-NEXT: ret i64 [[RETVAL]]
;
entry:
@@ -411,27 +478,27 @@ define i64 @three_early_exits_three_exit_blocks() {
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[TMP0]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[OFFSET_IDX]]
; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[TMP1]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT1:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
+; CHECK-NEXT: br i1 [[TMP8]], label %[[EXIT1:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
-; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i8 [[LD_A]], 34
-; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT2:.*]], label %[[EARLY_EXIT_1:.*]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp ult i8 [[LD_A]], 34
+; CHECK-NEXT: br i1 [[TMP10]], label %[[EXIT2:.*]], label %[[EARLY_EXIT_1:.*]]
; CHECK: [[EARLY_EXIT_1]]:
-; CHECK-NEXT: [[CMP3:%.*]] = icmp ugt i8 [[LD_B]], 100
-; CHECK-NEXT: br i1 [[CMP3]], label %[[EXIT3:.*]], label %[[LOOP_LATCH]]
+; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i8 [[LD_B]], 100
+; CHECK-NEXT: br i1 [[TMP11]], label %[[EXIT3:.*]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[OFFSET_IDX]], 1
; CHECK-NEXT: [[EC:%.*]] = icmp ne i64 [[IV_NEXT]], 99
; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_HEADER]], label %[[EXIT:.*]]
; CHECK: [[EXIT1]]:
-; CHECK-NEXT: [[RET3:%.*]] = phi i64 [ [[OFFSET_IDX]], %[[LOOP_HEADER]] ]
-; CHECK-NEXT: ret i64 [[RET3]]
+; CHECK-NEXT: [[RET4:%.*]] = phi i64 [ [[OFFSET_IDX]], %[[LOOP_HEADER]] ]
+; CHECK-NEXT: ret i64 [[RET4]]
; CHECK: [[EXIT2]]:
; CHECK-NEXT: [[RET2:%.*]] = phi i64 [ 100, %[[EARLY_EXIT_0]] ]
; CHECK-NEXT: ret i64 [[RET2]]
; CHECK: [[EXIT3]]:
-; CHECK-NEXT: [[RET4:%.*]] = phi i64 [ 200, %[[EARLY_EXIT_1]] ]
-; CHECK-NEXT: ret i64 [[RET4]]
+; CHECK-NEXT: [[RET3:%.*]] = phi i64 [ 200, %[[EARLY_EXIT_1]] ]
+; CHECK-NEXT: ret i64 [[RET3]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret i64 43
;
@@ -556,22 +623,22 @@ define i64 @three_early_exits_iv_and_load_live_out() {
; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
; CHECK: [[LOOP_HEADER]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[TMP0]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[TMP1]], align 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i8 [[LD_A]], 34
-; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP1]], [[CMP2]]
-; CHECK-NEXT: br i1 [[OR_COND]], label %[[EXIT:.*]], label %[[EARLY_EXIT_1:.*]]
+; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: br i1 [[TMP8]], label %[[EXIT:.*]], label %[[EARLY_EXIT_1:.*]]
; CHECK: [[EARLY_EXIT_1]]:
; CHECK-NEXT: [[CMP3:%.*]] = icmp ugt i8 [[LD_B]], 100
; CHECK-NEXT: br i1 [[CMP3]], label %[[EXIT]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
-; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP10]], label %[[EXIT]], label %[[LOOP_HEADER]]
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[INDEX]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 128
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[RETVAL_IV:%.*]] = phi i64 [ [[INDEX]], %[[LOOP_HEADER]] ], [ 128, %[[LOOP_LATCH]] ], [ [[INDEX]], %[[EARLY_EXIT_1]] ]
; CHECK-NEXT: [[RETVAL_LD:%.*]] = phi i8 [ [[LD_A]], %[[LOOP_HEADER]] ], [ 0, %[[LOOP_LATCH]] ], [ [[LD_B]], %[[EARLY_EXIT_1]] ]
@@ -703,21 +770,21 @@ define i64 @two_early_exits_iv_
diff _incoming() {
; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
; CHECK: [[LOOP_HEADER]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[TMP0]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[TMP1]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
+; CHECK-NEXT: br i1 [[TMP14]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
; CHECK-NEXT: [[IV_PLUS1:%.*]] = add i64 [[INDEX]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i8 [[LD_A]], 34
; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
-; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP8]], label %[[EXIT]], label %[[LOOP_HEADER]]
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[INDEX]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 128
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[INDEX]], %[[LOOP_HEADER]] ], [ [[IV_PLUS1]], %[[EARLY_EXIT_0]] ], [ 200, %[[LOOP_LATCH]] ]
; CHECK-NEXT: ret i64 [[RETVAL]]
@@ -762,13 +829,13 @@ define { i64, i64 } @three_early_exits_multiple_live_outs() {
; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
; CHECK: [[LOOP_HEADER]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[TMP0]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[TMP1]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
+; CHECK-NEXT: br i1 [[TMP10]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
; CHECK-NEXT: [[SUM:%.*]] = add i8 [[LD_A]], [[LD_B]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i8 [[SUM]], 34
@@ -778,9 +845,9 @@ define { i64, i64 } @three_early_exits_multiple_live_outs() {
; CHECK-NEXT: [[CMP3:%.*]] = icmp ugt i8 [[DIFF]], 100
; CHECK-NEXT: br i1 [[CMP3]], label %[[EXIT]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
-; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP11]], label %[[EXIT]], label %[[LOOP_HEADER]]
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[INDEX]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 128
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[RETVAL_IV:%.*]] = phi i64 [ [[INDEX]], %[[LOOP_HEADER]] ], [ [[INDEX]], %[[EARLY_EXIT_0]] ], [ [[INDEX]], %[[EARLY_EXIT_1]] ], [ 128, %[[LOOP_LATCH]] ]
; CHECK-NEXT: [[RETVAL_VAL:%.*]] = phi i8 [ [[LD_A]], %[[LOOP_HEADER]] ], [ [[SUM]], %[[EARLY_EXIT_0]] ], [ [[DIFF]], %[[EARLY_EXIT_1]] ], [ 0, %[[LOOP_LATCH]] ]
@@ -842,17 +909,17 @@ define i64 @two_early_exits_load_in_early_exit_block() {
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IV]]
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], 42
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i8 [[LD_A]], 42
+; CHECK-NEXT: br i1 [[TMP6]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
-; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
-; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
+; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
+; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[GEP_B]], align 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], 128
-; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP_HEADER]]
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 128
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[IV]], %[[LOOP_HEADER]] ], [ [[IV]], %[[EARLY_EXIT_0]] ], [ 128, %[[LOOP_LATCH]] ]
; CHECK-NEXT: ret i64 [[RETVAL]]
@@ -901,22 +968,22 @@ define i64 @three_early_exits_loads_in_
diff erent_blocks() {
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IV]]
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], 42
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i8 [[LD_A]], 42
+; CHECK-NEXT: br i1 [[TMP9]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
-; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
-; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1
+; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
+; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[GEP_B]], align 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[LD_A]], [[LD_B]]
; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT]], label %[[EARLY_EXIT_1:.*]]
; CHECK: [[EARLY_EXIT_1]]:
-; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, ptr [[P3]], i64 [[IV]]
-; CHECK-NEXT: [[LD_C:%.*]] = load i8, ptr [[ARRAYIDX3]], align 1
+; CHECK-NEXT: [[GEP_C:%.*]] = getelementptr inbounds i8, ptr [[P3]], i64 [[IV]]
+; CHECK-NEXT: [[LD_C:%.*]] = load i8, ptr [[GEP_C]], align 1
; CHECK-NEXT: [[CMP3:%.*]] = icmp eq i8 [[LD_B]], [[LD_C]]
; CHECK-NEXT: br i1 [[CMP3]], label %[[EXIT]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
-; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[IV_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP10]], label %[[EXIT]], label %[[LOOP_HEADER]]
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 128
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[IV]], %[[LOOP_HEADER]] ], [ [[IV]], %[[EARLY_EXIT_0]] ], [ [[IV]], %[[EARLY_EXIT_1]] ], [ 128, %[[LOOP_LATCH]] ]
; CHECK-NEXT: ret i64 [[RETVAL]]
@@ -975,27 +1042,27 @@ define { i64, i8 } @four_early_exits_with_conditional_loads() {
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[IV]]
; CHECK-NEXT: [[LD_A:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD_A]], 10
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
+; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i8 [[LD_A]], 10
+; CHECK-NEXT: br i1 [[TMP12]], label %[[EXIT:.*]], label %[[EARLY_EXIT_0:.*]]
; CHECK: [[EARLY_EXIT_0]]:
-; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
-; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1
+; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[IV]]
+; CHECK-NEXT: [[LD_B:%.*]] = load i8, ptr [[GEP_B]], align 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[LD_B]], 20
; CHECK-NEXT: br i1 [[CMP2]], label %[[EXIT]], label %[[EARLY_EXIT_1:.*]]
; CHECK: [[EARLY_EXIT_1]]:
-; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, ptr [[P3]], i64 [[IV]]
-; CHECK-NEXT: [[LD_C:%.*]] = load i8, ptr [[ARRAYIDX3]], align 1
+; CHECK-NEXT: [[GEP_C:%.*]] = getelementptr inbounds i8, ptr [[P3]], i64 [[IV]]
+; CHECK-NEXT: [[LD_C:%.*]] = load i8, ptr [[GEP_C]], align 1
; CHECK-NEXT: [[CMP3:%.*]] = icmp eq i8 [[LD_C]], 30
; CHECK-NEXT: br i1 [[CMP3]], label %[[EXIT]], label %[[EARLY_EXIT_2:.*]]
; CHECK: [[EARLY_EXIT_2]]:
-; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[P4]], i64 [[IV]]
-; CHECK-NEXT: [[LD_D:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; CHECK-NEXT: [[GEP_D:%.*]] = getelementptr inbounds i8, ptr [[P4]], i64 [[IV]]
+; CHECK-NEXT: [[LD_D:%.*]] = load i8, ptr [[GEP_D]], align 1
; CHECK-NEXT: [[CMP4:%.*]] = icmp eq i8 [[LD_D]], 40
; CHECK-NEXT: br i1 [[CMP4]], label %[[EXIT]], label %[[LOOP_LATCH]]
; CHECK: [[LOOP_LATCH]]:
; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
-; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[IV_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP13]], label %[[EXIT]], label %[[LOOP_HEADER]]
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 128
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[RETVAL_IV:%.*]] = phi i64 [ [[IV]], %[[LOOP_HEADER]] ], [ [[IV]], %[[EARLY_EXIT_0]] ], [ [[IV]], %[[EARLY_EXIT_1]] ], [ [[IV]], %[[EARLY_EXIT_2]] ], [ 128, %[[LOOP_LATCH]] ]
; CHECK-NEXT: [[RETVAL_VAL:%.*]] = phi i8 [ [[LD_A]], %[[LOOP_HEADER]] ], [ [[LD_B]], %[[EARLY_EXIT_0]] ], [ [[LD_C]], %[[EARLY_EXIT_1]] ], [ [[LD_D]], %[[EARLY_EXIT_2]] ], [ 0, %[[LOOP_LATCH]] ]
@@ -1172,8 +1239,3 @@ latch.exit:
early.exit:
ret i64 %iv
}
-;.
-; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-;.
diff --git a/llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll b/llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
index e2315c4fbab3b..f279a97a9a067 100644
--- a/llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
@@ -239,3 +239,36 @@ exit:
; uselistorder directives
uselistorder label %exit, { 1, 0 }
}
+
+define i64 @two_early_exits_same_exit_with_constant_live_outs() {
+; CHECK: LV: Not vectorizing: Loop has too many uncountable exits.
+;
+entry:
+ %A = alloca [1024 x i8]
+ %B = alloca [1024 x i8]
+ call void @init(ptr %A, i64 1024)
+ call void @init(ptr %B, i64 1024)
+ br label %loop.header
+
+loop.header:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ %gep.A = getelementptr inbounds i8, ptr %A, i64 %iv
+ %ld.A = load i8, ptr %gep.A, align 1
+ %cmp1 = icmp eq i8 %ld.A, 42
+ br i1 %cmp1, label %exit, label %early.exit.0
+
+early.exit.0:
+ %gep.B = getelementptr inbounds i8, ptr %B, i64 %iv
+ %ld.B = load i8, ptr %gep.B, align 1
+ %cmp2 = icmp eq i8 %ld.A, %ld.B
+ br i1 %cmp2, label %exit, label %loop.latch
+
+loop.latch:
+ %iv.next = add i64 %iv, 1
+ %ec = icmp ne i64 %iv.next, 67
+ br i1 %ec, label %loop.header, label %exit
+
+exit:
+ %retval = phi i64 [ %iv, %loop.header ], [ 100, %early.exit.0 ], [ 43, %loop.latch ]
+ ret i64 %retval
+}
diff --git a/llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll b/llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll
index 3cd60e8d7f592..80fbb6e7a49ca 100644
--- a/llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll
+++ b/llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll
@@ -488,6 +488,228 @@ loop.end:
}
+; Two uncountable early exits in a diamond pattern - they don't dominate each
+; other, so we can't determine a clear program order for checking them.
+define i64 @uncountable_exits_in_diamond_pattern() {
+; CHECK-LABEL: define i64 @uncountable_exits_in_diamond_pattern() {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1
+; CHECK-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1
+; CHECK-NEXT: call void @init_mem(ptr [[P1]], i64 1024)
+; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
+; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
+; CHECK: loop.header:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]
+; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[GEP1]], align 1
+; CHECK-NEXT: [[BRANCH_COND:%.*]] = icmp slt i8 [[LD1]], 0
+; CHECK-NEXT: br i1 [[BRANCH_COND]], label [[BLOCK_A:%.*]], label [[BLOCK_B:%.*]]
+; CHECK: block.a:
+; CHECK-NEXT: [[GEP2A:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
+; CHECK-NEXT: [[LD2A:%.*]] = load i8, ptr [[GEP2A]], align 1
+; CHECK-NEXT: [[CMP_A:%.*]] = icmp eq i8 [[LD1]], [[LD2A]]
+; CHECK-NEXT: br i1 [[CMP_A]], label [[LOOP_END:%.*]], label [[LOOP_LATCH]]
+; CHECK: block.b:
+; CHECK-NEXT: [[GEP2B:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
+; CHECK-NEXT: [[LD2B:%.*]] = load i8, ptr [[GEP2B]], align 1
+; CHECK-NEXT: [[CMP_B:%.*]] = icmp eq i8 [[LD1]], [[LD2B]]
+; CHECK-NEXT: br i1 [[CMP_B]], label [[LOOP_END]], label [[LOOP_LATCH]]
+; CHECK: loop.latch:
+; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDEX_NEXT]], 64
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP_HEADER]], label [[LOOP_END]]
+; CHECK: loop.end:
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ 1, [[BLOCK_A]] ], [ 2, [[BLOCK_B]] ], [ 0, [[LOOP_LATCH]] ]
+; CHECK-NEXT: ret i64 [[RETVAL]]
+;
+entry:
+ %p1 = alloca [1024 x i8], align 1
+ %p2 = alloca [1024 x i8], align 1
+ call void @init_mem(ptr %p1, i64 1024)
+ call void @init_mem(ptr %p2, i64 1024)
+ br label %loop.header
+
+loop.header:
+ %index = phi i64 [ %index.next, %loop.latch ], [ 0, %entry ]
+ %gep1 = getelementptr inbounds i8, ptr %p1, i64 %index
+ %ld1 = load i8, ptr %gep1, align 1
+ %branch.cond = icmp slt i8 %ld1, 0
+ br i1 %branch.cond, label %block.a, label %block.b
+
+block.a:
+ %gep2a = getelementptr inbounds i8, ptr %p2, i64 %index
+ %ld2a = load i8, ptr %gep2a, align 1
+ %cmp.a = icmp eq i8 %ld1, %ld2a
+ br i1 %cmp.a, label %loop.end, label %loop.latch
+
+block.b:
+ %gep2b = getelementptr inbounds i8, ptr %p2, i64 %index
+ %ld2b = load i8, ptr %gep2b, align 1
+ %cmp.b = icmp eq i8 %ld1, %ld2b
+ br i1 %cmp.b, label %loop.end, label %loop.latch
+
+loop.latch:
+ %index.next = add i64 %index, 1
+ %exitcond = icmp ne i64 %index.next, 64
+ br i1 %exitcond, label %loop.header, label %loop.end
+
+loop.end:
+ %retval = phi i64 [ 1, %block.a ], [ 2, %block.b ], [ 0, %loop.latch ]
+ ret i64 %retval
+}
+
+
+; Two early exits with udiv in a non-exiting middle block between them.
+; The udiv is only executed if the first early exit is not taken, so it
+; needs predication. This should not be vectorized.
+define i64 @multi_exit_udiv_in_nonexiting_block() {
+; CHECK-LABEL: define i64 @multi_exit_udiv_in_nonexiting_block() {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1
+; CHECK-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1
+; CHECK-NEXT: call void @init_mem(ptr [[P1]], i64 1024)
+; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
+; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
+; CHECK: loop.header:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]
+; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[GEP1]], align 1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD1]], 42
+; CHECK-NEXT: br i1 [[CMP1]], label [[LOOP_END:%.*]], label [[MIDDLE_BLOCK:%.*]]
+; CHECK: middle.block:
+; CHECK-NEXT: [[LD1_EXT:%.*]] = zext i8 [[LD1]] to i32
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 20000, [[LD1_EXT]]
+; CHECK-NEXT: br label [[EARLY_EXIT_2:%.*]]
+; CHECK: early.exit.2:
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
+; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[GEP2]], align 1
+; CHECK-NEXT: [[LD2_EXT:%.*]] = zext i8 [[LD2]] to i32
+; CHECK-NEXT: [[SUM:%.*]] = add i32 [[DIV]], [[LD2_EXT]]
+; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[SUM]], 100
+; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP_END]], label [[LOOP_LATCH]]
+; CHECK: loop.latch:
+; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDEX_NEXT]], 67
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP_HEADER]], label [[LOOP_END]]
+; CHECK: loop.end:
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[INDEX]], [[LOOP_HEADER]] ], [ [[INDEX]], [[EARLY_EXIT_2]] ], [ 67, [[LOOP_LATCH]] ]
+; CHECK-NEXT: ret i64 [[RETVAL]]
+;
+entry:
+ %p1 = alloca [1024 x i8]
+ %p2 = alloca [1024 x i8]
+ call void @init_mem(ptr %p1, i64 1024)
+ call void @init_mem(ptr %p2, i64 1024)
+ br label %loop.header
+
+loop.header:
+ %index = phi i64 [ %index.next, %loop.latch ], [ 0, %entry ]
+ %gep1 = getelementptr inbounds i8, ptr %p1, i64 %index
+ %ld1 = load i8, ptr %gep1, align 1
+ %cmp1 = icmp eq i8 %ld1, 42
+ br i1 %cmp1, label %loop.end, label %middle.block
+
+middle.block:
+ ; NOT an exiting block - unconditional branch to second early exit check
+ ; udiv here needs predication (only executed if cmp1 is false)
+ %ld1.ext = zext i8 %ld1 to i32
+ %div = udiv i32 20000, %ld1.ext
+ br label %early.exit.2
+
+early.exit.2:
+ ; Second early exit block
+ %gep2 = getelementptr inbounds i8, ptr %p2, i64 %index
+ %ld2 = load i8, ptr %gep2, align 1
+ %ld2.ext = zext i8 %ld2 to i32
+ %sum = add i32 %div, %ld2.ext
+ %cmp2 = icmp eq i32 %sum, 100
+ br i1 %cmp2, label %loop.end, label %loop.latch
+
+loop.latch:
+ %index.next = add i64 %index, 1
+ %exitcond = icmp ne i64 %index.next, 67
+ br i1 %exitcond, label %loop.header, label %loop.end
+
+loop.end:
+ %retval = phi i64 [ %index, %loop.header ], [ %index, %early.exit.2 ], [ 67, %loop.latch ]
+ ret i64 %retval
+}
+
+
+; Two early exits with store in a non-exiting middle block between them.
+; The store is only executed if the first early exit is not taken, so it
+; needs predication. This should not be vectorized.
+define i64 @multi_exit_store_in_nonexiting_block(ptr %dest) {
+; CHECK-LABEL: define i64 @multi_exit_store_in_nonexiting_block(
+; CHECK-SAME: ptr [[DEST:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[P1:%.*]] = alloca [1024 x i8], align 1
+; CHECK-NEXT: [[P2:%.*]] = alloca [1024 x i8], align 1
+; CHECK-NEXT: call void @init_mem(ptr [[P1]], i64 1024)
+; CHECK-NEXT: call void @init_mem(ptr [[P2]], i64 1024)
+; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
+; CHECK: loop.header:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, ptr [[P1]], i64 [[INDEX]]
+; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[GEP1]], align 1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LD1]], 42
+; CHECK-NEXT: br i1 [[CMP1]], label [[LOOP_END:%.*]], label [[MIDDLE_BLOCK:%.*]]
+; CHECK: middle.block:
+; CHECK-NEXT: [[GEP_DEST:%.*]] = getelementptr inbounds i8, ptr [[DEST]], i64 [[INDEX]]
+; CHECK-NEXT: store i8 [[LD1]], ptr [[GEP_DEST]], align 1
+; CHECK-NEXT: br label [[EARLY_EXIT_2:%.*]]
+; CHECK: early.exit.2:
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX]]
+; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[GEP2]], align 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[LD1]], [[LD2]]
+; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP_END]], label [[LOOP_LATCH]]
+; CHECK: loop.latch:
+; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDEX_NEXT]], 67
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP_HEADER]], label [[LOOP_END]]
+; CHECK: loop.end:
+; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[INDEX]], [[LOOP_HEADER]] ], [ [[INDEX]], [[EARLY_EXIT_2]] ], [ 67, [[LOOP_LATCH]] ]
+; CHECK-NEXT: ret i64 [[RETVAL]]
+;
+entry:
+ %p1 = alloca [1024 x i8]
+ %p2 = alloca [1024 x i8]
+ call void @init_mem(ptr %p1, i64 1024)
+ call void @init_mem(ptr %p2, i64 1024)
+ br label %loop.header
+
+loop.header:
+ %index = phi i64 [ %index.next, %loop.latch ], [ 0, %entry ]
+ %gep1 = getelementptr inbounds i8, ptr %p1, i64 %index
+ %ld1 = load i8, ptr %gep1, align 1
+ %cmp1 = icmp eq i8 %ld1, 42
+ br i1 %cmp1, label %loop.end, label %middle.block
+
+middle.block:
+ ; NOT an exiting block - unconditional branch to second early exit check
+ ; store here needs predication (only executed if cmp1 is false)
+ %gep.dest = getelementptr inbounds i8, ptr %dest, i64 %index
+ store i8 %ld1, ptr %gep.dest, align 1
+ br label %early.exit.2
+
+early.exit.2:
+ ; Second early exit block
+ %gep2 = getelementptr inbounds i8, ptr %p2, i64 %index
+ %ld2 = load i8, ptr %gep2, align 1
+ %cmp2 = icmp eq i8 %ld1, %ld2
+ br i1 %cmp2, label %loop.end, label %loop.latch
+
+loop.latch:
+ %index.next = add i64 %index, 1
+ %exitcond = icmp ne i64 %index.next, 67
+ br i1 %exitcond, label %loop.header, label %loop.end
+
+loop.end:
+ %retval = phi i64 [ %index, %loop.header ], [ %index, %early.exit.2 ], [ 67, %loop.latch ]
+ ret i64 %retval
+}
+
+
declare i32 @foo(i32) readonly
declare <vscale x 4 x i32> @foo_vec(<vscale x 4 x i32>)
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