[llvm] [AMDGPU] Handle AV classes when legalizing PHI nodes (PR #175995)

[Jay Foad via llvm-commits]

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/175995

None

>From e235594d36efcf349183b14f925e5a3f5ee66123 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 14 Jan 2026 17:13:27 +0000
Subject: [PATCH] [AMDGPU] Handle AV classes when legalizing PHI nodes

---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 90383f689b55c..5ab1eec138f49 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7303,11 +7303,15 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
         if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) {
           VRC = &AMDGPU::VReg_1RegClass;
         } else
-          VRC = RI.isAGPRClass(getOpRegClass(MI, 0))
+          VRC = RI.isVectorSuperClass(getOpRegClass(MI, 0))
+                    ? RI.getEquivalentAVClass(SRC)
+                : RI.isAGPRClass(getOpRegClass(MI, 0))
                     ? RI.getEquivalentAGPRClass(SRC)
                     : RI.getEquivalentVGPRClass(SRC);
       } else {
-        VRC = RI.isAGPRClass(getOpRegClass(MI, 0))
+        VRC = RI.isVectorSuperClass(getOpRegClass(MI, 0))
+                  ? RI.getEquivalentAVClass(VRC)
+              : RI.isAGPRClass(getOpRegClass(MI, 0))
                   ? RI.getEquivalentAGPRClass(VRC)
                   : RI.getEquivalentVGPRClass(VRC);
       }