[llvm] Handle ISD::ABDS in SelectionDAG::ComputeNumSignBits (PR #175321)

[Craig Topper via llvm-commits]

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@@ -338,6 +338,57 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_ADDC) {
   EXPECT_EQ(DAG->ComputeNumSignBits(Op), 2u);
 }
 
+TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_ABDS) {
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topperc wrote:

> Yes, if we give it values for known sign bits (sext/ashr) instead of known bits (known leading zeroes)

The known bits code uses ComputeNumSignBits on the inputs.  The inputs of ABSD are signed but the result is unsigned.

https://github.com/llvm/llvm-project/pull/175321