[llvm] [SDAG] (setcc (sub nsw a, b), zero, s??) -> (setcc a, b, s??) (PR #175459)
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https://github.com/DaKnig updated https://github.com/llvm/llvm-project/pull/175459
>From f422b5613f4cdf35af09c2f86a6d2f9f6c9ea511 Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: Sun, 11 Jan 2026 22:42:55 +0200
Subject: [PATCH 1/3] [SDAG] (setcc (add nsw), zero) -> (setcc)
---
.../test/CodeGen/AArch64/dag-combine-setcc.ll | 23 +++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll b/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
index a48a4e0e723eb..376ba30b2d4bd 100644
--- a/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
+++ b/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
@@ -331,13 +331,32 @@ entry:
ret i32 %or
}
+define i16 @combine_setcc_slt_add_nsw(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: combine_setcc_slt_add_nsw:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: adrp x8, .LCPI20_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0]
+; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: zip1 v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: addv h0, v0.8h
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
+ %add0 = sub nsw <16 x i8> %a, %b
+ %cmp1 = icmp slt <16 x i8> %add0, zeroinitializer
+ %cast = bitcast <16 x i1> %cmp1 to i16
+ ret i16 %cast
+}
+
; Reduced test from https://github.com/llvm/llvm-project/issues/58675
define [2 x i64] @PR58675(i128 %a.addr, i128 %b.addr) {
; CHECK-LABEL: PR58675:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: mov x9, xzr
-; CHECK-NEXT: .LBB20_1: // %do.body
+; CHECK-NEXT: .LBB21_1: // %do.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmp x0, x8
; CHECK-NEXT: sbcs xzr, x1, x9
@@ -347,7 +366,7 @@ define [2 x i64] @PR58675(i128 %a.addr, i128 %b.addr) {
; CHECK-NEXT: sbc x9, x3, x11
; CHECK-NEXT: cmp x3, x11
; CHECK-NEXT: ccmp x2, x10, #0, eq
-; CHECK-NEXT: b.ne .LBB20_1
+; CHECK-NEXT: b.ne .LBB21_1
; CHECK-NEXT: // %bb.2: // %do.end
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: mov x1, xzr
>From 74d0eb79d1ad5916361a4627fbc4b5f2796e72f7 Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: Sun, 11 Jan 2026 23:01:09 +0200
Subject: [PATCH 2/3] added the code, updated the test
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 6 +
llvm/test/CodeGen/AArch64/cond-br-tuning.ll | 2 +-
.../test/CodeGen/AArch64/dag-combine-setcc.ll | 3 +-
.../CodeGen/AArch64/selectcc-to-shiftand.ll | 16 +-
llvm/test/CodeGen/AArch64/sub1.ll | 21 ++-
.../CodeGen/RISCV/selectcc-to-shiftand.ll | 16 +-
llvm/test/CodeGen/Thumb2/mve-vabdus.ll | 160 ++++++++++--------
llvm/test/CodeGen/X86/jump_sign.ll | 2 +-
8 files changed, 122 insertions(+), 104 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index dfd074092fc78..6ae03b72ed87f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5668,6 +5668,12 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
}
+ // Fold (setcc (sub nsw a, b), zero, s??) -> (setcc a, b, s??)
+ if (isZeroOrZeroSplat(N1) && N0.getOpcode() == ISD::SUB &&
+ N0->getFlags().hasNoSignedWrap() && ISD::isSignedIntSetCC(Cond)) {
+ return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), Cond);
+ }
+
// Could not fold it.
return SDValue();
}
diff --git a/llvm/test/CodeGen/AArch64/cond-br-tuning.ll b/llvm/test/CodeGen/AArch64/cond-br-tuning.ll
index 87a315a49f3e0..3026cac837b90 100644
--- a/llvm/test/CodeGen/AArch64/cond-br-tuning.ll
+++ b/llvm/test/CodeGen/AArch64/cond-br-tuning.ll
@@ -161,7 +161,7 @@ define void @test_subs_tbnz(i32 %a, i32 %b, ptr %ptr) {
; CHECK-LABEL: test_subs_tbnz:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: subs w8, w0, w1
-; CHECK-NEXT: b.mi .LBB8_2
+; CHECK-NEXT: b.lt .LBB8_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: .LBB8_2: // %L2
diff --git a/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll b/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
index 376ba30b2d4bd..628da56109f35 100644
--- a/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
+++ b/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
@@ -334,10 +334,9 @@ entry:
define i16 @combine_setcc_slt_add_nsw(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: combine_setcc_slt_add_nsw:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: adrp x8, .LCPI20_0
+; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0]
-; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: zip1 v0.16b, v0.16b, v1.16b
diff --git a/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll b/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
index 96a7a9d039c21..22e7b1a971f8c 100644
--- a/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
+++ b/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
@@ -160,17 +160,11 @@ define i32 @not_neg_sel_same_variable(i32 %a) {
; ret = (x-y) > 0 ? x-y : 0
define i32 @PR31175(i32 %x, i32 %y) {
-; CHECK-SD-LABEL: PR31175:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub w8, w0, w1
-; CHECK-SD-NEXT: bic w0, w8, w8, asr #31
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: PR31175:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: subs w8, w0, w1
-; CHECK-GI-NEXT: csel w0, w8, wzr, gt
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: PR31175:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs w8, w0, w1
+; CHECK-NEXT: csel w0, w8, wzr, gt
+; CHECK-NEXT: ret
%sub = sub nsw i32 %x, %y
%cmp = icmp sgt i32 %sub, 0
%sel = select i1 %cmp, i32 %sub, i32 0
diff --git a/llvm/test/CodeGen/AArch64/sub1.ll b/llvm/test/CodeGen/AArch64/sub1.ll
index c359be57c27da..0ab05281c5418 100644
--- a/llvm/test/CodeGen/AArch64/sub1.ll
+++ b/llvm/test/CodeGen/AArch64/sub1.ll
@@ -119,13 +119,20 @@ define <4 x i32> @masked_sub_v4i32(<4 x i32> %x) {
}
define i32 @pr137254(i32 %0) {
-; CHECK-LABEL: pr137254:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
-; CHECK-NEXT: add w8, w0, w8
-; CHECK-NEXT: cmp w8, #0
-; CHECK-NEXT: cset w0, gt
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: pr137254:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, ne
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: pr137254:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-GI-NEXT: add w8, w0, w8
+; CHECK-GI-NEXT: cmp w8, #0
+; CHECK-GI-NEXT: cset w0, gt
+; CHECK-GI-NEXT: ret
%2 = sub nsw i32 %0, -2147483648
%3 = icmp sgt i32 %2, 0
%4 = select i1 %3, i32 1, i32 0
diff --git a/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll b/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
index fa1807cd7d911..d0013c8cc0370 100644
--- a/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
+++ b/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
@@ -184,18 +184,18 @@ define i32 @not_neg_sel_same_variable(i32 signext %a) {
define i32 @sub_clamp_zero(i32 signext %x, i32 signext %y) {
; RV32I-LABEL: sub_clamp_zero:
; RV32I: # %bb.0:
-; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: sgtz a1, a0
-; RV32I-NEXT: neg a1, a1
-; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: sub a2, a0, a1
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: neg a0, a0
+; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: sub_clamp_zero:
; RV64I: # %bb.0:
-; RV64I-NEXT: subw a0, a0, a1
-; RV64I-NEXT: sgtz a1, a0
-; RV64I-NEXT: neg a1, a1
-; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: subw a2, a0, a1
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: neg a0, a0
+; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ret
;
; RV32ZBB-LABEL: sub_clamp_zero:
diff --git a/llvm/test/CodeGen/Thumb2/mve-vabdus.ll b/llvm/test/CodeGen/Thumb2/mve-vabdus.ll
index 042a6ea18412a..e77a4181b94cf 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vabdus.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vabdus.ll
@@ -374,48 +374,48 @@ define void @vabd_loop_s32(ptr nocapture readonly %x, ptr nocapture readonly %y,
; CHECK-NEXT: .LBB17_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16
-; CHECK-NEXT: vldrw.u32 q3, [r1], #16
; CHECK-NEXT: vmov.f32 s8, s6
-; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov r7, s4
-; CHECK-NEXT: vmov.f32 s10, s7
+; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov r3, s8
-; CHECK-NEXT: vmov.f32 s8, s14
-; CHECK-NEXT: vmov.f32 s14, s15
-; CHECK-NEXT: vmov r4, s8
+; CHECK-NEXT: vldrw.u32 q2, [r1], #16
+; CHECK-NEXT: vmov.f32 s12, s10
+; CHECK-NEXT: vmov.f32 s10, s5
+; CHECK-NEXT: vmov.f32 s14, s11
+; CHECK-NEXT: vmov r4, s12
; CHECK-NEXT: asr.w r12, r3, #31
; CHECK-NEXT: subs.w r8, r3, r4
-; CHECK-NEXT: sbc.w r12, r12, r4, asr #31
-; CHECK-NEXT: vmov r4, s6
-; CHECK-NEXT: vmov.f32 s6, s13
-; CHECK-NEXT: vmov r6, s6
-; CHECK-NEXT: asrs r5, r4, #31
-; CHECK-NEXT: subs.w r9, r4, r6
+; CHECK-NEXT: sbcs.w r4, r12, r4, asr #31
; CHECK-NEXT: vmov r4, s10
-; CHECK-NEXT: sbc.w r5, r5, r6, asr #31
-; CHECK-NEXT: vmov r6, s12
-; CHECK-NEXT: asrs r5, r5, #31
+; CHECK-NEXT: csetm r12, lt
+; CHECK-NEXT: vmov.f32 s10, s9
+; CHECK-NEXT: vmov r6, s10
+; CHECK-NEXT: asrs r5, r4, #31
+; CHECK-NEXT: subs r4, r4, r6
+; CHECK-NEXT: sbcs.w r5, r5, r6, asr #31
+; CHECK-NEXT: vmov r6, s8
+; CHECK-NEXT: csetm r9, lt
+; CHECK-NEXT: vmov r5, s6
; CHECK-NEXT: subs r3, r7, r6
; CHECK-NEXT: asr.w r7, r7, #31
-; CHECK-NEXT: vmov q1[2], q1[0], r3, r8
+; CHECK-NEXT: vmov q2[2], q2[0], r3, r8
; CHECK-NEXT: vmov r3, s14
-; CHECK-NEXT: sbc.w r6, r7, r6, asr #31
-; CHECK-NEXT: asrs r6, r6, #31
-; CHECK-NEXT: subs r7, r4, r3
-; CHECK-NEXT: vmov q1[3], q1[1], r9, r7
-; CHECK-NEXT: mov.w r7, #0
-; CHECK-NEXT: bfi r7, r6, #0, #4
-; CHECK-NEXT: asr.w r6, r12, #31
-; CHECK-NEXT: bfi r7, r5, #4, #4
-; CHECK-NEXT: bfi r7, r6, #8, #4
-; CHECK-NEXT: asr.w r6, r4, #31
-; CHECK-NEXT: sbc.w r3, r6, r3, asr #31
-; CHECK-NEXT: asrs r3, r3, #31
-; CHECK-NEXT: bfi r7, r3, #12, #4
-; CHECK-NEXT: vmsr p0, r7
+; CHECK-NEXT: sbcs.w r6, r7, r6, asr #31
+; CHECK-NEXT: csetm r6, lt
+; CHECK-NEXT: subs r7, r5, r3
+; CHECK-NEXT: vmov q2[3], q2[1], r4, r7
+; CHECK-NEXT: mov.w r4, #0
+; CHECK-NEXT: bfi r4, r6, #0, #4
+; CHECK-NEXT: asr.w r7, r5, #31
+; CHECK-NEXT: sbcs.w r3, r7, r3, asr #31
+; CHECK-NEXT: bfi r4, r9, #4, #4
+; CHECK-NEXT: bfi r4, r12, #8, #4
+; CHECK-NEXT: csetm r3, lt
+; CHECK-NEXT: bfi r4, r3, #12, #4
+; CHECK-NEXT: vmsr p0, r4
; CHECK-NEXT: vpst
-; CHECK-NEXT: vsubt.i32 q1, q0, q1
-; CHECK-NEXT: vstrb.8 q1, [r2], #16
+; CHECK-NEXT: vsubt.i32 q2, q0, q2
+; CHECK-NEXT: vstrb.8 q2, [r2], #16
; CHECK-NEXT: le lr, .LBB17_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
@@ -530,62 +530,74 @@ for.cond.cleanup: ; preds = %vector.body
define void @vabd_loop_u32(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr noalias nocapture %z, i32 %n) {
; CHECK-LABEL: vabd_loop_u32:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: .vsave {d8, d9, d10, d11}
-; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: mov.w lr, #256
; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: .LBB20_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vldrw.u32 q4, [r1], #16
-; CHECK-NEXT: vldrw.u32 q5, [r0], #16
-; CHECK-NEXT: vmov.f32 s8, s18
-; CHECK-NEXT: vmov.f32 s10, s19
+; CHECK-NEXT: vldrw.u32 q6, [r0], #16
+; CHECK-NEXT: vldrw.u32 q5, [r1], #16
; CHECK-NEXT: vmov.f32 s12, s22
-; CHECK-NEXT: vand q2, q2, q0
+; CHECK-NEXT: vmov.f32 s16, s26
+; CHECK-NEXT: vmov r4, s24
; CHECK-NEXT: vmov.f32 s14, s23
-; CHECK-NEXT: vand q3, q3, q0
-; CHECK-NEXT: vmov r3, r12, d4
-; CHECK-NEXT: vmov r4, r5, d6
-; CHECK-NEXT: vmov.f32 s18, s17
+; CHECK-NEXT: vmov.f32 s18, s27
; CHECK-NEXT: vmov.f32 s22, s21
+; CHECK-NEXT: vmov.f32 s26, s25
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vmov r3, s16
+; CHECK-NEXT: sub.w r12, r3, r12
+; CHECK-NEXT: vmov r3, s20
+; CHECK-NEXT: subs r3, r4, r3
+; CHECK-NEXT: vmov r4, s18
+; CHECK-NEXT: vmov q2[2], q2[0], r3, r12
+; CHECK-NEXT: vmov r3, s14
+; CHECK-NEXT: vand q3, q3, q0
; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: sub.w r12, r4, r3
+; CHECK-NEXT: vmov r4, s22
+; CHECK-NEXT: vmov r3, s26
; CHECK-NEXT: vand q5, q5, q0
-; CHECK-NEXT: vmov r6, r7, d11
-; CHECK-NEXT: subs.w r8, r4, r3
-; CHECK-NEXT: sbc.w r12, r5, r12
-; CHECK-NEXT: vmov r5, r3, d9
-; CHECK-NEXT: subs.w r10, r6, r5
-; CHECK-NEXT: sbc.w r9, r7, r3
-; CHECK-NEXT: vmov r6, r7, d8
-; CHECK-NEXT: vmov r4, r3, d10
+; CHECK-NEXT: vand q6, q6, q0
+; CHECK-NEXT: subs r3, r3, r4
+; CHECK-NEXT: vmov r4, r5, d12
+; CHECK-NEXT: vmov q2[3], q2[1], r3, r12
+; CHECK-NEXT: vmov r3, r12, d10
+; CHECK-NEXT: subs r3, r4, r3
+; CHECK-NEXT: vmov r4, r6, d13
+; CHECK-NEXT: sbcs.w r3, r5, r12
+; CHECK-NEXT: csetm r5, lt
+; CHECK-NEXT: movs r3, #0
+; CHECK-NEXT: bfi r3, r5, #0, #4
+; CHECK-NEXT: vmov r5, r12, d11
+; CHECK-NEXT: subs r4, r4, r5
+; CHECK-NEXT: sbcs.w r6, r6, r12
+; CHECK-NEXT: vmov r4, r5, d8
+; CHECK-NEXT: csetm r6, lt
+; CHECK-NEXT: bfi r3, r6, #4, #4
+; CHECK-NEXT: vmov r6, r12, d6
; CHECK-NEXT: subs r4, r4, r6
-; CHECK-NEXT: sbcs r3, r7
-; CHECK-NEXT: vmov q4[2], q4[0], r4, r8
-; CHECK-NEXT: vmov r4, r6, d5
-; CHECK-NEXT: vmov r7, r5, d7
-; CHECK-NEXT: asrs r3, r3, #31
-; CHECK-NEXT: subs r4, r7, r4
-; CHECK-NEXT: vmov q4[3], q4[1], r10, r4
-; CHECK-NEXT: mov.w r4, #0
-; CHECK-NEXT: bfi r4, r3, #0, #4
-; CHECK-NEXT: asr.w r3, r9, #31
-; CHECK-NEXT: bfi r4, r3, #4, #4
-; CHECK-NEXT: asr.w r3, r12, #31
-; CHECK-NEXT: bfi r4, r3, #8, #4
-; CHECK-NEXT: sbc.w r3, r5, r6
-; CHECK-NEXT: asrs r3, r3, #31
-; CHECK-NEXT: bfi r4, r3, #12, #4
-; CHECK-NEXT: vmsr p0, r4
+; CHECK-NEXT: sbcs.w r6, r5, r12
+; CHECK-NEXT: vmov r4, r5, d9
+; CHECK-NEXT: csetm r6, lt
+; CHECK-NEXT: bfi r3, r6, #8, #4
+; CHECK-NEXT: vmov r6, r12, d7
+; CHECK-NEXT: subs r4, r4, r6
+; CHECK-NEXT: sbcs.w r6, r5, r12
+; CHECK-NEXT: csetm r6, lt
+; CHECK-NEXT: bfi r3, r6, #12, #4
+; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpst
-; CHECK-NEXT: vsubt.i32 q4, q1, q4
-; CHECK-NEXT: vstrb.8 q4, [r2], #16
+; CHECK-NEXT: vsubt.i32 q2, q1, q2
+; CHECK-NEXT: vstrb.8 q2, [r2], #16
; CHECK-NEXT: le lr, .LBB20_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
-; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: pop {r4, r5, r6, pc}
entry:
br label %vector.body
diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll
index d28a93ec3d77c..dbfd08cf3a772 100644
--- a/llvm/test/CodeGen/X86/jump_sign.ll
+++ b/llvm/test/CodeGen/X86/jump_sign.ll
@@ -203,7 +203,7 @@ define i32 @func_n(i32 %x, i32 %y) nounwind {
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: cmpl %ecx, %eax
-; CHECK-NEXT: cmovsl %ecx, %eax
+; CHECK-NEXT: cmovll %ecx, %eax
; CHECK-NEXT: retl
%sub = sub nsw i32 %x, %y
%cmp = icmp slt i32 %sub, 0
>From 01fb89461c912ff572a07dbf3e22dd131f318c5f Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: Sun, 11 Jan 2026 23:01:09 +0200
Subject: [PATCH 3/3] added the code, updated the test
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ee28260a74127..765e94863a6c3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13877,7 +13877,7 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
SDLoc DL(N);
- if (SDValue Combined = SimplifySetCC(VT, N0, N1, Cond, DL, !PreferSetCC)) {
+ if (SDValue Combined = Simplifysetcc(VT, N0, N1, Cond, DL, !PreferSetCC)) {
// If we prefer to have a setcc, and we don't, we'll try our best to
// recreate one using rebuildSetCC.
if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) {
- Previous message: [llvm] [SDAG] (setcc (sub nsw a, b), zero, s??) -> (setcc a, b, s??) (PR #175459)
- Next message: [llvm] [SDAG] (setcc (sub nsw a, b), zero, s??) -> (setcc a, b, s??) (PR #175459)
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