[llvm] [AMDGPU] Add regbankselect rules for G_ICMP/G_FCMP (PR #172048)

[Petar Avramovic via llvm-commits]

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@@ -560,14 +560,35 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Any({{UniS1, _}, {{Sgpr32Trunc}, {None}, UniCstExt}});
   addRulesForGOpcs({G_FREEZE}).Any({{DivS1}, {{Vcc}, {Vcc}}});
 
+  Predicate isSignedICmp([](const MachineInstr &MI) -> bool {
+    auto Pred =
+        static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
+    return CmpInst::isSigned(Pred);
+  });
+
+  Predicate isEqualityICmp([](const MachineInstr &MI) -> bool {
+    auto Pred =
+        static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
+    return CmpInst::isEquality(Pred);
+  });
+
   addRulesForGOpcs({G_ICMP})
+      .Any({{{UniS1, _, S16}, isSignedICmp},
+            {{Sgpr32Trunc}, {None, Sgpr32SExt, Sgpr32SExt}}})
+      .Any({{{UniS1, _, S16}, !isSignedICmp},
+            {{Sgpr32Trunc}, {None, Sgpr32ZExt, Sgpr32ZExt}}})
+      .Any({{DivS1, _, S16}, {{Vcc}, {None, Vgpr16, Vgpr16}}})
       .Any({{UniS1, _, S32}, {{Sgpr32Trunc}, {None, Sgpr32, Sgpr32}}})
       .Any({{DivS1, _, S32}, {{Vcc}, {None, Vgpr32, Vgpr32}}})
-      .Any({{DivS1, _, S64}, {{Vcc}, {None, Vgpr64, Vgpr64}}});
-
-  addRulesForGOpcs({G_FCMP})
-      .Any({{UniS1, _, S32}, {{UniInVcc}, {None, Vgpr32, Vgpr32}}})
-      .Any({{DivS1, _, S32}, {{Vcc}, {None, Vgpr32, Vgpr32}}});
+      .Any({{{UniS1, _, S64}, isEqualityICmp},
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petar-avramovic wrote:

> Does mapping to Sgpr32Trunc make sense, given that the source operands are mapped to Sgpr64?

Yes, result of comparing Sgpr64 is SgprS1 (the SCC), but result needs to be in Sgpr32

> I wonder if the source operands can be lowered into 32-bit values.

It can but is a bit complicated, for example check LegalizerHelper::narrowScalar. If we want to implement it like that instead of UniInVcc I would leave it for later.



https://github.com/llvm/llvm-project/pull/172048