[llvm] [SDAG] (setcc (sub nsw a, b), zero, s??) -> (setcc a, b, s??) (PR #175459)

[via llvm-commits]

https://github.com/DaKnig updated https://github.com/llvm/llvm-project/pull/175459

>From f422b5613f4cdf35af09c2f86a6d2f9f6c9ea511 Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: Sun, 11 Jan 2026 22:42:55 +0200
Subject: [PATCH 1/2] [SDAG] (setcc (add nsw), zero) -> (setcc)

---
 .../test/CodeGen/AArch64/dag-combine-setcc.ll | 23 +++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll b/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
index a48a4e0e723eb..376ba30b2d4bd 100644
--- a/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
+++ b/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
@@ -331,13 +331,32 @@ entry:
   ret i32 %or
 }
 
+define i16 @combine_setcc_slt_add_nsw(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: combine_setcc_slt_add_nsw:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    adrp x8, .LCPI20_0
+; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_0]
+; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    zip1 v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    addv h0, v0.8h
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    ret
+  %add0 = sub nsw <16 x i8> %a, %b
+  %cmp1 = icmp slt <16 x i8> %add0, zeroinitializer
+  %cast = bitcast <16 x i1> %cmp1 to i16
+  ret i16 %cast
+}
+
 ; Reduced test from https://github.com/llvm/llvm-project/issues/58675
 define [2 x i64] @PR58675(i128 %a.addr, i128 %b.addr) {
 ; CHECK-LABEL: PR58675:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    mov x8, xzr
 ; CHECK-NEXT:    mov x9, xzr
-; CHECK-NEXT:  .LBB20_1: // %do.body
+; CHECK-NEXT:  .LBB21_1: // %do.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    cmp x0, x8
 ; CHECK-NEXT:    sbcs xzr, x1, x9
@@ -347,7 +366,7 @@ define [2 x i64] @PR58675(i128 %a.addr, i128 %b.addr) {
 ; CHECK-NEXT:    sbc x9, x3, x11
 ; CHECK-NEXT:    cmp x3, x11
 ; CHECK-NEXT:    ccmp x2, x10, #0, eq
-; CHECK-NEXT:    b.ne .LBB20_1
+; CHECK-NEXT:    b.ne .LBB21_1
 ; CHECK-NEXT:  // %bb.2: // %do.end
 ; CHECK-NEXT:    mov x0, xzr
 ; CHECK-NEXT:    mov x1, xzr

>From b4f1c6ff36e2dfaf5be42fbef63d5013fbb7e904 Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: Sun, 11 Jan 2026 23:01:09 +0200
Subject: [PATCH 2/2] added the code, updated the test

---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 ++++++
 llvm/test/CodeGen/AArch64/dag-combine-setcc.ll   | 3 +--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index dfd074092fc78..6ae03b72ed87f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5668,6 +5668,12 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
     return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
   }
 
+  // Fold (setcc (sub nsw a, b), zero, s??) -> (setcc a, b, s??)
+  if (isZeroOrZeroSplat(N1) && N0.getOpcode() == ISD::SUB &&
+      N0->getFlags().hasNoSignedWrap() && ISD::isSignedIntSetCC(Cond)) {
+    return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), Cond);
+  }
+
   // Could not fold it.
   return SDValue();
 }
diff --git a/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll b/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
index 376ba30b2d4bd..628da56109f35 100644
--- a/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
+++ b/llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
@@ -334,10 +334,9 @@ entry:
 define i16 @combine_setcc_slt_add_nsw(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: combine_setcc_slt_add_nsw:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    adrp x8, .LCPI20_0
+; CHECK-NEXT:    cmgt v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_0]
-; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-NEXT:    zip1 v0.16b, v0.16b, v1.16b