[clang] [llvm] [RISCV] Add processor definitions for XuanTie C910V2 and C920V2 (PR #174056)

[Pengcheng Wang via llvm-commits]

================
@@ -881,3 +881,106 @@ def ANDES_AX45MPV : RISCVProcessorModel<"andes-ax45mpv",
                                          FeatureStdExtV,
                                          FeatureVendorXAndesPerf],
                                         Andes45TuneFeatures>;
+
+def XUANTIE_C910V2 : RISCVProcessorModel<"xt-c910v2",
+                                         GenericOOOModel,
+                                         [Feature64Bit,
+                                          FeatureStdExtI,
+                                          FeatureStdExtM,
+                                          FeatureStdExtA,
+                                          FeatureStdExtF,
+                                          FeatureStdExtD,
+                                          FeatureStdExtC,
+                                          FeatureStdExtZicbom,
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wangpc-pp wrote:

Yeah, I meant `!listconcat(!listremove(base_supported_profile, [unsupported_extensions, ...]), [extra_features...])`. And are you sure that XuanTie cores don't support Ziccif/`Zic64b`? That is kind of surprising.

https://github.com/llvm/llvm-project/pull/174056