[llvm] [RISCV] Add a custom pre-ra scheduler (PR #172613)

[Pengcheng Wang via llvm-commits]

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@@ -0,0 +1,122 @@
+//===- RISCVMachineScheduler.cpp - MI Scheduler for RISC-V ----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVMachineScheduler.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-prera-sched-strategy"
+
+bool RISCVPreRAMachineSchedStrategy::tryCandidate(SchedCandidate &Cand,
+                                                  SchedCandidate &TryCand,
+                                                  SchedBoundary *Zone) const {
+  //-------------------------------------------------------------------------//
+  // Below is copied from `GenericScheduler::tryCandidate`.
+  // FIXME: Is there a way to not replicate this?
----------------
wangpc-pp wrote:

There is no difference compared to `GenericScheduler::tryCandidate`. I added it here to make https://github.com/llvm/llvm-project/pull/95924 easy to review (so people don't need to care about the common implementation).

https://github.com/llvm/llvm-project/pull/172613