[llvm] [TableGen] Fix what looks like a mistake in RegClassByHwMode.td test. NFC (PR #174252)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 3 15:29:57 PST 2026
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/174252
>From 16d6d9b2fbba2eeab4fe3ea377abd2488c7207cd Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 2 Jan 2026 14:58:37 -0800
Subject: [PATCH 1/2] [TableGen] Fix what looks like a mistake in
RegClassByHwMode.td test. NFC
The $src operand for the MY_STORE instruction had a different
operand type in the input and output patterns which looks unusual.
Fixing this makes more isel patterns appear in the generated tables.
---
llvm/test/TableGen/RegClassByHwMode.td | 132 ++++++++++++++++++-------
1 file changed, 98 insertions(+), 34 deletions(-)
diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td
index 0be22be560bea..9adcf78253418 100644
--- a/llvm/test/TableGen/RegClassByHwMode.td
+++ b/llvm/test/TableGen/RegClassByHwMode.td
@@ -189,14 +189,36 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-SDAG: MatcherTable
// ISEL-SDAG: OPC_SwitchOpcode /*2 cases */, {{[0-9]+}}, TARGET_VAL(ISD::STORE),
-// ISEL-SDAG: OPC_RecordMemRef,
-// ISEL-SDAG: OPC_RecordNode, // #0 = 'st' chained node
-// ISEL-SDAG: OPC_RecordChild1, // #1 = $val
+// ISEL-SDAG-NEXT: OPC_RecordMemRef,
+// ISEL-SDAG-NEXT: OPC_RecordNode, // #0 = 'st' chained node
+// ISEL-SDAG-NEXT: OPC_RecordChild1, // #1 = $val
// ISEL-SDAG-NEXT: OPC_RecordChild2, // #2 = $src
+// ISEL-SDAG-NEXT: OPC_Scope, {{[0-9]+}}, /*->{{[0-9]+}}*/ // 2 children in Scope
+// ISEL-SDAG-NEXT: OPC_CheckChild2TypeI32,
+// ISEL-SDAG-NEXT: OPC_CheckPredicate0, // Predicate_unindexedstore
+// ISEL-SDAG-NEXT: OPC_CheckPredicate1, // Predicate_store
+// ISEL-SDAG-NEXT: OPC_Scope, {{[0-9]+}}, /*->{{[0-9]+}}*/ // 3 children in Scope
+// ISEL-SDAG-NEXT: OPC_CheckPatternPredicate0, // (Subtarget->hasAlignedRegisters())
+// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,
+// ISEL-SDAG-NEXT: OPC_MorphNodeTo0, TARGET_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs,
+
+// ISEL-SDAG: /*Scope*/
+// ISEL-SDAG: OPC_CheckPatternPredicate1, // (Subtarget->hasUnalignedRegisters())
+// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,
+// ISEL-SDAG-NEXT: OPC_MorphNodeTo0, TARGET_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs,
+
+// ISEL-SDAG: /*Scope*/
+// ISEL-SDAG: OPC_CheckPatternPredicate2, // !((Subtarget->hasAlignedRegisters())) && !((Subtarget->hasUnalignedRegisters())) && !((Subtarget->isPtr64()))
+// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,
+// ISEL-SDAG-NEXT: OPC_MorphNodeTo0, TARGET_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs,
+
+// ISEL-SDAG: /*Scope*/
// ISEL-SDAG-NEXT: OPC_CheckChild2TypeI64,
-// ISEL-SDAG-NEXT: OPC_CheckPredicate2, // Predicate_unindexedstore
-// ISEL-SDAG-NEXT: OPC_CheckPredicate3, // Predicate_store
-// ISEL-SDAG: OPC_MorphNodeTo0, TARGET_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs,
+// ISEL-SDAG-NEXT: OPC_CheckPredicate0, // Predicate_unindexedstore
+// ISEL-SDAG-NEXT: OPC_CheckPredicate1, // Predicate_store
+// ISEL-SDAG-NEXT: OPC_CheckPatternPredicate3, // (Subtarget->isPtr64())
+// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,
+// ISEL-SDAG-NEXT: OPC_MorphNodeTo0, TARGET_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs,
// ISEL-SDAG: /*SwitchOpcode*/ {{[0-9]+}}, TARGET_VAL(ISD::LOAD),
// ISEL-SDAG-NEXT: OPC_RecordMemRef,
@@ -205,28 +227,28 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-SDAG-NEXT: OPC_CheckTypeI64,
// ISEL-SDAG-NEXT: OPC_Scope, {{[0-9]+}}, /*->{{[0-9]+}}*/ // 2 children in Scope
// ISEL-SDAG-NEXT: OPC_CheckChild1TypeI32,
-// ISEL-SDAG-NEXT: OPC_CheckPredicate0, // Predicate_unindexedload
-// ISEL-SDAG-NEXT: OPC_CheckPredicate1, // Predicate_load
+// ISEL-SDAG-NEXT: OPC_CheckPredicate2, // Predicate_unindexedload
+// ISEL-SDAG-NEXT: OPC_CheckPredicate3, // Predicate_load
// ISEL-SDAG-NEXT: OPC_Scope, {{[0-9]+}}, /*->{{[0-9]+}}*/ // 3 children in Scope
-// ISEL-SDAG-NEXT: OPC_CheckPatternPredicate1, // (Subtarget->hasAlignedRegisters())
+// ISEL-SDAG-NEXT: OPC_CheckPatternPredicate0, // (Subtarget->hasAlignedRegisters())
// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,
// ISEL-SDAG-NEXT: OPC_MorphNodeTo1, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs,
// ISEL-SDAG: /*Scope*/
-// ISEL-SDAG: OPC_CheckPatternPredicate2, // (Subtarget->hasUnalignedRegisters())
+// ISEL-SDAG: OPC_CheckPatternPredicate1, // (Subtarget->hasUnalignedRegisters())
// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,
// ISEL-SDAG-NEXT: OPC_MorphNodeTo1, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs,
// ISEL-SDAG: /*Scope*/
-// ISEL-SDAG: OPC_CheckPatternPredicate3, // !((Subtarget->hasAlignedRegisters())) && !((Subtarget->hasUnalignedRegisters())) && !((Subtarget->isPtr64()))
+// ISEL-SDAG: OPC_CheckPatternPredicate2, // !((Subtarget->hasAlignedRegisters())) && !((Subtarget->hasUnalignedRegisters())) && !((Subtarget->isPtr64()))
// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,
// ISEL-SDAG-NEXT: OPC_MorphNodeTo1, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs,
// ISEL-SDAG: /*Scope*/
// ISEL-SDAG-NEXT: OPC_CheckChild1TypeI64,
-// ISEL-SDAG-NEXT: OPC_CheckPredicate0, // Predicate_unindexedload
-// ISEL-SDAG-NEXT: OPC_CheckPredicate1, // Predicate_load
-// ISEL-SDAG-NEXT: OPC_CheckPatternPredicate0, // (Subtarget->isPtr64())
+// ISEL-SDAG-NEXT: OPC_CheckPredicate2, // Predicate_unindexedload
+// ISEL-SDAG-NEXT: OPC_CheckPredicate3, // Predicate_load
+// ISEL-SDAG-NEXT: OPC_CheckPatternPredicate3, // (Subtarget->isPtr64())
// ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0,
// ISEL-SDAG-NEXT: OPC_MorphNodeTo1, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs,
@@ -245,36 +267,36 @@ include "Common/RegClassByHwModeCommon.td"
// FIXME: This should be a direct check for regbank, not have an incorrect class
// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
-// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(85), // Rule ID 1 //
-// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(85), // Rule ID 4 //
+// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
-// ISEL-GISEL-NEXT: // GIR_Coverage, 1,
+// ISEL-GISEL-NEXT: // GIR_Coverage, 4,
// ISEL-GISEL-NEXT: GIR_Done,
// ISEL-GISEL-NEXT: // Label 5: @85
-// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(100), // Rule ID 2 //
-// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(100), // Rule ID 5 //
+// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
-// ISEL-GISEL-NEXT: // GIR_Coverage, 2,
+// ISEL-GISEL-NEXT: // GIR_Coverage, 5,
// ISEL-GISEL-NEXT: GIR_Done,
// ISEL-GISEL-NEXT: // Label 6: @100
// ISEL-GISEL-NEXT: GIM_Reject,
// ISEL-GISEL-NEXT: // Label 4: @101
-// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(124), // Rule ID 3 //
-// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(124), // Rule ID 6 //
+// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
// ISEL-GISEL-NEXT: // MIs[0] src
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i64] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i64] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
-// ISEL-GISEL-NEXT: // GIR_Coverage, 3,
+// ISEL-GISEL-NEXT: // GIR_Coverage, 6,
// ISEL-GISEL-NEXT: GIR_Done,
// ISEL-GISEL-NEXT: // Label 7: @124
-// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(147), // Rule ID 4 //
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(147), // Rule ID 7 //
// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
// ISEL-GISEL-NEXT: // MIs[0] src
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
@@ -282,25 +304,67 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
-// ISEL-GISEL-NEXT: // GIR_Coverage, 4,
+// ISEL-GISEL-NEXT: // GIR_Coverage, 7,
// ISEL-GISEL-NEXT: GIR_Done,
// ISEL-GISEL-NEXT: // Label 8: @147
// ISEL-GISEL-NEXT: GIM_Reject,
// ISEL-GISEL-NEXT: // Label 3: @148
// ISEL-GISEL-NEXT: GIM_Reject,
// ISEL-GISEL-NEXT: // Label 1: @149
-// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(186), // Rule ID 0 //
-// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(259),
// ISEL-GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
// ISEL-GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// ISEL-GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID),
-// ISEL-GISEL-NEXT: // MIs[0] src
-// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
-// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i64] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, XRegs_EvenIfRequired:{ *:[i64] }:$src)
-// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
-// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4(212),
+// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 11*/ GIMT_Encode4(196), // Rule ID 0 //
+// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
+// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
+// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
+// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
+// ISEL-GISEL-NEXT: // GIR_Coverage, 0,
+// ISEL-GISEL-NEXT: GIR_Done,
+// ISEL-GISEL-NEXT: // Label 11: @196
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 12*/ GIMT_Encode4(211), // Rule ID 1 //
+// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
+// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
+// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
+// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
+// ISEL-GISEL-NEXT: // GIR_Coverage, 1,
+// ISEL-GISEL-NEXT: GIR_Done,
+// ISEL-GISEL-NEXT: // Label 12: @211
+// ISEL-GISEL-NEXT: GIM_Reject,
+// ISEL-GISEL-NEXT: // Label 10: @212
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(235), // Rule ID 2 //
+// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
+// ISEL-GISEL-NEXT: // MIs[0] src
+// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i64] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$src)
+// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
+// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
+// ISEL-GISEL-NEXT: // GIR_Coverage, 2,
+// ISEL-GISEL-NEXT: GIR_Done,
+// ISEL-GISEL-NEXT: // Label 13: @235
+// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 14*/ GIMT_Encode4(258), // Rule ID 3 //
+// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
+// ISEL-GISEL-NEXT: // MIs[0] src
+// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
+// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE)
+// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
+// ISEL-GISEL-NEXT: // GIR_Coverage, 3,
+// ISEL-GISEL-NEXT: GIR_Done,
+// ISEL-GISEL-NEXT: // Label 14: @258
+// ISEL-GISEL-NEXT: GIM_Reject,
+// ISEL-GISEL-NEXT: // Label 9: @259
+// ISEL-GISEL-NEXT: GIM_Reject,
+// ISEL-GISEL-NEXT: // Label 2: @260
+// ISEL-GISEL-NEXT: GIM_Reject,
+// ISEL-GISEL-NEXT: }; // Size: 261 bytes
def HasAlignedRegisters : Predicate<"Subtarget->hasAlignedRegisters()">;
def HasUnalignedRegisters : Predicate<"Subtarget->hasUnalignedRegisters()">;
@@ -418,7 +482,7 @@ def MY_LOAD_ALIAS2 : InstAlias<"also_my_load_2 $dst, $src",
// Direct RegClassByHwMode usage
def : Pat<
(store XRegs_EvenIfRequired:$val, MyPtrRC:$src),
- (MY_STORE $val, XRegs_EvenIfRequired:$src)
+ (MY_STORE $val, $src)
>;
// Wrapped in RegisterOperand
>From 2054e4865f0a6a72bd49a6c6a7df97241916b170 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 3 Jan 2026 15:29:40 -0800
Subject: [PATCH 2/2] fixup! address review comment
---
llvm/test/TableGen/RegClassByHwMode.td | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td
index 9adcf78253418..193a4c616bb89 100644
--- a/llvm/test/TableGen/RegClassByHwMode.td
+++ b/llvm/test/TableGen/RegClassByHwMode.td
@@ -321,7 +321,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 11*/ GIMT_Encode4(196), // Rule ID 0 //
// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
-// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
+// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// ISEL-GISEL-NEXT: // GIR_Coverage, 0,
@@ -329,7 +329,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: // Label 11: @196
// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 12*/ GIMT_Encode4(211), // Rule ID 1 //
// ISEL-GISEL-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
-// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
+// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// ISEL-GISEL-NEXT: // GIR_Coverage, 1,
@@ -342,7 +342,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: // MIs[0] src
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
-// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i64] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$src)
+// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i64] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i64] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// ISEL-GISEL-NEXT: // GIR_Coverage, 2,
@@ -353,7 +353,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: // MIs[0] src
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
-// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE ?:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
+// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE)
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// ISEL-GISEL-NEXT: // GIR_Coverage, 3,
@@ -482,7 +482,7 @@ def MY_LOAD_ALIAS2 : InstAlias<"also_my_load_2 $dst, $src",
// Direct RegClassByHwMode usage
def : Pat<
(store XRegs_EvenIfRequired:$val, MyPtrRC:$src),
- (MY_STORE $val, $src)
+ (MY_STORE XRegs_EvenIfRequired:$val, $src)
>;
// Wrapped in RegisterOperand
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