[llvm] [AArch64] Eliminate redundant setcc on vector comparison results (PR #171431)

[via llvm-commits]

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@@ -4746,6 +4746,20 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
     }
   }
 
+  // setcc X, 0, setlt --> X  (when X is all sign bits)
+  // setcc X, 0, setne --> X  (when X is all sign bits)
+  //
+  // When we know that X has 0 or -1 in each lane, this comparison will produce
+  // X. This is only true when boolean contents are represented via 0s and -1s.
+  if (OpVT.isVector() && VT == OpVT &&
+      // Check that the result of setcc is 0 and -1.
+      getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent &&
+      // Match only for checks X < 0 and X != 0
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DaKnig wrote:

actually this should also work for a few other compare instructions to zero:
- (unsigned) X > 0 (where X is all zeros or all ones, and ... zero is arbitrary, whatever unsigned value other than uint_max)
- all the opposites: when a hardware supports GT family better, we might get 0 on the left side

https://github.com/llvm/llvm-project/pull/171431