[llvm] 8663c30 - [X86] Cleanup uses of "(BW-1) - LOG2(C)" --> "CLZ(C)" instead. NFC. (#174167)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2026-01-03T13:55:45Z
New Revision: 8663c306e9b0e8492db66db62df61fac9694908a

URL: https://github.com/llvm/llvm-project/commit/8663c306e9b0e8492db66db62df61fac9694908a
DIFF: https://github.com/llvm/llvm-project/commit/8663c306e9b0e8492db66db62df61fac9694908a.diff

LOG: [X86] Cleanup uses of "(BW-1) - LOG2(C)" --> "CLZ(C)" instead. NFC. (#174167)

We know in both cases that the value `C` is a power-of-2 constant, so we
know the "(BW-1) - LOG2(C)" can be more obviously represented as
"CLZ(C)".

In both places it occurs it also makes it much easier to understand
what's being done: shift the single masked bit up to the MSB and then
use SRA to splat it to all bits.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 00b650f513516..fed4df707400f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -24553,13 +24553,13 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
     }
   }
 
-  // ICMP_EQ(AND(X,C),C) -> SRA(SHL(X,LOG2(C)),BW-1) iff C is power-of-2.
+  // ICMP_EQ(AND(X,C),C) -> SRA(SHL(X,CTLZ(C)),BW-1) iff C is power-of-2.
   if (Cond == ISD::SETEQ && Op0.getOpcode() == ISD::AND &&
       Op0.getOperand(1) == Op1 && Op0.hasOneUse()) {
     ConstantSDNode *C1 = isConstOrConstSplat(Op1);
     if (C1 && C1->getAPIntValue().isPowerOf2()) {
       unsigned BitWidth = VT.getScalarSizeInBits();
-      unsigned ShiftAmt = BitWidth - C1->getAPIntValue().logBase2() - 1;
+      unsigned ShiftAmt = C1->getAPIntValue().countl_zero();
 
       SDValue Result = Op0.getOperand(0);
       Result = DAG.getNode(ISD::SHL, dl, VT, Result,
@@ -48465,8 +48465,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
       SmallVector<int, 32> ShlVals;
       for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
         auto *MaskVal = cast<ConstantSDNode>(Mask.getOperand(i));
-        ShlVals.push_back(EltBitWidth - 1 -
-                          MaskVal->getAPIntValue().exactLogBase2());
+        ShlVals.push_back(MaskVal->getAPIntValue().countl_zero());
       }
       // vsel ((X & C) == 0), LHS, RHS --> vsel ((shl X, C') < 0), RHS, LHS
       MVT MskVT = Mask.getSimpleValueType();