[llvm] e4414a4 - [LV][doc] Update and extend the docs on floating-point reduction vectorization (#172809)

[via llvm-commits]

Author: Tibor Győri
Date: 2026-01-03T11:16:35Z
New Revision: e4414a4b568ef43ac0741e516d6400f9c029ad42

URL: https://github.com/llvm/llvm-project/commit/e4414a4b568ef43ac0741e516d6400f9c029ad42
DIFF: https://github.com/llvm/llvm-project/commit/e4414a4b568ef43ac0741e516d6400f9c029ad42.diff

LOG: [LV][doc] Update and extend the docs on floating-point reduction vectorization (#172809)

The docs for reduction vectorization currently say that

> We support floating point reduction operations when -ffast-math is
used.

This is outdated, as there are now cases where floating-point reductions
are vectorized even without -ffast-math, through ordered reduction.
This PR updates the documentation for reduction vectorization, noting
that that AArch64 and RISC-V default to ordered FP reductions being
permitted. Furthermore, an explanation of why the vectorization of FP
reduction is such a special case is added to the docs.

---------

Co-authored-by: GYT <tiborgyri at gmail.com>
Co-authored-by: Florian Hahn <flo at fhahn.com>

Added: 
    

Modified: 
    llvm/docs/Vectorizers.rst

Removed: 
    


################################################################################
diff  --git a/llvm/docs/Vectorizers.rst b/llvm/docs/Vectorizers.rst
index 9b80eb634fae0..50257bf5fde4b 100644
--- a/llvm/docs/Vectorizers.rst
+++ b/llvm/docs/Vectorizers.rst
@@ -200,7 +200,19 @@ reduction operations, such as addition, multiplication, XOR, AND and OR.
     return sum;
   }
 
-We support floating point reduction operations when `-ffast-math` is used.
+Fully vectorizing reductions requires reordering operations, which is
+problematic for floating-point arithmetic because it is not associative;
+therefore results may depend on the evaluation order.
+
+Changing floating-point results is implicitly prohibited by the C and C++
+standards, therefore LLVM supports vectorizing floating point reductions only
+when at least the `-fassociative-math -fno-signed-zeros -fno-trapping-math`
+subset of `-ffast-math` is used on most targets. On some targets, such as
+AArch64 and RISC-V, LLVM can generate ordered reductions that preserve the
+exact result, enabling limited, standards-compliant vectorization. However,
+ordered reductions are typically less efficient than traditionally vectorized
+reductions, therefore enabling floating-point reordering may still result in
+more performant reductions on these targets.
 
 Inductions
 ^^^^^^^^^^