[llvm] [SLP]Remove LoadCombine workaround after handling of the copyables (PR #174205)

[Alexey Bataev via llvm-commits]

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@@ -7,43 +7,10 @@
 
 define i64 @load_bswap(ptr %p) {
 ; CHECK-LABEL: @load_bswap(
-; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds [[V8I8:%.*]], ptr [[P:%.*]], i64 0, i32 1
-; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 2
-; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 3
-; CHECK-NEXT:    [[G4:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 4
-; CHECK-NEXT:    [[G5:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 5
-; CHECK-NEXT:    [[G6:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 6
-; CHECK-NEXT:    [[G7:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 7
-; CHECK-NEXT:    [[T0:%.*]] = load i8, ptr [[P]], align 1
-; CHECK-NEXT:    [[T1:%.*]] = load i8, ptr [[G1]], align 1
-; CHECK-NEXT:    [[T2:%.*]] = load i8, ptr [[G2]], align 1
-; CHECK-NEXT:    [[T3:%.*]] = load i8, ptr [[G3]], align 1
-; CHECK-NEXT:    [[T4:%.*]] = load i8, ptr [[G4]], align 1
-; CHECK-NEXT:    [[T5:%.*]] = load i8, ptr [[G5]], align 1
-; CHECK-NEXT:    [[T6:%.*]] = load i8, ptr [[G6]], align 1
-; CHECK-NEXT:    [[T7:%.*]] = load i8, ptr [[G7]], align 1
-; CHECK-NEXT:    [[Z0:%.*]] = zext i8 [[T0]] to i64
-; CHECK-NEXT:    [[Z1:%.*]] = zext i8 [[T1]] to i64
-; CHECK-NEXT:    [[Z2:%.*]] = zext i8 [[T2]] to i64
-; CHECK-NEXT:    [[Z3:%.*]] = zext i8 [[T3]] to i64
-; CHECK-NEXT:    [[Z4:%.*]] = zext i8 [[T4]] to i64
-; CHECK-NEXT:    [[Z5:%.*]] = zext i8 [[T5]] to i64
-; CHECK-NEXT:    [[Z6:%.*]] = zext i8 [[T6]] to i64
-; CHECK-NEXT:    [[Z7:%.*]] = zext i8 [[T7]] to i64
-; CHECK-NEXT:    [[SH0:%.*]] = shl nuw i64 [[Z0]], 56
-; CHECK-NEXT:    [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48
-; CHECK-NEXT:    [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40
-; CHECK-NEXT:    [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32
-; CHECK-NEXT:    [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24
-; CHECK-NEXT:    [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16
-; CHECK-NEXT:    [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8
-; CHECK-NEXT:    [[OR01:%.*]] = or i64 [[SH0]], [[SH1]]
-; CHECK-NEXT:    [[OR012:%.*]] = or i64 [[OR01]], [[SH2]]
-; CHECK-NEXT:    [[OR0123:%.*]] = or i64 [[OR012]], [[SH3]]
-; CHECK-NEXT:    [[OR01234:%.*]] = or i64 [[OR0123]], [[SH4]]
-; CHECK-NEXT:    [[OR012345:%.*]] = or i64 [[OR01234]], [[SH5]]
-; CHECK-NEXT:    [[OR0123456:%.*]] = or i64 [[OR012345]], [[SH6]]
-; CHECK-NEXT:    [[OR01234567:%.*]] = or i64 [[OR0123456]], [[Z7]]
+; CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i8>, ptr [[P:%.*]], align 1
+; CHECK-NEXT:    [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i64>
+; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw <8 x i64> [[TMP2]], <i64 56, i64 48, i64 40, i64 32, i64 24, i64 16, i64 8, i64 0>
+; CHECK-NEXT:    [[OR01234567:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP3]])
 ; CHECK-NEXT:    ret i64 [[OR01234567]]
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alexey-bataev wrote:

Just one thing I forgot to ask. Why InstCombiner does not recognize this pattern? SLP should not see such code at all, the whole scalar pattern should be recognized by InstCombiner, no?

https://github.com/llvm/llvm-project/pull/174205