[llvm] 775251a - [SelectionDAG] Remove OPC_EmitStringInteger from isel. (#173936)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 31 08:41:01 PST 2025
Author: Craig Topper
Date: 2025-12-31T08:40:57-08:00
New Revision: 775251a8074ca9f7e924a2705c9d407437e9df5b
URL: https://github.com/llvm/llvm-project/commit/775251a8074ca9f7e924a2705c9d407437e9df5b
DIFF: https://github.com/llvm/llvm-project/commit/775251a8074ca9f7e924a2705c9d407437e9df5b.diff
LOG: [SelectionDAG] Remove OPC_EmitStringInteger from isel. (#173936)
Instead emit this as an OPC_EmitInteger, but print the string
when the value is known to be 0..63 (when we don't need a VBR).
Also print the string into a comment when comments are not omitted
so it isn't lost when a VBR is needed.
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAGISel.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/test/TableGen/dag-isel-regclass-emit-enum.td
llvm/test/TableGen/dag-isel-subregs.td
llvm/utils/TableGen/Common/DAGISelMatcher.h
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
llvm/utils/TableGen/DAGISelMatcherGen.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 61c5fdc9ef2ba..569353670c532 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -261,9 +261,6 @@ class SelectionDAGISel {
OPC_EmitIntegerI16,
OPC_EmitIntegerI32,
OPC_EmitIntegerI64,
- OPC_EmitStringInteger,
- // Space-optimized forms that implicitly encode integer VT.
- OPC_EmitStringIntegerI32,
OPC_EmitRegister,
OPC_EmitRegisterI32,
OPC_EmitRegisterI64,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 5f5b40f6970e0..5bee87bb52322 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3693,7 +3693,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_CheckType:
case OPC_CheckTypeI32:
- case OPC_CheckTypeI64:
+ case OPC_CheckTypeI64: {
MVT::SimpleValueType VT;
switch (Opcode) {
case OPC_CheckTypeI32:
@@ -3709,6 +3709,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
if (!::CheckType(VT, N, TLI, CurDAG->getDataLayout()))
break;
continue;
+ }
case OPC_CheckTypeRes: {
unsigned Res = MatcherTable[MatcherIndex++];
@@ -3891,9 +3892,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_EmitIntegerI8:
case OPC_EmitIntegerI16:
case OPC_EmitIntegerI32:
- case OPC_EmitIntegerI64:
- case OPC_EmitStringInteger:
- case OPC_EmitStringIntegerI32: {
+ case OPC_EmitIntegerI64: {
MVT::SimpleValueType VT;
switch (Opcode) {
case OPC_EmitIntegerI8:
@@ -3903,7 +3902,6 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
VT = MVT::i16;
break;
case OPC_EmitIntegerI32:
- case OPC_EmitStringIntegerI32:
VT = MVT::i32;
break;
case OPC_EmitIntegerI64:
@@ -3913,14 +3911,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
VT = getSimpleVT(MatcherTable, MatcherIndex);
break;
}
- int64_t Val;
- if (Opcode >= OPC_EmitInteger && Opcode <= OPC_EmitIntegerI64) {
- Val = GetSignedVBR(MatcherTable, MatcherIndex);
- } else {
- Val = MatcherTable[MatcherIndex++];
- if (Val & 128)
- Val = GetVBR(Val, MatcherTable, MatcherIndex);
- }
+ int64_t Val = GetSignedVBR(MatcherTable, MatcherIndex);
RecordedNodes.emplace_back(
CurDAG->getSignedConstant(Val, SDLoc(NodeToMatch), VT,
/*isTarget=*/true),
diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
index 6a72eb3b34040..f2858fc7504a4 100644
--- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -25,14 +25,14 @@ def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
// CHECK-NEXT: OPC_Scope, 12, /*->18*/ // 2 children in Scope
// CHECK-NEXT: OPC_CheckChild1Integer, 0,
-// CHECK-NEXT: OPC_EmitIntegerI32, 0|128,1/*128*/, // 128 #1
+// CHECK-NEXT: OPC_EmitIntegerI32, 0|128,1/*128*/, // #1 = TestNamespace::GPRAbove127RegClassID
// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
// CHECK-NEXT: /*MVT::i32*/7, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 0))),
(COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
// CHECK: OPC_CheckChild1Integer, 1,
-// CHECK-NEXT: OPC_EmitStringIntegerI32, TestNamespace::GPR127RegClassID,
+// CHECK-NEXT: OPC_EmitIntegerI32, TestNamespace::GPR127RegClassID,
// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
// CHECK-NEXT: /*MVT::i32*/7, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 1))),
diff --git a/llvm/test/TableGen/dag-isel-subregs.td b/llvm/test/TableGen/dag-isel-subregs.td
index 8bee0e6976a83..e0e94e033a9b2 100644
--- a/llvm/test/TableGen/dag-isel-subregs.td
+++ b/llvm/test/TableGen/dag-isel-subregs.td
@@ -4,7 +4,7 @@ include "reg-with-subregs-common.td"
// CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
// CHECK: OPC_CheckChild1Integer, 0,
-// CHECK: OPC_EmitStringIntegerI32, sub0_sub1,
+// CHECK: OPC_EmitIntegerI32, sub0_sub1,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
(EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
diff --git a/llvm/utils/TableGen/Common/DAGISelMatcher.h b/llvm/utils/TableGen/Common/DAGISelMatcher.h
index e947dac3e6482..093da829b8966 100644
--- a/llvm/utils/TableGen/Common/DAGISelMatcher.h
+++ b/llvm/utils/TableGen/Common/DAGISelMatcher.h
@@ -857,16 +857,20 @@ class EmitIntegerMatcher : public Matcher {
/// EmitStringIntegerMatcher - A target constant whose value is represented
/// by a string.
class EmitStringIntegerMatcher : public Matcher {
- std::string Val;
+ std::string Str;
+ int64_t Val;
MVT VT;
unsigned ResultNo;
public:
- EmitStringIntegerMatcher(const std::string &val, MVT vt, unsigned resultNo)
- : Matcher(EmitStringInteger), Val(val), VT(vt), ResultNo(resultNo) {}
+ EmitStringIntegerMatcher(const std::string &str, int64_t val, MVT vt,
+ unsigned resultNo)
+ : Matcher(EmitStringInteger), Str(str), Val(val), VT(vt),
+ ResultNo(resultNo) {}
- const std::string &getValue() const { return Val; }
+ const std::string &getString() const { return Str; }
+ int64_t getValue() const { return Val; }
MVT getVT() const { return VT; }
unsigned getResultNo() const { return ResultNo; }
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 6a9321ba19736..a224dca5e5b91 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -818,27 +818,33 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N,
return Bytes;
}
case Matcher::EmitStringInteger: {
- const std::string &Val = cast<EmitStringIntegerMatcher>(N)->getValue();
- MVT VT = cast<EmitStringIntegerMatcher>(N)->getVT();
- // These should always fit into 7 bits.
- unsigned OpBytes;
+ const auto *SIM = cast<EmitStringIntegerMatcher>(N);
+ int64_t Val = SIM->getValue();
+ const std::string &Str = SIM->getString();
+ MVT VT = SIM->getVT();
+ unsigned TypeBytes = 0;
switch (VT.SimpleTy) {
case MVT::i32:
- OpBytes = 1;
- OS << "OPC_EmitStringIntegerI" << VT.getSizeInBits() << ", ";
+ OS << "OPC_EmitIntegerI" << VT.getSizeInBits() << ", ";
break;
default:
- OS << "OPC_EmitStringInteger, ";
+ OS << "OPC_EmitInteger, ";
if (!OmitComments)
OS << "/*" << getEnumName(VT) << "*/";
- OpBytes = EmitVBRValue(VT.SimpleTy, OS) + 1;
+ TypeBytes = EmitVBRValue(VT.SimpleTy, OS) + 1;
break;
}
- OS << Val << ',';
+ // If the value is 63 or smaller, use the string directly. Otherwise, use
+ // a VBR.
+ unsigned ValBytes = 1;
+ if (Val <= 63)
+ OS << Str << ',';
+ else
+ ValBytes = EmitSignedVBRValue(Val, OS);
if (!OmitComments)
- OS << " // #" << cast<EmitStringIntegerMatcher>(N)->getResultNo();
+ OS << " // #" << SIM->getResultNo() << " = " << Str;
OS << '\n';
- return OpBytes + 1;
+ return 1 + TypeBytes + ValBytes;
}
case Matcher::EmitRegister: {
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index d1c63d787de71..264fd063d2e29 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -705,14 +705,9 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode &N,
// StringIntegerMatcher. In this case, fallback to using IntegerMatcher.
const CodeGenRegisterClass &RC =
CGP.getTargetInfo().getRegisterClass(Def);
- if (RC.EnumValue <= 127) {
- std::string Value = RC.getQualifiedIdName();
- AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32,
- NextRecordedOperandNo));
- } else {
- AddMatcher(new EmitIntegerMatcher(RC.EnumValue, MVT::i32,
- NextRecordedOperandNo));
- }
+ std::string Name = RC.getQualifiedIdName();
+ AddMatcher(new EmitStringIntegerMatcher(Name, RC.EnumValue, MVT::i32,
+ NextRecordedOperandNo));
ResultOps.push_back(NextRecordedOperandNo++);
return;
}
@@ -720,20 +715,10 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode &N,
// Handle a subregister index. This is used for INSERT_SUBREG etc.
if (Def->isSubClassOf("SubRegIndex")) {
const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank();
- // If we have more than 127 subreg indices the encoding can overflow
- // 7 bit and we cannot use StringInteger.
- if (RB.getSubRegIndices().size() > 127) {
- const CodeGenSubRegIndex *I = RB.findSubRegIdx(Def);
- if (I->EnumValue > 127) {
- AddMatcher(new EmitIntegerMatcher(I->EnumValue, MVT::i32,
- NextRecordedOperandNo));
- ResultOps.push_back(NextRecordedOperandNo++);
- return;
- }
- }
- std::string Value = getQualifiedName(Def);
- AddMatcher(
- new EmitStringIntegerMatcher(Value, MVT::i32, NextRecordedOperandNo));
+ const CodeGenSubRegIndex *I = RB.findSubRegIdx(Def);
+ std::string Name = getQualifiedName(Def);
+ AddMatcher(new EmitStringIntegerMatcher(Name, I->EnumValue, MVT::i32,
+ NextRecordedOperandNo));
ResultOps.push_back(NextRecordedOperandNo++);
return;
}
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