[llvm] [SelectionDAG] Remove OPC_EmitStringInteger from isel. (PR #173936)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 30 22:49:49 PST 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/173936
>From bab8610b601cd1e9fcc6cc9f3c79617844a387f4 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 29 Dec 2025 14:05:10 -0800
Subject: [PATCH 1/2] [SelectionDAG] Use SLEB128 for signed integers in isel
table instead of 'signed rotated'. NFC
Previously, we used a VBR that stored the sign bit in bit 0 followed
by the absolute value in subsequent bits.
This patch changes it to use SLEB128 which discards redundant sign
bits, but keeps the bits in the same positions. This uses the same
number of bytes to encode values so doesn't change the table size.
My goal is to remove OPC_EmitStringInteger as a special opcode type.
Instead, we can print the string directly with OPC_EmitInteger for
any string that has an enum value of 0..63.
---
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 39 +++++++++----------
llvm/test/TableGen/DAGDefaultOps.td | 2 +-
.../TableGen/dag-isel-regclass-emit-enum.td | 4 +-
llvm/test/TableGen/dag-isel-subregs.td | 4 +-
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 18 ++++++---
5 files changed, 35 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 59375dd2ad349..06ebf7f4f6ad5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -96,6 +96,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
+#include "llvm/Support/LEB128.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
@@ -2719,6 +2720,14 @@ GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
return Val;
}
+LLVM_ATTRIBUTE_ALWAYS_INLINE static int64_t
+GetSignedVBR(const unsigned char *MatcherTable, unsigned &Idx) {
+ unsigned Len;
+ int64_t Val = decodeSLEB128(&MatcherTable[Idx], &Len);
+ Idx += Len;
+ return Val;
+}
+
/// getSimpleVT - Decode a value in MatcherTable, if it's a VBR encoded value,
/// use GetVBR to decode it.
LLVM_ATTRIBUTE_ALWAYS_INLINE static MVT::SimpleValueType
@@ -3024,25 +3033,10 @@ CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
}
-// Bit 0 stores the sign of the immediate. The upper bits contain the magnitude
-// shifted left by 1.
-static uint64_t decodeSignRotatedValue(uint64_t V) {
- if ((V & 1) == 0)
- return V >> 1;
- if (V != 1)
- return -(V >> 1);
- // There is no such thing as -0 with integers. "-0" really means MININT.
- return 1ULL << 63;
-}
-
LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
SDValue N) {
- int64_t Val = MatcherTable[MatcherIndex++];
- if (Val & 128)
- Val = GetVBR(Val, MatcherTable, MatcherIndex);
-
- Val = decodeSignRotatedValue(Val);
+ int64_t Val = GetSignedVBR(MatcherTable, MatcherIndex);
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
return C && C->getAPIntValue().trySExtValue() == Val;
@@ -3923,11 +3917,14 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
VT = getSimpleVT(MatcherTable, MatcherIndex);
break;
}
- int64_t Val = MatcherTable[MatcherIndex++];
- if (Val & 128)
- Val = GetVBR(Val, MatcherTable, MatcherIndex);
- if (Opcode >= OPC_EmitInteger && Opcode <= OPC_EmitIntegerI64)
- Val = decodeSignRotatedValue(Val);
+ int64_t Val;
+ if (Opcode >= OPC_EmitInteger && Opcode <= OPC_EmitIntegerI64) {
+ Val = GetSignedVBR(MatcherTable, MatcherIndex);
+ } else {
+ Val = MatcherTable[MatcherIndex++];
+ if (Val & 128)
+ Val = GetVBR(Val, MatcherTable, MatcherIndex);
+ }
RecordedNodes.emplace_back(
CurDAG->getSignedConstant(Val, SDLoc(NodeToMatch), VT,
/*isTarget=*/true),
diff --git a/llvm/test/TableGen/DAGDefaultOps.td b/llvm/test/TableGen/DAGDefaultOps.td
index 83c95b471373f..78cc58fcf9790 100644
--- a/llvm/test/TableGen/DAGDefaultOps.td
+++ b/llvm/test/TableGen/DAGDefaultOps.td
@@ -83,7 +83,7 @@ def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
// ADDINT-NEXT: OPC_CheckChild0Integer
// ADDINT-NEXT: OPC_RecordChild1
// ADDINT-NEXT: OPC_RecordChild2
-// ADDINT-NEXT: OPC_EmitIntegerI32, 2
+// ADDINT-NEXT: OPC_EmitIntegerI32, 1
// ADDINT-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::AddRRI)
// SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB)
diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
index c15835ee4fce3..6a72eb3b34040 100644
--- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -25,13 +25,13 @@ def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
// CHECK-NEXT: OPC_Scope, 12, /*->18*/ // 2 children in Scope
// CHECK-NEXT: OPC_CheckChild1Integer, 0,
-// CHECK-NEXT: OPC_EmitIntegerI32, 0|128,2/*256*/,
+// CHECK-NEXT: OPC_EmitIntegerI32, 0|128,1/*128*/, // 128 #1
// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
// CHECK-NEXT: /*MVT::i32*/7, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 0))),
(COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
-// CHECK: OPC_CheckChild1Integer, 2,
+// CHECK: OPC_CheckChild1Integer, 1,
// CHECK-NEXT: OPC_EmitStringIntegerI32, TestNamespace::GPR127RegClassID,
// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
// CHECK-NEXT: /*MVT::i32*/7, 2/*#Ops*/, 1, 0,
diff --git a/llvm/test/TableGen/dag-isel-subregs.td b/llvm/test/TableGen/dag-isel-subregs.td
index c66cb9e31ac0a..8bee0e6976a83 100644
--- a/llvm/test/TableGen/dag-isel-subregs.td
+++ b/llvm/test/TableGen/dag-isel-subregs.td
@@ -8,7 +8,7 @@ include "reg-with-subregs-common.td"
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
(EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
-// CHECK: OPC_CheckChild1Integer, 30,
-// CHECK: OPC_EmitIntegerI32, 10|128,2/*266*/,
+// CHECK: OPC_CheckChild1Integer, 15,
+// CHECK: OPC_EmitIntegerI32, 5|128,1/*133*/,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
(EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>;
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index f8367b09423b9..f35d8e1562c26 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -22,6 +22,7 @@
#include "llvm/ADT/TinyPtrVector.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Format.h"
+#include "llvm/Support/LEB128.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
@@ -258,13 +259,18 @@ static unsigned EmitVBRValue(uint64_t Val, raw_ostream &OS) {
/// Emit the specified signed value as a VBR. To improve compression we encode
/// positive numbers shifted left by 1 and negative numbers negated and shifted
/// left by 1 with bit 0 set.
-static unsigned EmitSignedVBRValue(uint64_t Val, raw_ostream &OS) {
- if ((int64_t)Val >= 0)
- Val = Val << 1;
- else
- Val = (-Val << 1) | 1;
+static unsigned EmitSignedVBRValue(int64_t Val, raw_ostream &OS) {
+ uint8_t Buffer[10];
+ unsigned Len = encodeSLEB128(Val, Buffer);
- return EmitVBRValue(Val, OS);
+ for (unsigned i = 0; i != Len - 1; ++i)
+ OS << static_cast<unsigned>(Buffer[i] & 127) << "|128,";
+
+ OS << static_cast<unsigned>(Buffer[Len - 1]);
+ if ((Len > 1 || Val < 0) && !OmitComments)
+ OS << "/*" << Val << "*/";
+ OS << ", ";
+ return Len;
}
// This is expensive and slow.
>From a06275c63568ee8b36173a98fb3fa36937b2841d Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 29 Dec 2025 16:31:28 -0800
Subject: [PATCH 2/2] [SelectionDAG] Remove OPC_EmitStringInteger from isel.
Instead emit this as an OPC_EmitInteger, but print the string
when the value is known to be 0..63 (when we don't need a VBR).
Also print the string into a comment when comments are not omitted
so it isn't lost when a VBR is needed.
Stacked on #173928.
---
llvm/include/llvm/CodeGen/SelectionDAGISel.h | 3 --
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 17 +++--------
.../TableGen/dag-isel-regclass-emit-enum.td | 4 +--
llvm/test/TableGen/dag-isel-subregs.td | 2 +-
llvm/utils/TableGen/Common/DAGISelMatcher.h | 12 +++++---
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 28 +++++++++++-------
llvm/utils/TableGen/DAGISelMatcherGen.cpp | 29 +++++--------------
7 files changed, 39 insertions(+), 56 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 147e780dfc191..c8ee7c3f37b3c 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -261,9 +261,6 @@ class SelectionDAGISel {
OPC_EmitIntegerI16,
OPC_EmitIntegerI32,
OPC_EmitIntegerI64,
- OPC_EmitStringInteger,
- // Space-optimized forms that implicitly encode integer VT.
- OPC_EmitStringIntegerI32,
OPC_EmitRegister,
OPC_EmitRegisterI32,
OPC_EmitRegisterI64,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 06ebf7f4f6ad5..7616eb24f7d64 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3697,7 +3697,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_CheckType:
case OPC_CheckTypeI32:
- case OPC_CheckTypeI64:
+ case OPC_CheckTypeI64: {
MVT::SimpleValueType VT;
switch (Opcode) {
case OPC_CheckTypeI32:
@@ -3713,6 +3713,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
if (!::CheckType(VT, N, TLI, CurDAG->getDataLayout()))
break;
continue;
+ }
case OPC_CheckTypeRes: {
unsigned Res = MatcherTable[MatcherIndex++];
@@ -3895,9 +3896,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_EmitIntegerI8:
case OPC_EmitIntegerI16:
case OPC_EmitIntegerI32:
- case OPC_EmitIntegerI64:
- case OPC_EmitStringInteger:
- case OPC_EmitStringIntegerI32: {
+ case OPC_EmitIntegerI64: {
MVT::SimpleValueType VT;
switch (Opcode) {
case OPC_EmitIntegerI8:
@@ -3907,7 +3906,6 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
VT = MVT::i16;
break;
case OPC_EmitIntegerI32:
- case OPC_EmitStringIntegerI32:
VT = MVT::i32;
break;
case OPC_EmitIntegerI64:
@@ -3917,14 +3915,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
VT = getSimpleVT(MatcherTable, MatcherIndex);
break;
}
- int64_t Val;
- if (Opcode >= OPC_EmitInteger && Opcode <= OPC_EmitIntegerI64) {
- Val = GetSignedVBR(MatcherTable, MatcherIndex);
- } else {
- Val = MatcherTable[MatcherIndex++];
- if (Val & 128)
- Val = GetVBR(Val, MatcherTable, MatcherIndex);
- }
+ int64_t Val = GetSignedVBR(MatcherTable, MatcherIndex);
RecordedNodes.emplace_back(
CurDAG->getSignedConstant(Val, SDLoc(NodeToMatch), VT,
/*isTarget=*/true),
diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
index 6a72eb3b34040..f2858fc7504a4 100644
--- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -25,14 +25,14 @@ def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
// CHECK-NEXT: OPC_Scope, 12, /*->18*/ // 2 children in Scope
// CHECK-NEXT: OPC_CheckChild1Integer, 0,
-// CHECK-NEXT: OPC_EmitIntegerI32, 0|128,1/*128*/, // 128 #1
+// CHECK-NEXT: OPC_EmitIntegerI32, 0|128,1/*128*/, // #1 = TestNamespace::GPRAbove127RegClassID
// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
// CHECK-NEXT: /*MVT::i32*/7, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 0))),
(COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
// CHECK: OPC_CheckChild1Integer, 1,
-// CHECK-NEXT: OPC_EmitStringIntegerI32, TestNamespace::GPR127RegClassID,
+// CHECK-NEXT: OPC_EmitIntegerI32, TestNamespace::GPR127RegClassID,
// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
// CHECK-NEXT: /*MVT::i32*/7, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 1))),
diff --git a/llvm/test/TableGen/dag-isel-subregs.td b/llvm/test/TableGen/dag-isel-subregs.td
index 8bee0e6976a83..e0e94e033a9b2 100644
--- a/llvm/test/TableGen/dag-isel-subregs.td
+++ b/llvm/test/TableGen/dag-isel-subregs.td
@@ -4,7 +4,7 @@ include "reg-with-subregs-common.td"
// CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
// CHECK: OPC_CheckChild1Integer, 0,
-// CHECK: OPC_EmitStringIntegerI32, sub0_sub1,
+// CHECK: OPC_EmitIntegerI32, sub0_sub1,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
(EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
diff --git a/llvm/utils/TableGen/Common/DAGISelMatcher.h b/llvm/utils/TableGen/Common/DAGISelMatcher.h
index e947dac3e6482..093da829b8966 100644
--- a/llvm/utils/TableGen/Common/DAGISelMatcher.h
+++ b/llvm/utils/TableGen/Common/DAGISelMatcher.h
@@ -857,16 +857,20 @@ class EmitIntegerMatcher : public Matcher {
/// EmitStringIntegerMatcher - A target constant whose value is represented
/// by a string.
class EmitStringIntegerMatcher : public Matcher {
- std::string Val;
+ std::string Str;
+ int64_t Val;
MVT VT;
unsigned ResultNo;
public:
- EmitStringIntegerMatcher(const std::string &val, MVT vt, unsigned resultNo)
- : Matcher(EmitStringInteger), Val(val), VT(vt), ResultNo(resultNo) {}
+ EmitStringIntegerMatcher(const std::string &str, int64_t val, MVT vt,
+ unsigned resultNo)
+ : Matcher(EmitStringInteger), Str(str), Val(val), VT(vt),
+ ResultNo(resultNo) {}
- const std::string &getValue() const { return Val; }
+ const std::string &getString() const { return Str; }
+ int64_t getValue() const { return Val; }
MVT getVT() const { return VT; }
unsigned getResultNo() const { return ResultNo; }
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index f35d8e1562c26..618da18398441 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -817,27 +817,33 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N,
return Bytes;
}
case Matcher::EmitStringInteger: {
- const std::string &Val = cast<EmitStringIntegerMatcher>(N)->getValue();
- MVT VT = cast<EmitStringIntegerMatcher>(N)->getVT();
- // These should always fit into 7 bits.
- unsigned OpBytes;
+ const auto *SIM = cast<EmitStringIntegerMatcher>(N);
+ int64_t Val = SIM->getValue();
+ const std::string &Str = SIM->getString();
+ MVT VT = SIM->getVT();
+ unsigned TypeBytes = 0;
switch (VT.SimpleTy) {
case MVT::i32:
- OpBytes = 1;
- OS << "OPC_EmitStringIntegerI" << VT.getSizeInBits() << ", ";
+ OS << "OPC_EmitIntegerI" << VT.getSizeInBits() << ", ";
break;
default:
- OS << "OPC_EmitStringInteger, ";
+ OS << "OPC_EmitInteger, ";
if (!OmitComments)
OS << "/*" << getEnumName(VT) << "*/";
- OpBytes = EmitVBRValue(VT.SimpleTy, OS) + 1;
+ TypeBytes = EmitVBRValue(VT.SimpleTy, OS) + 1;
break;
}
- OS << Val << ',';
+ // If the value is 63 or smaller, use the string directly. Otherwise, use
+ // a VBR.
+ unsigned ValBytes = 1;
+ if (Val <= 63)
+ OS << Str << ',';
+ else
+ ValBytes = EmitSignedVBRValue(Val, OS);
if (!OmitComments)
- OS << " // #" << cast<EmitStringIntegerMatcher>(N)->getResultNo();
+ OS << " // #" << SIM->getResultNo() << " = " << Str;
OS << '\n';
- return OpBytes + 1;
+ return 1 + TypeBytes + ValBytes;
}
case Matcher::EmitRegister: {
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index d1c63d787de71..264fd063d2e29 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -705,14 +705,9 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode &N,
// StringIntegerMatcher. In this case, fallback to using IntegerMatcher.
const CodeGenRegisterClass &RC =
CGP.getTargetInfo().getRegisterClass(Def);
- if (RC.EnumValue <= 127) {
- std::string Value = RC.getQualifiedIdName();
- AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32,
- NextRecordedOperandNo));
- } else {
- AddMatcher(new EmitIntegerMatcher(RC.EnumValue, MVT::i32,
- NextRecordedOperandNo));
- }
+ std::string Name = RC.getQualifiedIdName();
+ AddMatcher(new EmitStringIntegerMatcher(Name, RC.EnumValue, MVT::i32,
+ NextRecordedOperandNo));
ResultOps.push_back(NextRecordedOperandNo++);
return;
}
@@ -720,20 +715,10 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode &N,
// Handle a subregister index. This is used for INSERT_SUBREG etc.
if (Def->isSubClassOf("SubRegIndex")) {
const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank();
- // If we have more than 127 subreg indices the encoding can overflow
- // 7 bit and we cannot use StringInteger.
- if (RB.getSubRegIndices().size() > 127) {
- const CodeGenSubRegIndex *I = RB.findSubRegIdx(Def);
- if (I->EnumValue > 127) {
- AddMatcher(new EmitIntegerMatcher(I->EnumValue, MVT::i32,
- NextRecordedOperandNo));
- ResultOps.push_back(NextRecordedOperandNo++);
- return;
- }
- }
- std::string Value = getQualifiedName(Def);
- AddMatcher(
- new EmitStringIntegerMatcher(Value, MVT::i32, NextRecordedOperandNo));
+ const CodeGenSubRegIndex *I = RB.findSubRegIdx(Def);
+ std::string Name = getQualifiedName(Def);
+ AddMatcher(new EmitStringIntegerMatcher(Name, I->EnumValue, MVT::i32,
+ NextRecordedOperandNo));
ResultOps.push_back(NextRecordedOperandNo++);
return;
}
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