[llvm] [msan][NFCI] Add tests for dot product intrinsics on Arm (PR #174042)
Vitaly Buka via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 30 17:45:22 PST 2025
================
@@ -0,0 +1,579 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -mattr=+sve < %s -passes=msan -S | FileCheck %s
+;
+; Forked from llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll
+;
+; Strictly handled:
+; - llvm.aarch64.sve.abs.nxv16i8
+; - llvm.aarch64.sve.abs.nxv2i64
+; - llvm.aarch64.sve.abs.nxv4i32
+; - llvm.aarch64.sve.abs.nxv8i16
+; - llvm.aarch64.sve.neg.nxv16i8
+; - llvm.aarch64.sve.neg.nxv2i64
+; - llvm.aarch64.sve.neg.nxv4i32
+; - llvm.aarch64.sve.neg.nxv8i16
+; - llvm.aarch64.sve.sdot.lane.nxv2i64
+; - llvm.aarch64.sve.sdot.lane.nxv4i32
+; - llvm.aarch64.sve.sdot.nxv2i64
+; - llvm.aarch64.sve.sdot.nxv4i32
+; - llvm.aarch64.sve.udot.lane.nxv4i32
+; - llvm.aarch64.sve.udot.nxv2i64
+; - llvm.aarch64.sve.udot.nxv4i32
+;
+; Heuristically handled:
+; - llvm.aarch64.sve.sqadd.x.nxv16i8
+; - llvm.aarch64.sve.sqadd.x.nxv2i64
+; - llvm.aarch64.sve.sqadd.x.nxv4i32
+; - llvm.aarch64.sve.sqadd.x.nxv8i16
+; - llvm.aarch64.sve.sqsub.x.nxv16i8
+; - llvm.aarch64.sve.sqsub.x.nxv2i64
+; - llvm.aarch64.sve.sqsub.x.nxv4i32
+; - llvm.aarch64.sve.sqsub.x.nxv8i16
+; - llvm.aarch64.sve.uqadd.x.nxv16i8
+; - llvm.aarch64.sve.uqadd.x.nxv2i64
+; - llvm.aarch64.sve.uqadd.x.nxv4i32
+; - llvm.aarch64.sve.uqadd.x.nxv8i16
+; - llvm.aarch64.sve.uqsub.x.nxv16i8
+; - llvm.aarch64.sve.uqsub.x.nxv2i64
+; - llvm.aarch64.sve.uqsub.x.nxv4i32
+; - llvm.aarch64.sve.uqsub.x.nxv8i16
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-android9001"
+
+define <vscale x 16 x i8> @abs_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) sanitize_memory {
+; CHECK-LABEL: define <vscale x 16 x i8> @abs_i8(
+; CHECK-SAME: <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> [[A]], <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[B]])
+; CHECK-NEXT: store <vscale x 16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 16 x i8> [[OUT]]
+;
+ %out = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %a,
+ <vscale x 16 x i1> %pg,
+ <vscale x 16 x i8> %b)
+ ret <vscale x 16 x i8> %out
+}
+
+define <vscale x 8 x i16> @abs_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) sanitize_memory {
+; CHECK-LABEL: define <vscale x 8 x i16> @abs_i16(
+; CHECK-SAME: <vscale x 8 x i16> [[A:%.*]], <vscale x 8 x i1> [[PG:%.*]], <vscale x 8 x i16> [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> [[A]], <vscale x 8 x i1> [[PG]], <vscale x 8 x i16> [[B]])
+; CHECK-NEXT: store <vscale x 8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 8 x i16> [[OUT]]
+;
+ %out = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %a,
+ <vscale x 8 x i1> %pg,
+ <vscale x 8 x i16> %b)
+ ret <vscale x 8 x i16> %out
+}
+
+define <vscale x 4 x i32> @abs_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) sanitize_memory {
+; CHECK-LABEL: define <vscale x 4 x i32> @abs_i32(
+; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[B]])
+; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %a,
+ <vscale x 4 x i1> %pg,
+ <vscale x 4 x i32> %b)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 2 x i64> @abs_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) sanitize_memory {
+; CHECK-LABEL: define <vscale x 2 x i64> @abs_i64(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i1> [[PG:%.*]], <vscale x 2 x i64> [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> [[A]], <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> [[B]])
+; CHECK-NEXT: store <vscale x 2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %out = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %a,
+ <vscale x 2 x i1> %pg,
+ <vscale x 2 x i64> %b)
+ ret <vscale x 2 x i64> %out
+}
+
+
+define <vscale x 16 x i8> @neg_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) sanitize_memory {
+; CHECK-LABEL: define <vscale x 16 x i8> @neg_i8(
+; CHECK-SAME: <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> [[A]], <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[B]])
+; CHECK-NEXT: store <vscale x 16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 16 x i8> [[OUT]]
+;
+ %out = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> %a,
+ <vscale x 16 x i1> %pg,
+ <vscale x 16 x i8> %b)
+ ret <vscale x 16 x i8> %out
+}
+
+define <vscale x 8 x i16> @neg_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) sanitize_memory {
+; CHECK-LABEL: define <vscale x 8 x i16> @neg_i16(
+; CHECK-SAME: <vscale x 8 x i16> [[A:%.*]], <vscale x 8 x i1> [[PG:%.*]], <vscale x 8 x i16> [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> [[A]], <vscale x 8 x i1> [[PG]], <vscale x 8 x i16> [[B]])
+; CHECK-NEXT: store <vscale x 8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 8 x i16> [[OUT]]
+;
+ %out = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> %a,
+ <vscale x 8 x i1> %pg,
+ <vscale x 8 x i16> %b)
+ ret <vscale x 8 x i16> %out
+}
+
+define <vscale x 4 x i32> @neg_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) sanitize_memory {
+; CHECK-LABEL: define <vscale x 4 x i32> @neg_i32(
+; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[B]])
+; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> %a,
+ <vscale x 4 x i1> %pg,
+ <vscale x 4 x i32> %b)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 2 x i64> @neg_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) sanitize_memory {
+; CHECK-LABEL: define <vscale x 2 x i64> @neg_i64(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i1> [[PG:%.*]], <vscale x 2 x i64> [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> [[A]], <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> [[B]])
+; CHECK-NEXT: store <vscale x 2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %out = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> %a,
+ <vscale x 2 x i1> %pg,
+ <vscale x 2 x i64> %b)
+ ret <vscale x 2 x i64> %out
+}
+
+
+define <vscale x 4 x i32> @sdot_i32(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) sanitize_memory {
+; CHECK-LABEL: define <vscale x 4 x i32> @sdot_i32(
+; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 16 x i8> [[B]], <vscale x 16 x i8> [[C]])
+; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
+;
+ %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %a,
+ <vscale x 16 x i8> %b,
+ <vscale x 16 x i8> %c)
+ ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 2 x i64> @sdot_i64(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) sanitize_memory {
+; CHECK-LABEL: define <vscale x 2 x i64> @sdot_i64(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 8 x i16> [[B:%.*]], <vscale x 8 x i16> [[C:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> [[A]], <vscale x 8 x i16> [[B]], <vscale x 8 x i16> [[C]])
+; CHECK-NEXT: store <vscale x 2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 2 x i64> [[OUT]]
+;
+ %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %a,
+ <vscale x 8 x i16> %b,
+ <vscale x 8 x i16> %c)
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @test_sdot_i64_zero(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) sanitize_memory {
+; CHECK-LABEL: define <vscale x 2 x i64> @test_sdot_i64_zero(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 8 x i16> [[B:%.*]], <vscale x 8 x i16> [[C:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[VDOT1_I:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 8 x i16> [[B]], <vscale x 8 x i16> [[C]])
+; CHECK-NEXT: [[RET:%.*]] = add <vscale x 2 x i64> [[VDOT1_I]], [[A]]
+; CHECK-NEXT: store <vscale x 2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 2 x i64> [[RET]]
+;
+entry:
+ %vdot1.i = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)
+ %ret = add <vscale x 2 x i64> %vdot1.i, %a
+ ret <vscale x 2 x i64> %ret
+}
+
+define <vscale x 4 x i32> @test_sdot_i32_zero(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) sanitize_memory {
+; CHECK-LABEL: define <vscale x 4 x i32> @test_sdot_i32_zero(
+; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: call void @llvm.donothing()
+; CHECK-NEXT: [[VDOT1_I:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i8> [[B]], <vscale x 16 x i8> [[C]])
+; CHECK-NEXT: [[RET:%.*]] = add <vscale x 4 x i32> [[VDOT1_I]], [[A]]
+; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT: ret <vscale x 4 x i32> [[RET]]
+;
+entry:
+ %vdot1.i = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)
+ %ret = add <vscale x 4 x i32> %vdot1.i, %a
----------------
vitalybuka wrote:
the same for return, return as is, without unrelated operations
https://github.com/llvm/llvm-project/pull/174042
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