[llvm] [update_mc_test_checks] Support --show-inst output (PR #174011)
Alexander Richardson via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 30 11:04:25 PST 2025
https://github.com/arichardson created https://github.com/llvm/llvm-project/pull/174011
This is useful to check that the correct registers were used in cases
where different register classes use the same name in asm input/output.
>From 4fe4824c766bf2c85405ecfb39cb1b72167a7c2e Mon Sep 17 00:00:00 2001
From: Alex Richardson <alexrichardson at google.com>
Date: Tue, 30 Dec 2025 11:03:58 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
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Created using spr 1.3.8-beta.1
---
.../Inputs/riscv_show_inst.s | 2 +
.../Inputs/riscv_show_inst.s.expected | 8 ++++
.../riscv-show-inst.test | 5 +++
llvm/utils/update_mc_test_checks.py | 44 ++++++++++---------
4 files changed, 38 insertions(+), 21 deletions(-)
create mode 100644 llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s
create mode 100644 llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s.expected
create mode 100644 llvm/test/tools/UpdateTestChecks/update_mc_test_checks/riscv-show-inst.test
diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s
new file mode 100644
index 0000000000000..3f0250b831015
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s
@@ -0,0 +1,2 @@
+// RUN: llvm-mc -triple=riscv32 -mattr=+experimental-y -show-encoding -show-inst %s | FileCheck %s
+add a0, a1, a2
diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s.expected
new file mode 100644
index 0000000000000..644f5698e0137
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/riscv_show_inst.s.expected
@@ -0,0 +1,8 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py
+// RUN: llvm-mc -triple=riscv32 -mattr=+experimental-y -show-encoding -show-inst %s | FileCheck %s
+add a0, a1, a2
+// CHECK: add a0, a1, a2 # encoding: [0x33,0x85,0xc5,0x00]
+// CHECK-NEXT: # <MCInst #[[#MCINST1:]] ADD{{$}}
+// CHECK-NEXT: # <MCOperand Reg:X10>
+// CHECK-NEXT: # <MCOperand Reg:X11>
+// CHECK-NEXT: # <MCOperand Reg:X12>>
diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/riscv-show-inst.test b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/riscv-show-inst.test
new file mode 100644
index 0000000000000..f944c701c8df8
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/riscv-show-inst.test
@@ -0,0 +1,5 @@
+# REQUIRES: riscv-registered-target
+## Check that --show-inst output is handled correctly
+
+# RUN: cp -f %S/Inputs/riscv_show_inst.s %t.s && %update_mc_test_checks %t.s
+# RUN: diff -u %S/Inputs/riscv_show_inst.s.expected %t.s
diff --git a/llvm/utils/update_mc_test_checks.py b/llvm/utils/update_mc_test_checks.py
index 9b80267e8ad8c..db1be1c374100 100755
--- a/llvm/utils/update_mc_test_checks.py
+++ b/llvm/utils/update_mc_test_checks.py
@@ -90,15 +90,15 @@ def getErrString(err):
def getOutputString(out):
if not out:
return ""
- output = ""
+ lines = []
for line in out.splitlines():
if OUTPUT_SKIPPED_RE.search(line):
continue
if line.strip("\t ") == "":
continue
- output += line.lstrip("\t ")
- return output
+ lines.append(line.lstrip("\t "))
+ return "\n".join(lines)
def should_add_line_to_output(input_line, prefix_set, mc_mode):
@@ -111,23 +111,20 @@ def should_add_line_to_output(input_line, prefix_set, mc_mode):
)
-def getStdCheckLine(prefix, output, mc_mode):
- o = ""
- for line in output.splitlines():
- o += COMMENT[mc_mode] + " " + prefix + ": " + line + "\n"
+def getStdCheckLines(prefix: str, output: str, mc_mode) -> list[str]:
+ o = []
+ for i, line in enumerate(output.splitlines()):
+ maybe_next = "-NEXT" if i > 0 else ""
+ # Add an extra end-of-line check for --show-inst MCInst lines to
+ # ensure we matched the full instruction name and not just a prefix.
+ if line.startswith("# <MCInst "):
+ line += "{{$}}"
+ o.append(f"{COMMENT[mc_mode]} {prefix}{maybe_next}: {line}")
return o
-def getErrCheckLine(prefix, output, mc_mode, line_offset=1):
- return (
- COMMENT[mc_mode]
- + " "
- + prefix
- + ": "
- + ":[[@LINE-{}]]".format(line_offset)
- + output
- + "\n"
- )
+def getErrCheckLines(prefix: str, output: str, mc_mode, line_offset=1) -> list[str]:
+ return [f"{COMMENT[mc_mode]} {prefix}: :[[@LINE-{line_offset}]]{output}"]
def parse_token_defs(test_info):
@@ -318,6 +315,7 @@ def update_test(ti: common.TestInfo):
used_prefixes = set()
prefix_set = set([prefix for p in run_list for prefix in p[0]])
common.debug("Rewriting FileCheck prefixes:", str(prefix_set))
+ ginfo = common.make_asm_generalizer(version=1)
for test_id, input_line in enumerate(testlines):
# a {prefix : output, [runid] } dict
@@ -373,18 +371,22 @@ def update_test(ti: common.TestInfo):
# Generate check lines in alphabetical order.
check_lines = []
+ vars_seen = {prefix: dict() for prefix in selected_prefixes}
+ global_vars_seen = {prefix: dict() for prefix in selected_prefixes}
for prefix in sorted(selected_prefixes):
o, run_ids = p_dict[prefix]
used_prefixes.add(prefix)
if hasErr(o):
line_offset = len(check_lines) + 1
- check = getErrCheckLine(prefix, o, mc_mode, line_offset)
+ check = getErrCheckLines(prefix, o, mc_mode, line_offset)
else:
- check = getStdCheckLine(prefix, o, mc_mode)
+ check = getStdCheckLines(prefix, o, mc_mode)
+ check = common.generalize_check_lines(
+ check, ginfo, vars_seen[prefix], global_vars_seen[prefix]
+ )
- if check:
- check_lines.append(check.strip())
+ check_lines.extend(check)
generated_prefixes[input_line] = "\n".join(check_lines)
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