[llvm] [RISCV][SelectionDAG] Add a ISD::CTLS node for count leading redundant sign bits. Use it to select CLS(W). (PR #173417)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 30 10:28:05 PST 2025

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topperc wrote:

> I'm not complaining - I was just curious if you could match both?

Will do

https://github.com/llvm/llvm-project/pull/173417

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