[llvm] f5832c5 - [X86] Add i512 add/sub test coverage (#173998)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 30 08:07:20 PST 2025
Author: Simon Pilgrim
Date: 2025-12-30T16:07:15Z
New Revision: f5832c5d9f655b934fa641b416a0dea8686c6300
URL: https://github.com/llvm/llvm-project/commit/f5832c5d9f655b934fa641b416a0dea8686c6300
DIFF: https://github.com/llvm/llvm-project/commit/f5832c5d9f655b934fa641b416a0dea8686c6300.diff
LOG: [X86] Add i512 add/sub test coverage (#173998)
Base test coverage for #173996
Added:
llvm/test/CodeGen/X86/add-i512.ll
llvm/test/CodeGen/X86/sub-i512.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/add-i512.ll b/llvm/test/CodeGen/X86/add-i512.ll
new file mode 100644
index 0000000000000..16ba701072031
--- /dev/null
+++ b/llvm/test/CodeGen/X86/add-i512.ll
@@ -0,0 +1,447 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=knl | FileCheck %s --check-prefixes=AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512,AVX512VL
+
+define i512 @test_add_i512_reg_reg(i512 %a0, i512 %a1) nounwind {
+; SSE-LABEL: test_add_i512_reg_reg:
+; SSE: # %bb.0:
+; SSE-NEXT: addq {{[0-9]+}}(%rsp), %rsi
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %rdx
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %rcx
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %r8
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %r9
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %r10
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %rdi
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %r11
+; SSE-NEXT: movq %rcx, 16(%rax)
+; SSE-NEXT: movq %rdx, 8(%rax)
+; SSE-NEXT: movq %rsi, (%rax)
+; SSE-NEXT: movq %r8, 24(%rax)
+; SSE-NEXT: movq %r9, 32(%rax)
+; SSE-NEXT: movq %r10, 40(%rax)
+; SSE-NEXT: movq %rdi, 48(%rax)
+; SSE-NEXT: movq %r11, 56(%rax)
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: test_add_i512_reg_reg:
+; AVX2: # %bb.0:
+; AVX2-NEXT: addq {{[0-9]+}}(%rsp), %rsi
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %rdx
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %rcx
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %r8
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %r9
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %rdi
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %r10
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %r11
+; AVX2-NEXT: movq %rcx, 16(%rax)
+; AVX2-NEXT: movq %rdx, 8(%rax)
+; AVX2-NEXT: movq %rsi, (%rax)
+; AVX2-NEXT: movq %r8, 24(%rax)
+; AVX2-NEXT: movq %r9, 32(%rax)
+; AVX2-NEXT: movq %rdi, 40(%rax)
+; AVX2-NEXT: movq %r10, 48(%rax)
+; AVX2-NEXT: movq %r11, 56(%rax)
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: test_add_i512_reg_reg:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: addq {{[0-9]+}}(%rsp), %rsi
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %rdx
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %rcx
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %r8
+; AVX512F-NEXT: movq %rdi, %rax
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %r9
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %rdi
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %r10
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %r11
+; AVX512F-NEXT: movq %rcx, 16(%rax)
+; AVX512F-NEXT: movq %rdx, 8(%rax)
+; AVX512F-NEXT: movq %rsi, (%rax)
+; AVX512F-NEXT: movq %r8, 24(%rax)
+; AVX512F-NEXT: movq %r9, 32(%rax)
+; AVX512F-NEXT: movq %rdi, 40(%rax)
+; AVX512F-NEXT: movq %r10, 48(%rax)
+; AVX512F-NEXT: movq %r11, 56(%rax)
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: test_add_i512_reg_reg:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: movq %rdi, %rax
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX512VL-NEXT: addq {{[0-9]+}}(%rsp), %rsi
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %rdx
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %rcx
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %r8
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %r9
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %r11
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %rdi
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: movq %rcx, 16(%rax)
+; AVX512VL-NEXT: movq %rdx, 8(%rax)
+; AVX512VL-NEXT: movq %rsi, (%rax)
+; AVX512VL-NEXT: movq %r8, 24(%rax)
+; AVX512VL-NEXT: movq %r9, 32(%rax)
+; AVX512VL-NEXT: movq %r11, 40(%rax)
+; AVX512VL-NEXT: movq %rdi, 48(%rax)
+; AVX512VL-NEXT: movq %r10, 56(%rax)
+; AVX512VL-NEXT: retq
+ %r = add i512 %a0, %a1
+ ret i512 %r
+}
+
+define i512 @test_add_i512_reg_mem(i512 %a0, ptr %p1) nounwind {
+; SSE-LABEL: test_add_i512_reg_mem:
+; SSE: # %bb.0:
+; SSE-NEXT: pushq %rbx
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; SSE-NEXT: addq (%r10), %rsi
+; SSE-NEXT: adcq 8(%r10), %rdx
+; SSE-NEXT: adcq 16(%r10), %rcx
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: adcq 24(%r10), %r8
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; SSE-NEXT: adcq 32(%r10), %r9
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; SSE-NEXT: adcq 40(%r10), %r11
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; SSE-NEXT: adcq 48(%r10), %rdi
+; SSE-NEXT: adcq 56(%r10), %rbx
+; SSE-NEXT: movq %rsi, (%rax)
+; SSE-NEXT: movq %rdx, 8(%rax)
+; SSE-NEXT: movq %rcx, 16(%rax)
+; SSE-NEXT: movq %r8, 24(%rax)
+; SSE-NEXT: movq %r9, 32(%rax)
+; SSE-NEXT: movq %r11, 40(%rax)
+; SSE-NEXT: movq %rdi, 48(%rax)
+; SSE-NEXT: movq %rbx, 56(%rax)
+; SSE-NEXT: popq %rbx
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: test_add_i512_reg_mem:
+; AVX2: # %bb.0:
+; AVX2-NEXT: pushq %rbx
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX2-NEXT: addq (%r10), %rsi
+; AVX2-NEXT: adcq 8(%r10), %rdx
+; AVX2-NEXT: adcq 16(%r10), %rcx
+; AVX2-NEXT: adcq 24(%r10), %r8
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: adcq 32(%r10), %r9
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX2-NEXT: adcq 40(%r10), %rdi
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX2-NEXT: adcq 48(%r10), %r11
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; AVX2-NEXT: adcq 56(%r10), %rbx
+; AVX2-NEXT: movq %rsi, (%rax)
+; AVX2-NEXT: movq %rdx, 8(%rax)
+; AVX2-NEXT: movq %rcx, 16(%rax)
+; AVX2-NEXT: movq %r8, 24(%rax)
+; AVX2-NEXT: movq %r9, 32(%rax)
+; AVX2-NEXT: movq %rdi, 40(%rax)
+; AVX2-NEXT: movq %r11, 48(%rax)
+; AVX2-NEXT: movq %rbx, 56(%rax)
+; AVX2-NEXT: popq %rbx
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: test_add_i512_reg_mem:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: pushq %rbx
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512F-NEXT: addq (%r10), %rsi
+; AVX512F-NEXT: adcq 8(%r10), %rdx
+; AVX512F-NEXT: adcq 16(%r10), %rcx
+; AVX512F-NEXT: adcq 24(%r10), %r8
+; AVX512F-NEXT: movq %rdi, %rax
+; AVX512F-NEXT: adcq 32(%r10), %r9
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX512F-NEXT: adcq 40(%r10), %rdi
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX512F-NEXT: adcq 48(%r10), %r11
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; AVX512F-NEXT: adcq 56(%r10), %rbx
+; AVX512F-NEXT: movq %rsi, (%rax)
+; AVX512F-NEXT: movq %rdx, 8(%rax)
+; AVX512F-NEXT: movq %rcx, 16(%rax)
+; AVX512F-NEXT: movq %r8, 24(%rax)
+; AVX512F-NEXT: movq %r9, 32(%rax)
+; AVX512F-NEXT: movq %rdi, 40(%rax)
+; AVX512F-NEXT: movq %r11, 48(%rax)
+; AVX512F-NEXT: movq %rbx, 56(%rax)
+; AVX512F-NEXT: popq %rbx
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: test_add_i512_reg_mem:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: pushq %rbx
+; AVX512VL-NEXT: movq %rdi, %rax
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; AVX512VL-NEXT: addq (%rbx), %rsi
+; AVX512VL-NEXT: adcq 8(%rbx), %rdx
+; AVX512VL-NEXT: adcq 16(%rbx), %rcx
+; AVX512VL-NEXT: adcq 24(%rbx), %r8
+; AVX512VL-NEXT: adcq 32(%rbx), %r9
+; AVX512VL-NEXT: adcq 40(%rbx), %r11
+; AVX512VL-NEXT: adcq 48(%rbx), %rdi
+; AVX512VL-NEXT: adcq 56(%rbx), %r10
+; AVX512VL-NEXT: movq %rsi, (%rax)
+; AVX512VL-NEXT: movq %rdx, 8(%rax)
+; AVX512VL-NEXT: movq %rcx, 16(%rax)
+; AVX512VL-NEXT: movq %r8, 24(%rax)
+; AVX512VL-NEXT: movq %r9, 32(%rax)
+; AVX512VL-NEXT: movq %r11, 40(%rax)
+; AVX512VL-NEXT: movq %rdi, 48(%rax)
+; AVX512VL-NEXT: movq %r10, 56(%rax)
+; AVX512VL-NEXT: popq %rbx
+; AVX512VL-NEXT: retq
+ %a1 = load i512, ptr %p1
+ %r = add i512 %a0, %a1
+ ret i512 %r
+}
+
+define i512 @test_add_i512_mem_reg(ptr %p0, i512 %a1) nounwind {
+; SSE-LABEL: test_add_i512_mem_reg:
+; SSE: # %bb.0:
+; SSE-NEXT: addq (%rsi), %rdx
+; SSE-NEXT: adcq 8(%rsi), %rcx
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: adcq 16(%rsi), %r8
+; SSE-NEXT: movq 56(%rsi), %rdi
+; SSE-NEXT: adcq 24(%rsi), %r9
+; SSE-NEXT: movq 32(%rsi), %r10
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %r10
+; SSE-NEXT: movq 40(%rsi), %r11
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %r11
+; SSE-NEXT: movq 48(%rsi), %rsi
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %rsi
+; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %rdi
+; SSE-NEXT: movq %rdx, (%rax)
+; SSE-NEXT: movq %rcx, 8(%rax)
+; SSE-NEXT: movq %r8, 16(%rax)
+; SSE-NEXT: movq %r9, 24(%rax)
+; SSE-NEXT: movq %r10, 32(%rax)
+; SSE-NEXT: movq %r11, 40(%rax)
+; SSE-NEXT: movq %rsi, 48(%rax)
+; SSE-NEXT: movq %rdi, 56(%rax)
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: test_add_i512_mem_reg:
+; AVX2: # %bb.0:
+; AVX2-NEXT: addq (%rsi), %rdx
+; AVX2-NEXT: adcq 8(%rsi), %rcx
+; AVX2-NEXT: adcq 16(%rsi), %r8
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: adcq 24(%rsi), %r9
+; AVX2-NEXT: movq 32(%rsi), %rdi
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %rdi
+; AVX2-NEXT: movq 40(%rsi), %r10
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %r10
+; AVX2-NEXT: movq 48(%rsi), %r11
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %r11
+; AVX2-NEXT: movq 56(%rsi), %rsi
+; AVX2-NEXT: adcq {{[0-9]+}}(%rsp), %rsi
+; AVX2-NEXT: movq %rdx, (%rax)
+; AVX2-NEXT: movq %rcx, 8(%rax)
+; AVX2-NEXT: movq %r8, 16(%rax)
+; AVX2-NEXT: movq %r9, 24(%rax)
+; AVX2-NEXT: movq %rdi, 32(%rax)
+; AVX2-NEXT: movq %r10, 40(%rax)
+; AVX2-NEXT: movq %r11, 48(%rax)
+; AVX2-NEXT: movq %rsi, 56(%rax)
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: test_add_i512_mem_reg:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: addq (%rsi), %rdx
+; AVX512F-NEXT: adcq 8(%rsi), %rcx
+; AVX512F-NEXT: adcq 16(%rsi), %r8
+; AVX512F-NEXT: movq %rdi, %rax
+; AVX512F-NEXT: adcq 24(%rsi), %r9
+; AVX512F-NEXT: movq 32(%rsi), %rdi
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %rdi
+; AVX512F-NEXT: movq 40(%rsi), %r10
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %r10
+; AVX512F-NEXT: movq 48(%rsi), %r11
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %r11
+; AVX512F-NEXT: movq 56(%rsi), %rsi
+; AVX512F-NEXT: adcq {{[0-9]+}}(%rsp), %rsi
+; AVX512F-NEXT: movq %rdx, (%rax)
+; AVX512F-NEXT: movq %rcx, 8(%rax)
+; AVX512F-NEXT: movq %r8, 16(%rax)
+; AVX512F-NEXT: movq %r9, 24(%rax)
+; AVX512F-NEXT: movq %rdi, 32(%rax)
+; AVX512F-NEXT: movq %r10, 40(%rax)
+; AVX512F-NEXT: movq %r11, 48(%rax)
+; AVX512F-NEXT: movq %rsi, 56(%rax)
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: test_add_i512_mem_reg:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: pushq %rbx
+; AVX512VL-NEXT: movq %rdi, %rax
+; AVX512VL-NEXT: movq 56(%rsi), %rdi
+; AVX512VL-NEXT: movq 48(%rsi), %r10
+; AVX512VL-NEXT: movq 32(%rsi), %r11
+; AVX512VL-NEXT: movq 40(%rsi), %rbx
+; AVX512VL-NEXT: addq (%rsi), %rdx
+; AVX512VL-NEXT: adcq 8(%rsi), %rcx
+; AVX512VL-NEXT: adcq 16(%rsi), %r8
+; AVX512VL-NEXT: adcq 24(%rsi), %r9
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %r11
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %rbx
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: adcq {{[0-9]+}}(%rsp), %rdi
+; AVX512VL-NEXT: movq %rdx, (%rax)
+; AVX512VL-NEXT: movq %rcx, 8(%rax)
+; AVX512VL-NEXT: movq %r8, 16(%rax)
+; AVX512VL-NEXT: movq %r9, 24(%rax)
+; AVX512VL-NEXT: movq %r11, 32(%rax)
+; AVX512VL-NEXT: movq %rbx, 40(%rax)
+; AVX512VL-NEXT: movq %r10, 48(%rax)
+; AVX512VL-NEXT: movq %rdi, 56(%rax)
+; AVX512VL-NEXT: popq %rbx
+; AVX512VL-NEXT: retq
+ %a0 = load i512, ptr %p0
+ %r = add i512 %a0, %a1
+ ret i512 %r
+}
+
+define i512 @test_inc_i512_mem(ptr %p0) nounwind {
+; SSE-LABEL: test_inc_i512_mem:
+; SSE: # %bb.0:
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: movq 48(%rsi), %rcx
+; SSE-NEXT: movq 40(%rsi), %rdx
+; SSE-NEXT: movq 32(%rsi), %rdi
+; SSE-NEXT: movq 24(%rsi), %r8
+; SSE-NEXT: movq 16(%rsi), %r9
+; SSE-NEXT: movq (%rsi), %r10
+; SSE-NEXT: movq 8(%rsi), %r11
+; SSE-NEXT: addq $1, %r10
+; SSE-NEXT: adcq $0, %r11
+; SSE-NEXT: adcq $0, %r9
+; SSE-NEXT: adcq $0, %r8
+; SSE-NEXT: adcq $0, %rdi
+; SSE-NEXT: adcq $0, %rdx
+; SSE-NEXT: adcq $0, %rcx
+; SSE-NEXT: movq 56(%rsi), %rsi
+; SSE-NEXT: adcq $0, %rsi
+; SSE-NEXT: movq %r10, (%rax)
+; SSE-NEXT: movq %r11, 8(%rax)
+; SSE-NEXT: movq %r9, 16(%rax)
+; SSE-NEXT: movq %r8, 24(%rax)
+; SSE-NEXT: movq %rdi, 32(%rax)
+; SSE-NEXT: movq %rdx, 40(%rax)
+; SSE-NEXT: movq %rcx, 48(%rax)
+; SSE-NEXT: movq %rsi, 56(%rax)
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: test_inc_i512_mem:
+; AVX2: # %bb.0:
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: movq 56(%rsi), %rcx
+; AVX2-NEXT: movq 48(%rsi), %rdx
+; AVX2-NEXT: movq 40(%rsi), %rdi
+; AVX2-NEXT: movq 32(%rsi), %r8
+; AVX2-NEXT: movq 24(%rsi), %r9
+; AVX2-NEXT: movq 16(%rsi), %r10
+; AVX2-NEXT: movq (%rsi), %r11
+; AVX2-NEXT: movq 8(%rsi), %rsi
+; AVX2-NEXT: addq $1, %r11
+; AVX2-NEXT: adcq $0, %rsi
+; AVX2-NEXT: adcq $0, %r10
+; AVX2-NEXT: adcq $0, %r9
+; AVX2-NEXT: adcq $0, %r8
+; AVX2-NEXT: adcq $0, %rdi
+; AVX2-NEXT: adcq $0, %rdx
+; AVX2-NEXT: adcq $0, %rcx
+; AVX2-NEXT: movq %r11, (%rax)
+; AVX2-NEXT: movq %rsi, 8(%rax)
+; AVX2-NEXT: movq %r10, 16(%rax)
+; AVX2-NEXT: movq %r9, 24(%rax)
+; AVX2-NEXT: movq %r8, 32(%rax)
+; AVX2-NEXT: movq %rdi, 40(%rax)
+; AVX2-NEXT: movq %rdx, 48(%rax)
+; AVX2-NEXT: movq %rcx, 56(%rax)
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: test_inc_i512_mem:
+; AVX512: # %bb.0:
+; AVX512-NEXT: movq %rdi, %rax
+; AVX512-NEXT: movq 56(%rsi), %rcx
+; AVX512-NEXT: movq 48(%rsi), %rdx
+; AVX512-NEXT: movq 40(%rsi), %rdi
+; AVX512-NEXT: movq 32(%rsi), %r8
+; AVX512-NEXT: movq 24(%rsi), %r9
+; AVX512-NEXT: movq 16(%rsi), %r10
+; AVX512-NEXT: movq (%rsi), %r11
+; AVX512-NEXT: movq 8(%rsi), %rsi
+; AVX512-NEXT: addq $1, %r11
+; AVX512-NEXT: adcq $0, %rsi
+; AVX512-NEXT: adcq $0, %r10
+; AVX512-NEXT: adcq $0, %r9
+; AVX512-NEXT: adcq $0, %r8
+; AVX512-NEXT: adcq $0, %rdi
+; AVX512-NEXT: adcq $0, %rdx
+; AVX512-NEXT: adcq $0, %rcx
+; AVX512-NEXT: movq %r11, (%rax)
+; AVX512-NEXT: movq %rsi, 8(%rax)
+; AVX512-NEXT: movq %r10, 16(%rax)
+; AVX512-NEXT: movq %r9, 24(%rax)
+; AVX512-NEXT: movq %r8, 32(%rax)
+; AVX512-NEXT: movq %rdi, 40(%rax)
+; AVX512-NEXT: movq %rdx, 48(%rax)
+; AVX512-NEXT: movq %rcx, 56(%rax)
+; AVX512-NEXT: retq
+ %a0 = load i512, ptr %p0
+ %r = add i512 %a0, 1
+ ret i512 %r
+}
+
+define void @test_inc_i512_rmw(ptr %p0) nounwind {
+; CHECK-LABEL: test_inc_i512_rmw:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addq $1, (%rdi)
+; CHECK-NEXT: adcq $0, 8(%rdi)
+; CHECK-NEXT: adcq $0, 16(%rdi)
+; CHECK-NEXT: adcq $0, 24(%rdi)
+; CHECK-NEXT: adcq $0, 32(%rdi)
+; CHECK-NEXT: adcq $0, 40(%rdi)
+; CHECK-NEXT: adcq $0, 48(%rdi)
+; CHECK-NEXT: adcq $0, 56(%rdi)
+; CHECK-NEXT: retq
+;
+; AVX512-LABEL: test_inc_i512_rmw:
+; AVX512: # %bb.0:
+; AVX512-NEXT: addq $1, (%rdi)
+; AVX512-NEXT: adcq $0, 8(%rdi)
+; AVX512-NEXT: adcq $0, 16(%rdi)
+; AVX512-NEXT: adcq $0, 24(%rdi)
+; AVX512-NEXT: adcq $0, 32(%rdi)
+; AVX512-NEXT: adcq $0, 40(%rdi)
+; AVX512-NEXT: adcq $0, 48(%rdi)
+; AVX512-NEXT: adcq $0, 56(%rdi)
+; AVX512-NEXT: retq
+ %a0 = load i512, ptr %p0
+ %r = add i512 %a0, 1
+ store i512 %r, ptr %p0
+ ret void
+}
diff --git a/llvm/test/CodeGen/X86/sub-i512.ll b/llvm/test/CodeGen/X86/sub-i512.ll
new file mode 100644
index 0000000000000..b2b57fe923adc
--- /dev/null
+++ b/llvm/test/CodeGen/X86/sub-i512.ll
@@ -0,0 +1,477 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=knl | FileCheck %s --check-prefixes=AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512,AVX512VL
+
+define i512 @test_sub_i512_reg_reg(i512 %a0, i512 %a1) nounwind {
+; SSE-LABEL: test_sub_i512_reg_reg:
+; SSE: # %bb.0:
+; SSE-NEXT: subq {{[0-9]+}}(%rsp), %rsi
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %rcx
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %r8
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %r9
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %r10
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %rdi
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %r11
+; SSE-NEXT: movq %rcx, 16(%rax)
+; SSE-NEXT: movq %rdx, 8(%rax)
+; SSE-NEXT: movq %rsi, (%rax)
+; SSE-NEXT: movq %r8, 24(%rax)
+; SSE-NEXT: movq %r9, 32(%rax)
+; SSE-NEXT: movq %r10, 40(%rax)
+; SSE-NEXT: movq %rdi, 48(%rax)
+; SSE-NEXT: movq %r11, 56(%rax)
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: test_sub_i512_reg_reg:
+; AVX2: # %bb.0:
+; AVX2-NEXT: subq {{[0-9]+}}(%rsp), %rsi
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %rcx
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %r8
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %r9
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %rdi
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %r10
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %r11
+; AVX2-NEXT: movq %rcx, 16(%rax)
+; AVX2-NEXT: movq %rdx, 8(%rax)
+; AVX2-NEXT: movq %rsi, (%rax)
+; AVX2-NEXT: movq %r8, 24(%rax)
+; AVX2-NEXT: movq %r9, 32(%rax)
+; AVX2-NEXT: movq %rdi, 40(%rax)
+; AVX2-NEXT: movq %r10, 48(%rax)
+; AVX2-NEXT: movq %r11, 56(%rax)
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: test_sub_i512_reg_reg:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: subq {{[0-9]+}}(%rsp), %rsi
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %rcx
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %r8
+; AVX512F-NEXT: movq %rdi, %rax
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %r9
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %rdi
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %r10
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %r11
+; AVX512F-NEXT: movq %rcx, 16(%rax)
+; AVX512F-NEXT: movq %rdx, 8(%rax)
+; AVX512F-NEXT: movq %rsi, (%rax)
+; AVX512F-NEXT: movq %r8, 24(%rax)
+; AVX512F-NEXT: movq %r9, 32(%rax)
+; AVX512F-NEXT: movq %rdi, 40(%rax)
+; AVX512F-NEXT: movq %r10, 48(%rax)
+; AVX512F-NEXT: movq %r11, 56(%rax)
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: test_sub_i512_reg_reg:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: movq %rdi, %rax
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX512VL-NEXT: subq {{[0-9]+}}(%rsp), %rsi
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %rcx
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %r8
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %r9
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %r11
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %rdi
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: movq %rcx, 16(%rax)
+; AVX512VL-NEXT: movq %rdx, 8(%rax)
+; AVX512VL-NEXT: movq %rsi, (%rax)
+; AVX512VL-NEXT: movq %r8, 24(%rax)
+; AVX512VL-NEXT: movq %r9, 32(%rax)
+; AVX512VL-NEXT: movq %r11, 40(%rax)
+; AVX512VL-NEXT: movq %rdi, 48(%rax)
+; AVX512VL-NEXT: movq %r10, 56(%rax)
+; AVX512VL-NEXT: retq
+ %r = sub i512 %a0, %a1
+ ret i512 %r
+}
+
+define i512 @test_sub_i512_reg_mem(i512 %a0, ptr %p1) nounwind {
+; SSE-LABEL: test_sub_i512_reg_mem:
+; SSE: # %bb.0:
+; SSE-NEXT: pushq %rbx
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; SSE-NEXT: subq (%r10), %rsi
+; SSE-NEXT: sbbq 8(%r10), %rdx
+; SSE-NEXT: sbbq 16(%r10), %rcx
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: sbbq 24(%r10), %r8
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; SSE-NEXT: sbbq 32(%r10), %r9
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; SSE-NEXT: sbbq 40(%r10), %r11
+; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; SSE-NEXT: sbbq 48(%r10), %rdi
+; SSE-NEXT: sbbq 56(%r10), %rbx
+; SSE-NEXT: movq %rsi, (%rax)
+; SSE-NEXT: movq %rdx, 8(%rax)
+; SSE-NEXT: movq %rcx, 16(%rax)
+; SSE-NEXT: movq %r8, 24(%rax)
+; SSE-NEXT: movq %r9, 32(%rax)
+; SSE-NEXT: movq %r11, 40(%rax)
+; SSE-NEXT: movq %rdi, 48(%rax)
+; SSE-NEXT: movq %rbx, 56(%rax)
+; SSE-NEXT: popq %rbx
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: test_sub_i512_reg_mem:
+; AVX2: # %bb.0:
+; AVX2-NEXT: pushq %rbx
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX2-NEXT: subq (%r10), %rsi
+; AVX2-NEXT: sbbq 8(%r10), %rdx
+; AVX2-NEXT: sbbq 16(%r10), %rcx
+; AVX2-NEXT: sbbq 24(%r10), %r8
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: sbbq 32(%r10), %r9
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX2-NEXT: sbbq 40(%r10), %rdi
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX2-NEXT: sbbq 48(%r10), %r11
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; AVX2-NEXT: sbbq 56(%r10), %rbx
+; AVX2-NEXT: movq %rsi, (%rax)
+; AVX2-NEXT: movq %rdx, 8(%rax)
+; AVX2-NEXT: movq %rcx, 16(%rax)
+; AVX2-NEXT: movq %r8, 24(%rax)
+; AVX2-NEXT: movq %r9, 32(%rax)
+; AVX2-NEXT: movq %rdi, 40(%rax)
+; AVX2-NEXT: movq %r11, 48(%rax)
+; AVX2-NEXT: movq %rbx, 56(%rax)
+; AVX2-NEXT: popq %rbx
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: test_sub_i512_reg_mem:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: pushq %rbx
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512F-NEXT: subq (%r10), %rsi
+; AVX512F-NEXT: sbbq 8(%r10), %rdx
+; AVX512F-NEXT: sbbq 16(%r10), %rcx
+; AVX512F-NEXT: sbbq 24(%r10), %r8
+; AVX512F-NEXT: movq %rdi, %rax
+; AVX512F-NEXT: sbbq 32(%r10), %r9
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX512F-NEXT: sbbq 40(%r10), %rdi
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX512F-NEXT: sbbq 48(%r10), %r11
+; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; AVX512F-NEXT: sbbq 56(%r10), %rbx
+; AVX512F-NEXT: movq %rsi, (%rax)
+; AVX512F-NEXT: movq %rdx, 8(%rax)
+; AVX512F-NEXT: movq %rcx, 16(%rax)
+; AVX512F-NEXT: movq %r8, 24(%rax)
+; AVX512F-NEXT: movq %r9, 32(%rax)
+; AVX512F-NEXT: movq %rdi, 40(%rax)
+; AVX512F-NEXT: movq %r11, 48(%rax)
+; AVX512F-NEXT: movq %rbx, 56(%rax)
+; AVX512F-NEXT: popq %rbx
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: test_sub_i512_reg_mem:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: pushq %rbx
+; AVX512VL-NEXT: movq %rdi, %rax
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; AVX512VL-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; AVX512VL-NEXT: subq (%rbx), %rsi
+; AVX512VL-NEXT: sbbq 8(%rbx), %rdx
+; AVX512VL-NEXT: sbbq 16(%rbx), %rcx
+; AVX512VL-NEXT: sbbq 24(%rbx), %r8
+; AVX512VL-NEXT: sbbq 32(%rbx), %r9
+; AVX512VL-NEXT: sbbq 40(%rbx), %r11
+; AVX512VL-NEXT: sbbq 48(%rbx), %rdi
+; AVX512VL-NEXT: sbbq 56(%rbx), %r10
+; AVX512VL-NEXT: movq %rsi, (%rax)
+; AVX512VL-NEXT: movq %rdx, 8(%rax)
+; AVX512VL-NEXT: movq %rcx, 16(%rax)
+; AVX512VL-NEXT: movq %r8, 24(%rax)
+; AVX512VL-NEXT: movq %r9, 32(%rax)
+; AVX512VL-NEXT: movq %r11, 40(%rax)
+; AVX512VL-NEXT: movq %rdi, 48(%rax)
+; AVX512VL-NEXT: movq %r10, 56(%rax)
+; AVX512VL-NEXT: popq %rbx
+; AVX512VL-NEXT: retq
+ %a1 = load i512, ptr %p1
+ %r = sub i512 %a0, %a1
+ ret i512 %r
+}
+
+define i512 @test_sub_i512_mem_reg(ptr %p0, i512 %a1) nounwind {
+; SSE-LABEL: test_sub_i512_mem_reg:
+; SSE: # %bb.0:
+; SSE-NEXT: pushq %r14
+; SSE-NEXT: pushq %rbx
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: movq 56(%rsi), %rdi
+; SSE-NEXT: movq 24(%rsi), %r10
+; SSE-NEXT: movq 16(%rsi), %r11
+; SSE-NEXT: movq (%rsi), %rbx
+; SSE-NEXT: movq 8(%rsi), %r14
+; SSE-NEXT: subq %rdx, %rbx
+; SSE-NEXT: sbbq %rcx, %r14
+; SSE-NEXT: sbbq %r8, %r11
+; SSE-NEXT: sbbq %r9, %r10
+; SSE-NEXT: movq 32(%rsi), %rcx
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %rcx
+; SSE-NEXT: movq 40(%rsi), %rdx
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx
+; SSE-NEXT: movq 48(%rsi), %rsi
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %rsi
+; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %rdi
+; SSE-NEXT: movq %rbx, (%rax)
+; SSE-NEXT: movq %r14, 8(%rax)
+; SSE-NEXT: movq %r11, 16(%rax)
+; SSE-NEXT: movq %r10, 24(%rax)
+; SSE-NEXT: movq %rcx, 32(%rax)
+; SSE-NEXT: movq %rdx, 40(%rax)
+; SSE-NEXT: movq %rsi, 48(%rax)
+; SSE-NEXT: movq %rdi, 56(%rax)
+; SSE-NEXT: popq %rbx
+; SSE-NEXT: popq %r14
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: test_sub_i512_mem_reg:
+; AVX2: # %bb.0:
+; AVX2-NEXT: pushq %rbx
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: movq 24(%rsi), %rdi
+; AVX2-NEXT: movq 16(%rsi), %r10
+; AVX2-NEXT: movq (%rsi), %r11
+; AVX2-NEXT: movq 8(%rsi), %rbx
+; AVX2-NEXT: subq %rdx, %r11
+; AVX2-NEXT: sbbq %rcx, %rbx
+; AVX2-NEXT: sbbq %r8, %r10
+; AVX2-NEXT: sbbq %r9, %rdi
+; AVX2-NEXT: movq 32(%rsi), %rcx
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %rcx
+; AVX2-NEXT: movq 40(%rsi), %rdx
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx
+; AVX2-NEXT: movq 48(%rsi), %r8
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %r8
+; AVX2-NEXT: movq 56(%rsi), %rsi
+; AVX2-NEXT: sbbq {{[0-9]+}}(%rsp), %rsi
+; AVX2-NEXT: movq %r11, (%rax)
+; AVX2-NEXT: movq %rbx, 8(%rax)
+; AVX2-NEXT: movq %r10, 16(%rax)
+; AVX2-NEXT: movq %rdi, 24(%rax)
+; AVX2-NEXT: movq %rcx, 32(%rax)
+; AVX2-NEXT: movq %rdx, 40(%rax)
+; AVX2-NEXT: movq %r8, 48(%rax)
+; AVX2-NEXT: movq %rsi, 56(%rax)
+; AVX2-NEXT: popq %rbx
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: test_sub_i512_mem_reg:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: pushq %rbx
+; AVX512F-NEXT: movq %rdi, %rax
+; AVX512F-NEXT: movq 24(%rsi), %rdi
+; AVX512F-NEXT: movq 16(%rsi), %r10
+; AVX512F-NEXT: movq (%rsi), %r11
+; AVX512F-NEXT: movq 8(%rsi), %rbx
+; AVX512F-NEXT: subq %rdx, %r11
+; AVX512F-NEXT: sbbq %rcx, %rbx
+; AVX512F-NEXT: sbbq %r8, %r10
+; AVX512F-NEXT: sbbq %r9, %rdi
+; AVX512F-NEXT: movq 32(%rsi), %rcx
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %rcx
+; AVX512F-NEXT: movq 40(%rsi), %rdx
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx
+; AVX512F-NEXT: movq 48(%rsi), %r8
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %r8
+; AVX512F-NEXT: movq 56(%rsi), %rsi
+; AVX512F-NEXT: sbbq {{[0-9]+}}(%rsp), %rsi
+; AVX512F-NEXT: movq %r11, (%rax)
+; AVX512F-NEXT: movq %rbx, 8(%rax)
+; AVX512F-NEXT: movq %r10, 16(%rax)
+; AVX512F-NEXT: movq %rdi, 24(%rax)
+; AVX512F-NEXT: movq %rcx, 32(%rax)
+; AVX512F-NEXT: movq %rdx, 40(%rax)
+; AVX512F-NEXT: movq %r8, 48(%rax)
+; AVX512F-NEXT: movq %rsi, 56(%rax)
+; AVX512F-NEXT: popq %rbx
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: test_sub_i512_mem_reg:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: pushq %r15
+; AVX512VL-NEXT: pushq %r14
+; AVX512VL-NEXT: pushq %r12
+; AVX512VL-NEXT: pushq %rbx
+; AVX512VL-NEXT: movq %rdi, %rax
+; AVX512VL-NEXT: movq 56(%rsi), %rdi
+; AVX512VL-NEXT: movq 48(%rsi), %r10
+; AVX512VL-NEXT: movq 40(%rsi), %r11
+; AVX512VL-NEXT: movq 32(%rsi), %rbx
+; AVX512VL-NEXT: movq 24(%rsi), %r14
+; AVX512VL-NEXT: movq 16(%rsi), %r15
+; AVX512VL-NEXT: movq (%rsi), %r12
+; AVX512VL-NEXT: movq 8(%rsi), %rsi
+; AVX512VL-NEXT: subq %rdx, %r12
+; AVX512VL-NEXT: sbbq %rcx, %rsi
+; AVX512VL-NEXT: sbbq %r8, %r15
+; AVX512VL-NEXT: sbbq %r9, %r14
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %rbx
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %r11
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %r10
+; AVX512VL-NEXT: sbbq {{[0-9]+}}(%rsp), %rdi
+; AVX512VL-NEXT: movq %r12, (%rax)
+; AVX512VL-NEXT: movq %rsi, 8(%rax)
+; AVX512VL-NEXT: movq %r15, 16(%rax)
+; AVX512VL-NEXT: movq %r14, 24(%rax)
+; AVX512VL-NEXT: movq %rbx, 32(%rax)
+; AVX512VL-NEXT: movq %r11, 40(%rax)
+; AVX512VL-NEXT: movq %r10, 48(%rax)
+; AVX512VL-NEXT: movq %rdi, 56(%rax)
+; AVX512VL-NEXT: popq %rbx
+; AVX512VL-NEXT: popq %r12
+; AVX512VL-NEXT: popq %r14
+; AVX512VL-NEXT: popq %r15
+; AVX512VL-NEXT: retq
+ %a0 = load i512, ptr %p0
+ %r = sub i512 %a0, %a1
+ ret i512 %r
+}
+
+define i512 @test_dec_i512_mem(ptr %p0) nounwind {
+; SSE-LABEL: test_dec_i512_mem:
+; SSE: # %bb.0:
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: movq 48(%rsi), %rcx
+; SSE-NEXT: movq 40(%rsi), %rdx
+; SSE-NEXT: movq 32(%rsi), %rdi
+; SSE-NEXT: movq 24(%rsi), %r8
+; SSE-NEXT: movq 16(%rsi), %r9
+; SSE-NEXT: movq (%rsi), %r10
+; SSE-NEXT: movq 8(%rsi), %r11
+; SSE-NEXT: addq $-1, %r10
+; SSE-NEXT: adcq $-1, %r11
+; SSE-NEXT: adcq $-1, %r9
+; SSE-NEXT: adcq $-1, %r8
+; SSE-NEXT: adcq $-1, %rdi
+; SSE-NEXT: adcq $-1, %rdx
+; SSE-NEXT: adcq $-1, %rcx
+; SSE-NEXT: movq 56(%rsi), %rsi
+; SSE-NEXT: adcq $-1, %rsi
+; SSE-NEXT: movq %r10, (%rax)
+; SSE-NEXT: movq %r11, 8(%rax)
+; SSE-NEXT: movq %r9, 16(%rax)
+; SSE-NEXT: movq %r8, 24(%rax)
+; SSE-NEXT: movq %rdi, 32(%rax)
+; SSE-NEXT: movq %rdx, 40(%rax)
+; SSE-NEXT: movq %rcx, 48(%rax)
+; SSE-NEXT: movq %rsi, 56(%rax)
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: test_dec_i512_mem:
+; AVX2: # %bb.0:
+; AVX2-NEXT: movq %rdi, %rax
+; AVX2-NEXT: movq 56(%rsi), %rcx
+; AVX2-NEXT: movq 48(%rsi), %rdx
+; AVX2-NEXT: movq 40(%rsi), %rdi
+; AVX2-NEXT: movq 32(%rsi), %r8
+; AVX2-NEXT: movq 24(%rsi), %r9
+; AVX2-NEXT: movq 16(%rsi), %r10
+; AVX2-NEXT: movq (%rsi), %r11
+; AVX2-NEXT: movq 8(%rsi), %rsi
+; AVX2-NEXT: addq $-1, %r11
+; AVX2-NEXT: adcq $-1, %rsi
+; AVX2-NEXT: adcq $-1, %r10
+; AVX2-NEXT: adcq $-1, %r9
+; AVX2-NEXT: adcq $-1, %r8
+; AVX2-NEXT: adcq $-1, %rdi
+; AVX2-NEXT: adcq $-1, %rdx
+; AVX2-NEXT: adcq $-1, %rcx
+; AVX2-NEXT: movq %r11, (%rax)
+; AVX2-NEXT: movq %rsi, 8(%rax)
+; AVX2-NEXT: movq %r10, 16(%rax)
+; AVX2-NEXT: movq %r9, 24(%rax)
+; AVX2-NEXT: movq %r8, 32(%rax)
+; AVX2-NEXT: movq %rdi, 40(%rax)
+; AVX2-NEXT: movq %rdx, 48(%rax)
+; AVX2-NEXT: movq %rcx, 56(%rax)
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: test_dec_i512_mem:
+; AVX512: # %bb.0:
+; AVX512-NEXT: movq %rdi, %rax
+; AVX512-NEXT: movq 56(%rsi), %rcx
+; AVX512-NEXT: movq 48(%rsi), %rdx
+; AVX512-NEXT: movq 40(%rsi), %rdi
+; AVX512-NEXT: movq 32(%rsi), %r8
+; AVX512-NEXT: movq 24(%rsi), %r9
+; AVX512-NEXT: movq 16(%rsi), %r10
+; AVX512-NEXT: movq (%rsi), %r11
+; AVX512-NEXT: movq 8(%rsi), %rsi
+; AVX512-NEXT: addq $-1, %r11
+; AVX512-NEXT: adcq $-1, %rsi
+; AVX512-NEXT: adcq $-1, %r10
+; AVX512-NEXT: adcq $-1, %r9
+; AVX512-NEXT: adcq $-1, %r8
+; AVX512-NEXT: adcq $-1, %rdi
+; AVX512-NEXT: adcq $-1, %rdx
+; AVX512-NEXT: adcq $-1, %rcx
+; AVX512-NEXT: movq %r11, (%rax)
+; AVX512-NEXT: movq %rsi, 8(%rax)
+; AVX512-NEXT: movq %r10, 16(%rax)
+; AVX512-NEXT: movq %r9, 24(%rax)
+; AVX512-NEXT: movq %r8, 32(%rax)
+; AVX512-NEXT: movq %rdi, 40(%rax)
+; AVX512-NEXT: movq %rdx, 48(%rax)
+; AVX512-NEXT: movq %rcx, 56(%rax)
+; AVX512-NEXT: retq
+ %a0 = load i512, ptr %p0
+ %r = sub i512 %a0, 1
+ ret i512 %r
+}
+
+define void @test_dec_i512_rmw(ptr %p0) nounwind {
+; CHECK-LABEL: test_dec_i512_rmw:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addq $-1, (%rdi)
+; CHECK-NEXT: adcq $-1, 8(%rdi)
+; CHECK-NEXT: adcq $-1, 16(%rdi)
+; CHECK-NEXT: adcq $-1, 24(%rdi)
+; CHECK-NEXT: adcq $-1, 32(%rdi)
+; CHECK-NEXT: adcq $-1, 40(%rdi)
+; CHECK-NEXT: adcq $-1, 48(%rdi)
+; CHECK-NEXT: adcq $-1, 56(%rdi)
+; CHECK-NEXT: retq
+;
+; AVX512-LABEL: test_dec_i512_rmw:
+; AVX512: # %bb.0:
+; AVX512-NEXT: addq $-1, (%rdi)
+; AVX512-NEXT: adcq $-1, 8(%rdi)
+; AVX512-NEXT: adcq $-1, 16(%rdi)
+; AVX512-NEXT: adcq $-1, 24(%rdi)
+; AVX512-NEXT: adcq $-1, 32(%rdi)
+; AVX512-NEXT: adcq $-1, 40(%rdi)
+; AVX512-NEXT: adcq $-1, 48(%rdi)
+; AVX512-NEXT: adcq $-1, 56(%rdi)
+; AVX512-NEXT: retq
+ %a0 = load i512, ptr %p0
+ %r = sub i512 %a0, 1
+ store i512 %r, ptr %p0
+ ret void
+}
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