[llvm] [SDAG] Select _, X, X -> X (PR #173989)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 30 06:20:18 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
Author: None (DaKnig)
<details>
<summary>Changes</summary>
The code was simplified a tad. No tests since I am not sure that it would even catch any real case this deep into the functions.
---
Full diff: https://github.com/llvm/llvm-project/pull/173989.diff
1 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+3-5)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 74d00317c3649..f75b797abef19 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13383,11 +13383,9 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
if (!IsTAllZero && !IsTAllOne && !IsFAllZero && !IsFAllOne)
return SDValue();
- // select Cond, 0, 0 → 0
- if (IsTAllZero && IsFAllZero) {
- return VT.isFloatingPoint() ? DAG.getConstantFP(0.0, DL, VT)
- : DAG.getConstant(0, DL, VT);
- }
+ // select Cond, X, X → X
+ if (TVal == FVal)
+ return TVal;
// check select(setgt lhs, -1), 1, -1 --> or (sra lhs, bitwidth - 1), 1
APInt TValAPInt;
``````````
</details>
https://github.com/llvm/llvm-project/pull/173989
More information about the llvm-commits
mailing list