[llvm] [RISCV][SelectionDAG] Add a ISD::CTLS node for count leading redundant sign bits. Use it to select CLS(W). (PR #173417)

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 30 06:06:05 PST 2025

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RKSimon wrote:

aarch64 uses this pattern:
https://github.com/llvm/llvm-project/blob/6ec2ec4826b51d7d809fe08b36883a78d7dc0b98/llvm/lib/Target/AArch64/AArch64InstrInfo.td#L3294-L3299

https://github.com/llvm/llvm-project/pull/173417

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