[llvm] Revert "[aarch64] Mix the frame pointer with the stack cookie when protecting the stack (#161114)" (PR #173987)
Leandro Lupori via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 30 04:59:50 PST 2025
https://github.com/luporl created https://github.com/llvm/llvm-project/pull/173987
This reverts commit b6bfa856860bb4304e635102872a4c994af101b4.
This commit broke Windows on Arm bots.
>From fa17c0c24b9276e62e8c7de41991e880783368d6 Mon Sep 17 00:00:00 2001
From: Leandro Lupori <leandro.lupori at linaro.org>
Date: Tue, 30 Dec 2025 09:56:24 -0300
Subject: [PATCH] Revert "[aarch64] Mix the frame pointer with the stack cookie
when protecting the stack (#161114)"
This reverts commit b6bfa856860bb4304e635102872a4c994af101b4.
This commit broke Windows on Arm bots.
---
llvm/include/llvm/CodeGen/TargetLowering.h | 10 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 12 +-
llvm/lib/CodeGen/StackProtector.cpp | 2 +-
.../Target/AArch64/AArch64ISelDAGToDAG.cpp | 15 ---
.../Target/AArch64/AArch64ISelLowering.cpp | 19 ----
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 4 -
.../lib/Target/AArch64/AArch64InstrFormats.td | 2 -
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 12 --
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 5 -
llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +-
llvm/lib/Target/X86/X86ISelLowering.h | 8 +-
.../CodeGen/AArch64/arm64ec-indirect-call.ll | 1 -
llvm/test/CodeGen/AArch64/mingw-refptr.ll | 105 ++++++------------
.../CodeGen/AArch64/stack-protector-target.ll | 8 +-
15 files changed, 59 insertions(+), 156 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 7fb2517e5c625..8ad64a852b74d 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2150,10 +2150,11 @@ class LLVM_ABI TargetLoweringBase {
/// getIRStackGuard returns nullptr.
virtual Value *getSDagStackGuard(const Module &M) const;
- /// If this function returns true, stack protection checks should mix the
+ /// If this function returns true, stack protection checks should XOR the
+ /// frame pointer (or whichever pointer is used to address locals) into the
/// stack guard value before checking it. getIRStackGuard must return nullptr
/// if this returns true.
- virtual bool useStackGuardMixCookie() const { return false; }
+ virtual bool useStackGuardXorFP() const { return false; }
/// If the target has a standard stack protection check function that
/// performs validation and error handling, returns the function. Otherwise,
@@ -5859,9 +5860,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
virtual bool useLoadStackGuardNode(const Module &M) const { return false; }
- virtual SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
- const SDLoc &DL,
- bool FailureBB) const {
+ virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
+ const SDLoc &DL) const {
llvm_unreachable("not implemented for this target");
}
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 1698a6433e370..d87a2311d5739 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -4009,9 +4009,8 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile)
.getReg(0);
- if (TLI->useStackGuardMixCookie()) {
- LLVM_DEBUG(
- dbgs() << "Stack protector mix'ing the cookie not yet implemented");
+ if (TLI->useStackGuardXorFP()) {
+ LLVM_DEBUG(dbgs() << "Stack protector xor'ing with FP not yet implemented");
return false;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index c915cc058b4c5..ba70484ccd034 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3127,8 +3127,8 @@ void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
MachineMemOperand::MOVolatile);
- if (TLI.useStackGuardMixCookie())
- GuardVal = TLI.emitStackGuardMixCookie(DAG, GuardVal, dl, false);
+ if (TLI.useStackGuardXorFP())
+ GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl);
// If we're using function-based instrumentation, call the guard check
// function
@@ -3236,8 +3236,8 @@ void SelectionDAGBuilder::visitSPDescriptorFailure(
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
MachineMemOperand::MOVolatile);
- if (TLI.useStackGuardMixCookie())
- GuardVal = TLI.emitStackGuardMixCookie(DAG, GuardVal, dl, true);
+ if (TLI.useStackGuardXorFP())
+ GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl);
// The target provides a guard check function to validate the guard value.
// Generate a call to that function with the content of the guard slot as
@@ -7475,8 +7475,8 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
MachinePointerInfo(Global, 0), Align,
MachineMemOperand::MOVolatile);
}
- if (TLI.useStackGuardMixCookie())
- Res = TLI.emitStackGuardMixCookie(DAG, Res, sdl, false);
+ if (TLI.useStackGuardXorFP())
+ Res = TLI.emitStackGuardXorFP(DAG, Res, sdl);
DAG.setRoot(Chain);
setValue(&I, Res);
return;
diff --git a/llvm/lib/CodeGen/StackProtector.cpp b/llvm/lib/CodeGen/StackProtector.cpp
index 82e566106f3fd..9ddd61b0f20ef 100644
--- a/llvm/lib/CodeGen/StackProtector.cpp
+++ b/llvm/lib/CodeGen/StackProtector.cpp
@@ -581,7 +581,7 @@ bool InsertStackProtectors(const TargetMachine *TM, Function *F,
// impossible to emit the check in IR, so the target *must* support stack
// protection in SDAG.
bool SupportsSelectionDAGSP =
- TLI->useStackGuardMixCookie() ||
+ TLI->useStackGuardXorFP() ||
(EnableSelectionDAGSP && !TM->Options.EnableFastISel);
AllocaInst *AI = nullptr; // Place on stack that stores the stack guard.
BasicBlock *FailBB = nullptr;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 92d9f24b93086..dc207e0cbba95 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -74,8 +74,6 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
template <signed Low, signed High>
bool SelectRDSVLShiftImm(SDValue N, SDValue &Imm);
- bool SelectAddUXTXRegister(SDValue N, SDValue &Reg, SDValue &Shift);
-
bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
bool SelectArithUXTXRegister(SDValue N, SDValue &Reg, SDValue &Shift);
bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
@@ -961,19 +959,6 @@ bool AArch64DAGToDAGISel::SelectRDSVLShiftImm(SDValue N, SDValue &Imm) {
return false;
}
-/// SelectAddUXTXRegister - Select a "UXTX register" operand. This
-/// operand is referred by the instructions have SP operand
-bool AArch64DAGToDAGISel::SelectAddUXTXRegister(SDValue N, SDValue &Reg,
- SDValue &Shift) {
- // TODO: Relax condition to apply to more scenarios
- if (N.getOpcode() != ISD::LOAD)
- return false;
- Reg = N;
- Shift = CurDAG->getTargetConstant(getArithExtendImm(AArch64_AM::UXTX, 0),
- SDLoc(N), MVT::i32);
- return true;
-}
-
/// SelectArithExtendedRegister - Select a "extended register" operand. This
/// operand folds in an extend followed by an optional left shift.
bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f1465451802da..8b2922b341416 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -29528,25 +29528,6 @@ bool AArch64TargetLowering::useLoadStackGuardNode(const Module &M) const {
return true;
}
-bool AArch64TargetLowering::useStackGuardMixCookie() const {
- // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
- return Subtarget->getTargetTriple().isOSMSVCRT() &&
- !getTargetMachine().Options.EnableGlobalISel;
-}
-
-SDValue AArch64TargetLowering::emitStackGuardMixCookie(SelectionDAG &DAG,
- SDValue Val,
- const SDLoc &DL,
- bool FailureBB) const {
- if (FailureBB)
- return DAG.getNode(
- ISD::ADD, DL, Val.getValueType(),
- DAG.getCopyFromReg(DAG.getEntryNode(), DL,
- getStackPointerRegisterToSaveRestore(), MVT::i64),
- Val);
- return Val;
-}
-
unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
// Combine multiple FDIVs with the same divisor into multiple FMULs by the
// reciprocal if there are three or more FDIVs.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 2152d479ed61d..a066c63304b16 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -363,10 +363,6 @@ class AArch64TargetLowering : public TargetLowering {
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
bool useLoadStackGuardNode(const Module &M) const override;
- bool useStackGuardMixCookie() const override;
- SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
- const SDLoc &DL,
- bool FailureBB) const override;
TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(MVT VT) const override;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 07214e70d1324..d6221855a7962 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1400,8 +1400,6 @@ def gi_arith_extended_reg32to64_i64 :
def arith_uxtx : ComplexPattern<i64, 2, "SelectArithUXTXRegister", []>;
-def add_uxtx : ComplexPattern<i64, 2, "SelectAddUXTXRegister", []>;
-
// Floating-point immediate.
def fpimm16XForm : SDNodeXForm<fpimm, [{
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 5720bef575892..f82180fc57b99 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2544,18 +2544,6 @@ bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
.addMemOperand(*MI.memoperands_begin());
}
}
- // To match MSVC. Unlike x86_64 which uses xor instruction to mix the cookie,
- // we use sub instruction to mix the cookie on aarch64 for keeping the
- // existing inlining logic intact.
- if (Subtarget.getTargetTriple().isOSMSVCRT() &&
- !Subtarget.getTargetLowering()
- ->getTargetMachine()
- .Options.EnableGlobalISel) {
- BuildMI(MBB, MI, DL, get(AArch64::SUBXrx64), Reg)
- .addReg(AArch64::SP)
- .addReg(Reg, RegState::Kill)
- .addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 0));
- }
MBB.erase(MI);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index f3cd613a6bd99..b90f3552ed398 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2760,11 +2760,6 @@ def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
(ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
}
-let AddedComplexity = 1 in {
-def : Pat<(add copyFromSP:$R2, (add_uxtx GPR64:$R3, arith_extendlsl64:$imm)),
- (ADDXrx64 GPR64sp:$R2, GPR64:$R3, arith_extendlsl64:$imm)>;
-}
-
def trunc_isWorthFoldingALU : PatFrag<(ops node:$src), (trunc $src)> {
let PredicateCode = [{ return isWorthFoldingALU(SDValue(N, 0)); }];
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a12582afa7c30..275a00b571fe1 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2762,14 +2762,13 @@ bool X86TargetLowering::useLoadStackGuardNode(const Module &M) const {
return Subtarget.isTargetMachO() && Subtarget.is64Bit();
}
-bool X86TargetLowering::useStackGuardMixCookie() const {
+bool X86TargetLowering::useStackGuardXorFP() const {
// Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
}
-SDValue X86TargetLowering::emitStackGuardMixCookie(SelectionDAG &DAG,
- SDValue Val, const SDLoc &DL,
- bool FailureBB) const {
+SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
+ const SDLoc &DL) const {
EVT PtrTy = getPointerTy(DAG.getDataLayout());
unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 5d8e0505d3707..a528c311975d8 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1595,11 +1595,11 @@ namespace llvm {
Value *getIRStackGuard(IRBuilderBase &IRB) const override;
bool useLoadStackGuardNode(const Module &M) const override;
- bool useStackGuardMixCookie() const override;
+ bool useStackGuardXorFP() const override;
void insertSSPDeclarations(Module &M) const override;
- SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
- const SDLoc &DL,
- bool FailureBB) const override;
+ SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
+ const SDLoc &DL) const override;
+
/// Return true if the target stores SafeStack pointer at a fixed offset in
/// some non-standard address space, and populates the address space and
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-indirect-call.ll b/llvm/test/CodeGen/AArch64/arm64ec-indirect-call.ll
index 50e563847b853..e6a42c382e4f6 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-indirect-call.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-indirect-call.ll
@@ -32,7 +32,6 @@ define void @stackguard(ptr %g) sspreq {
; CHECK-NEXT: adrp x8, __security_cookie
; CHECK-NEXT: ldr x10, [sp, #8]
; CHECK-NEXT: ldr x8, [x8, :lo12:__security_cookie]
-; CHECK-NEXT: sub x8, sp, x8
; CHECK-NEXT: cmp x8, x10
; CHECK-NEXT: b.ne .LBB1_2
; CHECK-NEXT: // %bb.1:
diff --git a/llvm/test/CodeGen/AArch64/mingw-refptr.ll b/llvm/test/CodeGen/AArch64/mingw-refptr.ll
index 286039ce1e856..02c81440dd753 100644
--- a/llvm/test/CodeGen/AArch64/mingw-refptr.ll
+++ b/llvm/test/CodeGen/AArch64/mingw-refptr.ll
@@ -77,75 +77,39 @@ entry:
declare dso_local void @otherFunc()
define dso_local void @sspFunc() #0 {
-; CHECK-SD-LABEL: sspFunc:
-; CHECK-SD: .seh_proc sspFunc
-; CHECK-SD-NEXT: // %bb.0: // %entry
-; CHECK-SD-NEXT: sub sp, sp, #32
-; CHECK-SD-NEXT: .seh_stackalloc 32
-; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-SD-NEXT: .seh_save_reg x30, 16
-; CHECK-SD-NEXT: .seh_endprologue
-; CHECK-SD-NEXT: adrp x8, .refptr.__stack_chk_guard
-; CHECK-SD-NEXT: add x0, sp, #7
-; CHECK-SD-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
-; CHECK-SD-NEXT: ldr x8, [x8]
-; CHECK-SD-NEXT: sub x8, sp, x8
-; CHECK-SD-NEXT: str x8, [sp, #8]
-; CHECK-SD-NEXT: bl ptrUser
-; CHECK-SD-NEXT: adrp x8, .refptr.__stack_chk_guard
-; CHECK-SD-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
-; CHECK-SD-NEXT: ldr x9, [sp, #8]
-; CHECK-SD-NEXT: ldr x8, [x8]
-; CHECK-SD-NEXT: sub x8, sp, x8
-; CHECK-SD-NEXT: cmp x8, x9
-; CHECK-SD-NEXT: b.ne .LBB6_2
-; CHECK-SD-NEXT: // %bb.1: // %entry
-; CHECK-SD-NEXT: .seh_startepilogue
-; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-SD-NEXT: .seh_save_reg x30, 16
-; CHECK-SD-NEXT: add sp, sp, #32
-; CHECK-SD-NEXT: .seh_stackalloc 32
-; CHECK-SD-NEXT: .seh_endepilogue
-; CHECK-SD-NEXT: ret
-; CHECK-SD-NEXT: .LBB6_2: // %entry
-; CHECK-SD-NEXT: bl __stack_chk_fail
-; CHECK-SD-NEXT: brk #0x1
-; CHECK-SD-NEXT: .seh_endfunclet
-; CHECK-SD-NEXT: .seh_endproc
-;
-; CHECK-GI-LABEL: sspFunc:
-; CHECK-GI: .seh_proc sspFunc
-; CHECK-GI-NEXT: // %bb.0: // %entry
-; CHECK-GI-NEXT: sub sp, sp, #32
-; CHECK-GI-NEXT: .seh_stackalloc 32
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: .seh_save_reg x30, 16
-; CHECK-GI-NEXT: .seh_endprologue
-; CHECK-GI-NEXT: adrp x8, .refptr.__stack_chk_guard
-; CHECK-GI-NEXT: add x0, sp, #7
-; CHECK-GI-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
-; CHECK-GI-NEXT: ldr x8, [x8]
-; CHECK-GI-NEXT: str x8, [sp, #8]
-; CHECK-GI-NEXT: bl ptrUser
-; CHECK-GI-NEXT: adrp x8, .refptr.__stack_chk_guard
-; CHECK-GI-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
-; CHECK-GI-NEXT: ldr x9, [sp, #8]
-; CHECK-GI-NEXT: ldr x8, [x8]
-; CHECK-GI-NEXT: cmp x8, x9
-; CHECK-GI-NEXT: b.ne .LBB6_2
-; CHECK-GI-NEXT: // %bb.1: // %entry
-; CHECK-GI-NEXT: .seh_startepilogue
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: .seh_save_reg x30, 16
-; CHECK-GI-NEXT: add sp, sp, #32
-; CHECK-GI-NEXT: .seh_stackalloc 32
-; CHECK-GI-NEXT: .seh_endepilogue
-; CHECK-GI-NEXT: ret
-; CHECK-GI-NEXT: .LBB6_2: // %entry
-; CHECK-GI-NEXT: bl __stack_chk_fail
-; CHECK-GI-NEXT: brk #0x1
-; CHECK-GI-NEXT: .seh_endfunclet
-; CHECK-GI-NEXT: .seh_endproc
+; CHECK-LABEL: sspFunc:
+; CHECK: .seh_proc sspFunc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: .seh_stackalloc 32
+; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: .seh_save_reg x30, 16
+; CHECK-NEXT: .seh_endprologue
+; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
+; CHECK-NEXT: add x0, sp, #7
+; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
+; CHECK-NEXT: ldr x8, [x8]
+; CHECK-NEXT: str x8, [sp, #8]
+; CHECK-NEXT: bl ptrUser
+; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
+; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
+; CHECK-NEXT: ldr x9, [sp, #8]
+; CHECK-NEXT: ldr x8, [x8]
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: b.ne .LBB6_2
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: .seh_startepilogue
+; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: .seh_save_reg x30, 16
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: .seh_stackalloc 32
+; CHECK-NEXT: .seh_endepilogue
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_2: // %entry
+; CHECK-NEXT: bl __stack_chk_fail
+; CHECK-NEXT: brk #0x1
+; CHECK-NEXT: .seh_endfunclet
+; CHECK-NEXT: .seh_endproc
entry:
%c = alloca i8, align 1
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %c)
@@ -169,3 +133,6 @@ attributes #0 = { sspstrong }
; CHECK: .refptr.var:
; CHECK: .xword var
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/stack-protector-target.ll b/llvm/test/CodeGen/AArch64/stack-protector-target.ll
index 98ffaf830b495..b1ddd1d0d160f 100644
--- a/llvm/test/CodeGen/AArch64/stack-protector-target.ll
+++ b/llvm/test/CodeGen/AArch64/stack-protector-target.ll
@@ -31,18 +31,14 @@ declare void @_Z7CapturePi(ptr)
; WINDOWS-AARCH64: adrp x8, __security_cookie
; WINDOWS-AARCH64: ldr x8, [x8, :lo12:__security_cookie]
-; WINDOWS-AARCH64: sub x8, sp, x8
; WINDOWS-AARCH64: str x8, [sp, #8]
; WINDOWS-AARCH64: bl _Z7CapturePi
-; WINDOWS-AARCH64: ldr x8, [sp, #8]
-; WINDOWS-AARCH64: add x0, sp, x8
+; WINDOWS-AARCH64: ldr x0, [sp, #8]
; WINDOWS-AARCH64: bl __security_check_cookie
; WINDOWS-ARM64EC: adrp x8, __security_cookie
; WINDOWS-ARM64EC: ldr x8, [x8, :lo12:__security_cookie]
-; WINDOWS-ARM64EC: sub x8, sp, x8
; WINDOWS-ARM64EC: str x8, [sp, #8]
; WINDOWS-ARM64EC: bl "#_Z7CapturePi"
-; WINDOWS-ARM64EC: ldr x8, [sp, #8]
-; WINDOWS-ARM64EC: add x0, sp, x8
+; WINDOWS-ARM64EC: ldr x0, [sp, #8]
; WINDOWS-ARM64EC: bl "#__security_check_cookie_arm64ec"
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