[llvm] Revert "[X86] combineSelect - relax "vselect (X & C == 0), LHS, RHS" … (PR #173986)

[Walter Lee via llvm-commits]

https://github.com/googlewalt created https://github.com/llvm/llvm-project/pull/173986

…--> "vselect (X & C != 0), RHS, LHS" type limitation (#173366)"

This reverts commit 2ebe16c58591a4e8dab5e45d9e5de59cc933f2c7.  It causes clang to crashes.

>From 4a0c66f2d778f25aee67402b3434e6dac2ee418e Mon Sep 17 00:00:00 2001
From: Walter Lee <waltl at google.com>
Date: Tue, 30 Dec 2025 07:47:02 -0500
Subject: [PATCH] Revert "[X86] combineSelect - relax "vselect (X & C == 0),
 LHS, RHS" --> "vselect (X & C != 0), RHS, LHS" type limitation (#173366)"

This reverts commit 2ebe16c58591a4e8dab5e45d9e5de59cc933f2c7.  It causes clang to crashes.
---
 llvm/lib/Target/X86/X86ISelLowering.cpp |  4 ++--
 llvm/test/CodeGen/X86/vselect-pcmp.ll   | 25 ++++++++++++++++++-------
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a12582afa7c30..98725dc452c68 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -47914,7 +47914,6 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
   EVT CondVT = Cond.getValueType();
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   bool CondConstantVector = ISD::isBuildVectorOfConstantSDNodes(Cond.getNode());
-  unsigned EltBitWidth = VT.getScalarSizeInBits();
 
   // Attempt to combine (select M, (sub 0, X), X) -> (sub (xor X, M), M).
   // Limit this to cases of non-constant masks that createShuffleMaskFromVSELECT
@@ -48440,7 +48439,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
       Cond.getOperand(0).getOpcode() == ISD::AND &&
       isNullOrNullSplat(Cond.getOperand(1)) &&
       cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
-      Cond.getOperand(0).getScalarValueSizeInBits() == EltBitWidth) {
+      Cond.getOperand(0).getValueType() == VT) {
     // The 'and' mask must be composed of power-of-2 constants.
     SDValue And = Cond.getOperand(0);
     auto *C = isConstOrConstSplat(And.getOperand(1));
@@ -48454,6 +48453,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
     // If we have a non-splat but still powers-of-2 mask, AVX1 can use pmulld
     // and AVX2 can use vpsllv{dq}. 8-bit lacks a proper shift or multiply.
     // 16-bit lacks a proper blendv.
+    unsigned EltBitWidth = VT.getScalarSizeInBits();
     bool CanShiftBlend =
         TLI.isTypeLegal(VT) && ((Subtarget.hasAVX() && EltBitWidth == 32) ||
                                 (Subtarget.hasAVX2() && EltBitWidth == 64) ||
diff --git a/llvm/test/CodeGen/X86/vselect-pcmp.ll b/llvm/test/CodeGen/X86/vselect-pcmp.ll
index b9fdf71c62d2d..8e6c4d83c7617 100644
--- a/llvm/test/CodeGen/X86/vselect-pcmp.ll
+++ b/llvm/test/CodeGen/X86/vselect-pcmp.ll
@@ -544,12 +544,23 @@ define <4 x i64> @blend_splat1_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x
   ret <4 x i64> %r
 }
 
+; FIXME: use PSLLD(Z,31) like blend_splat1_mask_cond_v4i32
 define <4 x float> @blend_splat1_mask_cond_v4f32(<4 x i32> %x, <4 x float> %y, <4 x float> %z) {
-; AVX12-LABEL: blend_splat1_mask_cond_v4f32:
-; AVX12:       # %bb.0:
-; AVX12-NEXT:    vpslld $31, %xmm0, %xmm0
-; AVX12-NEXT:    vblendvps %xmm0, %xmm2, %xmm1, %xmm0
-; AVX12-NEXT:    retq
+; AVX1-LABEL: blend_splat1_mask_cond_v4f32:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vbroadcastss {{.*#+}} xmm3 = [1,1,1,1]
+; AVX1-NEXT:    vpand %xmm3, %xmm0, %xmm0
+; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm0, %xmm0
+; AVX1-NEXT:    vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: blend_splat1_mask_cond_v4f32:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm3 = [1,1,1,1]
+; AVX2-NEXT:    vpand %xmm3, %xmm0, %xmm0
+; AVX2-NEXT:    vpcmpeqd %xmm3, %xmm0, %xmm0
+; AVX2-NEXT:    vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; AVX2-NEXT:    retq
 ;
 ; AVX512F-LABEL: blend_splat1_mask_cond_v4f32:
 ; AVX512F:       # %bb.0:
@@ -572,8 +583,8 @@ define <4 x float> @blend_splat1_mask_cond_v4f32(<4 x i32> %x, <4 x float> %y, <
 ; XOP:       # %bb.0:
 ; XOP-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; XOP-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; XOP-NEXT:    vpcomneqd %xmm3, %xmm0, %xmm0
-; XOP-NEXT:    vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; XOP-NEXT:    vpcomeqd %xmm3, %xmm0, %xmm0
+; XOP-NEXT:    vblendvps %xmm0, %xmm1, %xmm2, %xmm0
 ; XOP-NEXT:    retq
   %a = and <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
   %c = icmp eq <4 x i32> %a, zeroinitializer