[llvm] 44514f7 - [SelectionDAG] Rename OPC_EmitInteger8->OPC_EmitIntegerI8. NFC (#173832)
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Mon Dec 29 11:12:48 PST 2025
Author: Craig Topper
Date: 2025-12-29T11:12:44-08:00
New Revision: 44514f791766afbddaa3b2deb5437a293e529610
URL: https://github.com/llvm/llvm-project/commit/44514f791766afbddaa3b2deb5437a293e529610
DIFF: https://github.com/llvm/llvm-project/commit/44514f791766afbddaa3b2deb5437a293e529610.diff
LOG: [SelectionDAG] Rename OPC_EmitInteger8->OPC_EmitIntegerI8. NFC (#173832)
Same for OPC_EmitInteger16/32/64 and OPC_EmitStringInteger32.
This matches OPC_CheckTypeI32, OPC_EmitRegisterI32, etc.
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAGISel.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/test/TableGen/DAGDefaultOps.td
llvm/test/TableGen/dag-isel-regclass-emit-enum.td
llvm/test/TableGen/dag-isel-subregs.td
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 7add717227963..147e780dfc191 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -257,13 +257,13 @@ class SelectionDAGISel {
OPC_EmitInteger,
// Space-optimized forms that implicitly encode integer VT.
- OPC_EmitInteger8,
- OPC_EmitInteger16,
- OPC_EmitInteger32,
- OPC_EmitInteger64,
+ OPC_EmitIntegerI8,
+ OPC_EmitIntegerI16,
+ OPC_EmitIntegerI32,
+ OPC_EmitIntegerI64,
OPC_EmitStringInteger,
// Space-optimized forms that implicitly encode integer VT.
- OPC_EmitStringInteger32,
+ OPC_EmitStringIntegerI32,
OPC_EmitRegister,
OPC_EmitRegisterI32,
OPC_EmitRegisterI64,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 6776adae64eb3..59375dd2ad349 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3898,25 +3898,25 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
}
case OPC_EmitInteger:
- case OPC_EmitInteger8:
- case OPC_EmitInteger16:
- case OPC_EmitInteger32:
- case OPC_EmitInteger64:
+ case OPC_EmitIntegerI8:
+ case OPC_EmitIntegerI16:
+ case OPC_EmitIntegerI32:
+ case OPC_EmitIntegerI64:
case OPC_EmitStringInteger:
- case OPC_EmitStringInteger32: {
+ case OPC_EmitStringIntegerI32: {
MVT::SimpleValueType VT;
switch (Opcode) {
- case OPC_EmitInteger8:
+ case OPC_EmitIntegerI8:
VT = MVT::i8;
break;
- case OPC_EmitInteger16:
+ case OPC_EmitIntegerI16:
VT = MVT::i16;
break;
- case OPC_EmitInteger32:
- case OPC_EmitStringInteger32:
+ case OPC_EmitIntegerI32:
+ case OPC_EmitStringIntegerI32:
VT = MVT::i32;
break;
- case OPC_EmitInteger64:
+ case OPC_EmitIntegerI64:
VT = MVT::i64;
break;
default:
@@ -3926,7 +3926,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
int64_t Val = MatcherTable[MatcherIndex++];
if (Val & 128)
Val = GetVBR(Val, MatcherTable, MatcherIndex);
- if (Opcode >= OPC_EmitInteger && Opcode <= OPC_EmitInteger64)
+ if (Opcode >= OPC_EmitInteger && Opcode <= OPC_EmitIntegerI64)
Val = decodeSignRotatedValue(Val);
RecordedNodes.emplace_back(
CurDAG->getSignedConstant(Val, SDLoc(NodeToMatch), VT,
diff --git a/llvm/test/TableGen/DAGDefaultOps.td b/llvm/test/TableGen/DAGDefaultOps.td
index 70c8413f2c053..83c95b471373f 100644
--- a/llvm/test/TableGen/DAGDefaultOps.td
+++ b/llvm/test/TableGen/DAGDefaultOps.td
@@ -76,20 +76,20 @@ def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
// ADD: SwitchOpcode{{.*}}TARGET_VAL(ISD::ADD)
// ADD-NEXT: OPC_RecordChild0
// ADD-NEXT: OPC_RecordChild1
-// ADD-NEXT: OPC_EmitInteger32, 0
+// ADD-NEXT: OPC_EmitIntegerI32, 0
// ADD-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::AddRRI)
// ADDINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_WO_CHAIN)
// ADDINT-NEXT: OPC_CheckChild0Integer
// ADDINT-NEXT: OPC_RecordChild1
// ADDINT-NEXT: OPC_RecordChild2
-// ADDINT-NEXT: OPC_EmitInteger32, 2
+// ADDINT-NEXT: OPC_EmitIntegerI32, 2
// ADDINT-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::AddRRI)
// SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB)
// SUB-NEXT: OPC_RecordChild0
// SUB-NEXT: OPC_RecordChild1
-// SUB-NEXT: OPC_EmitInteger32, 0
+// SUB-NEXT: OPC_EmitIntegerI32, 0
// SUB-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(::SubRRI)
// MULINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_W_CHAIN)
@@ -102,7 +102,7 @@ def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
// MULINT-NEXT: OPC_MorphNodeTo1Chain, TARGET_VAL(::MulRRI)
// MUL: SwitchOpcode{{.*}}TARGET_VAL(ISD::MUL)
-// MUL-NEXT: OPC_EmitInteger32, 0
+// MUL-NEXT: OPC_EmitIntegerI32, 0
// MUL-NEXT: OPC_RecordChild0
// MUL-NEXT: OPC_RecordChild1
// MUL-NEXT: OPC_MorphNodeTo1Chain, TARGET_VAL(::MulRRI)
diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
index c41a19e97e763..c15835ee4fce3 100644
--- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -25,14 +25,14 @@ def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
// CHECK-NEXT: OPC_Scope, 12, /*->18*/ // 2 children in Scope
// CHECK-NEXT: OPC_CheckChild1Integer, 0,
-// CHECK-NEXT: OPC_EmitInteger32, 0|128,2/*256*/,
+// CHECK-NEXT: OPC_EmitIntegerI32, 0|128,2/*256*/,
// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
// CHECK-NEXT: /*MVT::i32*/7, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 0))),
(COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
// CHECK: OPC_CheckChild1Integer, 2,
-// CHECK-NEXT: OPC_EmitStringInteger32, TestNamespace::GPR127RegClassID,
+// CHECK-NEXT: OPC_EmitStringIntegerI32, TestNamespace::GPR127RegClassID,
// CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
// CHECK-NEXT: /*MVT::i32*/7, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 1))),
diff --git a/llvm/test/TableGen/dag-isel-subregs.td b/llvm/test/TableGen/dag-isel-subregs.td
index 52ac0377bd2c9..c66cb9e31ac0a 100644
--- a/llvm/test/TableGen/dag-isel-subregs.td
+++ b/llvm/test/TableGen/dag-isel-subregs.td
@@ -4,11 +4,11 @@ include "reg-with-subregs-common.td"
// CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
// CHECK: OPC_CheckChild1Integer, 0,
-// CHECK: OPC_EmitStringInteger32, sub0_sub1,
+// CHECK: OPC_EmitStringIntegerI32, sub0_sub1,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
(EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
// CHECK: OPC_CheckChild1Integer, 30,
-// CHECK: OPC_EmitInteger32, 10|128,2/*266*/,
+// CHECK: OPC_EmitIntegerI32, 10|128,2/*266*/,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
(EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>;
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index f89187a8d8f2a..f8367b09423b9 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -795,7 +795,7 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N,
case MVT::i32:
case MVT::i64:
OpBytes = 1;
- OS << "OPC_EmitInteger" << VT.getSizeInBits() << ", ";
+ OS << "OPC_EmitIntegerI" << VT.getSizeInBits() << ", ";
break;
default:
OS << "OPC_EmitInteger, ";
@@ -818,7 +818,7 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N,
switch (VT.SimpleTy) {
case MVT::i32:
OpBytes = 1;
- OS << "OPC_EmitStringInteger" << VT.getSizeInBits() << ", ";
+ OS << "OPC_EmitStringIntegerI" << VT.getSizeInBits() << ", ";
break;
default:
OS << "OPC_EmitStringInteger, ";
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