[llvm] [AArch64] Eliminate redundant setcc on vector comparison results (PR #171431)

[via llvm-commits]

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@@ -4746,6 +4746,19 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
     }
   }
 
+  // setcc X, 0, setlt --> X  (when X is all sign bits)
+  //
+  // When we know that X has 0 or -1 in each lane, this comparison will produce
+  // X. This is only true when boolean contents are represented via 0s and -1s.
+  if (OpVT.isVector() && VT == OpVT &&
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DaKnig wrote:

why only when `isVector`?

https://github.com/llvm/llvm-project/pull/171431