[llvm] [InstCombine] Fold `(select C, (x bin_op a), x) bin_op b` into `x bin_op select C, (a bin_op b), b` (PR #173511)
Gábor Spaits via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 26 01:37:43 PST 2025
https://github.com/spaits updated https://github.com/llvm/llvm-project/pull/173511
>From bd6a25799082c15ccd70b02e993b2b2770f7376a Mon Sep 17 00:00:00 2001
From: Gabor Spaits <gaborspaits1 at gmail.com>
Date: Wed, 24 Dec 2025 18:40:57 +0100
Subject: [PATCH 1/5] Pre commit tests
---
.../Transforms/InstCombine/binop-select.ll | 788 ++++++++++++++++++
1 file changed, 788 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/binop-select.ll b/llvm/test/Transforms/InstCombine/binop-select.ll
index 9e336ad104599..f6af13ffabd7e 100644
--- a/llvm/test/Transforms/InstCombine/binop-select.ll
+++ b/llvm/test/Transforms/InstCombine/binop-select.ll
@@ -571,3 +571,791 @@ define i32 @OrSelectIcmpNonZero(i32 %a, i32 %b) {
%or = or i32 %sel, %a
ret i32 %or
}
+
+define i8 @BinOpSelectBinOpMultiUseRegsWithSelect1(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
+; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
+; CHECK-NEXT: [[USE:%.*]] = add i8 [[V1]], 42
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 [[USE]], i8 [[V3]]
+; CHECK-NEXT: ret i8 [[RETVAL]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 4, %arg0
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 1, %v2
+ %use = add i8 %v1, 42
+ %retVal = select i1 %whatToReturn, i8 %use, i8 %v3
+ ret i8 %retVal
+}
+
+
+define i8 @BinOpSelectBinOpMultiUseRegsWithSelect2(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
+; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
+; CHECK-NEXT: [[USE:%.*]] = add i8 [[V2]], 42
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 [[USE]], i8 [[V3]]
+; CHECK-NEXT: ret i8 [[RETVAL]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 4, %arg0
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 1, %v2
+ %use = add i8 %v2, 42
+ %retVal = select i1 %whatToReturn, i8 %use, i8 %v3
+ ret i8 %retVal
+}
+
+define i8 @BinOpSelectBinOpMultiUseRegsWithSelect3(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
+; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect3(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 [[V1]], i8 [[V3]]
+; CHECK-NEXT: ret i8 [[RETVAL]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 4, %arg0
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 1, %v2
+ %retVal = select i1 %whatToReturn, i8 %v1, i8 %v3
+ ret i8 %retVal
+}
+
+define i8 @BinOpSelectBinOpMultiUseRegsWithSelect4(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
+; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect4(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[NOT_WHATTORETURN:%.*]] = xor i1 [[WHATTORETURN:%.*]], true
+; CHECK-NEXT: [[V3:%.*]] = zext i1 [[NOT_WHATTORETURN]] to i8
+; CHECK-NEXT: [[RETVAL:%.*]] = or i8 [[V2]], [[V3]]
+; CHECK-NEXT: ret i8 [[RETVAL]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 4, %arg0
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 1, %v2
+ %retVal = select i1 %whatToReturn, i8 %v2, i8 %v3
+ ret i8 %retVal
+}
+
+; or tests
+define i8 @orSelectOrNoCommonBits1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrNoCommonBits1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 4
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 %v2, 1
+ ret i8 %v3
+}
+
+define i8 @orSelectOrNoCommonBits2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrNoCommonBits2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = zext i1 [[V0]] to i8
+; CHECK-NEXT: [[V2:%.*]] = or i8 [[ARG0:%.*]], [[V1]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 4
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 1
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 %v2, 4
+ ret i8 %v3
+}
+
+define i8 @orSelectOrReserved(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrReserved(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 2
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[ARG0]], i8 [[V1]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 13
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %arg0, i8 %v1
+ %v3 = or i8 %v2, 13
+ ret i8 %v3
+}
+
+define i8 @orSelectOrSubset1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrSubset1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 2
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 13
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 %v2, 13
+ ret i8 %v3
+}
+
+define i8 @orSelectOrSubset2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrSubset2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 13
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @orSelectOrSomeCommon1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrSomeCommon1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 10
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 5
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 %v2, 5
+ ret i8 %v3
+}
+
+define i8 @orSelectOrSomeCommon2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrSomeCommon2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 5
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @orSelectOrSame(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrSame(
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 42
+; CHECK-NEXT: ret i8 [[V1]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 42
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 %v2, 42
+ ret i8 %v3
+}
+
+; and tests
+define i8 @andSelectandNoCommonBits1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @andSelectandNoCommonBits1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[ARG0:%.*]], 1
+; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i8 0, i8 [[TMP1]]
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = and i8 %arg0, 4
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = and i8 %v2, 1
+ ret i8 %v3
+}
+
+define i8 @andSelectandNoCommonBits2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @andSelectandNoCommonBits2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V3:%.*]] = and i8 [[V2:%.*]], 4
+; CHECK-NEXT: [[V4:%.*]] = select i1 [[V0]], i8 0, i8 [[V3]]
+; CHECK-NEXT: ret i8 [[V4]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = and i8 %arg0, 1
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = and i8 %v2, 4
+ ret i8 %v3
+}
+
+define i8 @andSelectandSubset1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @andSelectandSubset1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V3_V:%.*]] = select i1 [[V0]], i8 9, i8 13
+; CHECK-NEXT: [[V3:%.*]] = and i8 [[ARG0:%.*]], [[V3_V]]
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = and i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = and i8 %v2, 13
+ ret i8 %v3
+}
+
+define i8 @andSelectandSubset2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @andSelectandSubset2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V3_V:%.*]] = select i1 [[V0]], i8 9, i8 11
+; CHECK-NEXT: [[V3:%.*]] = and i8 [[ARG0:%.*]], [[V3_V]]
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = and i8 %arg0, 13
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = and i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @andSelectandSomeCommon1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @andSelectandSomeCommon1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V3_V:%.*]] = select i1 [[V0]], i8 1, i8 5
+; CHECK-NEXT: [[V3:%.*]] = and i8 [[ARG0:%.*]], [[V3_V]]
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = and i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = and i8 %v2, 5
+ ret i8 %v3
+}
+
+define i8 @andSelectandSomeCommon2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @andSelectandSomeCommon2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V3_V:%.*]] = select i1 [[V0]], i8 1, i8 11
+; CHECK-NEXT: [[V3:%.*]] = and i8 [[ARG0:%.*]], [[V3_V]]
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = and i8 %arg0, 5
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = and i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @andSelectandSame(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @andSelectandSame(
+; CHECK-NEXT: [[V1:%.*]] = and i8 [[ARG0:%.*]], 42
+; CHECK-NEXT: ret i8 [[V1]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = and i8 %arg0, 42
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = and i8 %v2, 42
+ ret i8 %v3
+}
+
+; xor tests
+define i8 @xorSelectxorNoCommonBits1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @xorSelectxorNoCommonBits1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 1
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = xor i8 %arg0, 4
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = xor i8 %v2, 1
+ ret i8 %v3
+}
+
+define i8 @xorSelectxorNoCommonBits2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @xorSelectxorNoCommonBits2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = zext i1 [[V0]] to i8
+; CHECK-NEXT: [[V2:%.*]] = xor i8 [[ARG0:%.*]], [[V1]]
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 4
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = xor i8 %arg0, 1
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = xor i8 %v2, 4
+ ret i8 %v3
+}
+
+define i8 @xorSelectxorSubset1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @xorSelectxorSubset1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 11
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 13
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = xor i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = xor i8 %v2, 13
+ ret i8 %v3
+}
+
+define i8 @xorSelectxorSubset2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @xorSelectxorSubset2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 13
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = xor i8 %arg0, 13
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = xor i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @xorSelectxorSomeCommon1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @xorSelectxorSomeCommon1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 11
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 5
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = xor i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = xor i8 %v2, 5
+ ret i8 %v3
+}
+
+define i8 @xorSelectxorSomeCommon2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @xorSelectxorSomeCommon2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 5
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = xor i8 %arg0, 5
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = xor i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @xorSelectxorSame(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @xorSelectxorSame(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 42
+; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i8 [[ARG0]], i8 [[V1]]
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = xor i8 %arg0, 42
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = xor i8 %v2, 42
+ ret i8 %v3
+}
+
+; add tests
+define i8 @addSelectaddNoCommonBits1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @addSelectaddNoCommonBits1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 1
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = add i8 %arg0, 4
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = add i8 %v2, 1
+ ret i8 %v3
+}
+
+define i8 @addSelectaddNoCommonBits2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @addSelectaddNoCommonBits2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = zext i1 [[V0]] to i8
+; CHECK-NEXT: [[V2:%.*]] = add i8 [[ARG0:%.*]], [[V1]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 4
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = add i8 %arg0, 1
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = add i8 %v2, 4
+ ret i8 %v3
+}
+
+define i8 @addSelectaddSubset1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @addSelectaddSubset1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 11
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 13
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = add i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = add i8 %v2, 13
+ ret i8 %v3
+}
+
+define i8 @addSelectaddSubset2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @addSelectaddSubset2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 13
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = add i8 %arg0, 13
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = add i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @addSelectaddSomeCommon1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @addSelectaddSomeCommon1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 11
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 5
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = add i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = add i8 %v2, 5
+ ret i8 %v3
+}
+
+define i8 @addSelectaddSomeCommon2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @addSelectaddSomeCommon2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 5
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = add i8 %arg0, 5
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = add i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @addSelectaddSame(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @addSelectaddSame(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 42
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 42
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = add i8 %arg0, 42
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = add i8 %v2, 42
+ ret i8 %v3
+}
+
+; sub tests
+define i8 @subSelectsubNoCommonBitsConstOnLeft1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubNoCommonBitsConstOnLeft1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = sub i8 4, [[ARG0:%.*]]
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -1
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 4, %arg0
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 %v2, 1
+ ret i8 %v3
+}
+
+define i8 @subSelectsubNoCommonBitsConstOnLeft2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubNoCommonBitsConstOnLeft2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = sub i8 1, [[V2]]
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 %arg0, 4
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 1, %v2
+ ret i8 %v3
+}
+
+define i8 @subSelectsubNoCommonBitsConstOnLeft3(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubNoCommonBitsConstOnLeft3(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = sub i8 4, [[TMP2:%.*]]
+; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i8 [[TMP1]], i8 [[TMP2]]
+; CHECK-NEXT: [[V4:%.*]] = sub i8 1, [[V3]]
+; CHECK-NEXT: ret i8 [[V4]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 4, %arg0
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 1, %v2
+ ret i8 %v3
+}
+
+define i8 @subSelectsubNoCommonBits1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubNoCommonBits1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -1
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 %arg0, 4
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 %v2, 1
+ ret i8 %v3
+}
+
+define i8 @subSelectsubNoCommonBits2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubNoCommonBits2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = sext i1 [[V0]] to i8
+; CHECK-NEXT: [[V2:%.*]] = add i8 [[ARG0:%.*]], [[V1]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -4
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 %arg0, 1
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 %v2, 4
+ ret i8 %v3
+}
+
+define i8 @subSelectsubSubset1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubSubset1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -11
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -13
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 %v2, 13
+ ret i8 %v3
+}
+
+define i8 @subSelectsubSubset2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubSubset2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -13
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 %arg0, 13
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @subSelectsubSomeCommon1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubSomeCommon1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -11
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -5
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 %v2, 5
+ ret i8 %v3
+}
+
+define i8 @subSelectsubSomeCommon2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubSomeCommon2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -5
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 %arg0, 5
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @subSelectsubSame(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @subSelectsubSame(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -42
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -42
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = sub i8 %arg0, 42
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = sub i8 %v2, 42
+ ret i8 %v3
+}
+
+; mul tests
+define i8 @mulSelectmulNoCommonBits1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @mulSelectmulNoCommonBits1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = shl i8 [[ARG0:%.*]], 2
+; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V2:%.*]] = shl i8 [[V3]], 1
+; CHECK-NEXT: ret i8 [[V2]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = mul i8 %arg0, 4
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = mul i8 %v2, 2
+ ret i8 %v3
+}
+
+define i8 @mulSelectmulNoCommonBits2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @mulSelectmulNoCommonBits2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG2:%.*]], 3
+; CHECK-NEXT: [[ARG0:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG2]]
+; CHECK-NEXT: [[V3:%.*]] = shl i8 [[ARG0]], 2
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = mul i8 %arg0, 3
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = mul i8 %v2, 4
+ ret i8 %v3
+}
+
+define i8 @mulSelectmulmulset1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @mulSelectmulmulset1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 11
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 13
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = mul i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = mul i8 %v2, 13
+ ret i8 %v3
+}
+
+define i8 @mulSelectmulmulset2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @mulSelectmulmulset2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 13
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = mul i8 %arg0, 13
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = mul i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @mulSelectmulSomeCommon1(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @mulSelectmulSomeCommon1(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 11
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 5
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = mul i8 %arg0, 11
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = mul i8 %v2, 5
+ ret i8 %v3
+}
+
+define i8 @mulSelectmulSomeCommon2(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @mulSelectmulSomeCommon2(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 5
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 11
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = mul i8 %arg0, 5
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = mul i8 %v2, 11
+ ret i8 %v3
+}
+
+define i8 @mulSelectmulSame(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @mulSelectmulSame(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 42
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 42
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = mul i8 %arg0, 42
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = mul i8 %v2, 42
+ ret i8 %v3
+}
+
+define i8 @orSelectOrUses(i8 %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrUses(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
+; CHECK-NEXT: [[RES:%.*]] = add i8 [[V1]], [[V3]]
+; CHECK-NEXT: ret i8 [[RES]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or i8 %arg0, 4
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = or i8 %v2, 1
+ %res = add i8 %v1, %v3
+ ret i8 %res
+}
+
+define i8 @udivSelectudivSomeCommon1InfLoopRep(i8 %arg0, i8 %arg1, i1 %v0) {
+; CHECK-LABEL: @udivSelectudivSomeCommon1InfLoopRep(
+; CHECK-NEXT: [[V1:%.*]] = udiv i8 11, [[ARG0:%.*]]
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0:%.*]], i8 [[V1]], i8 [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = udiv i8 [[V2]], 5
+; CHECK-NEXT: ret i8 [[V3]]
+;
+ %v01 = icmp sgt i8 %arg0, 0
+ %v1 = udiv i8 11, %arg0
+ %v2 = select i1 %v0, i8 %v1, i8 %arg0
+ %v3 = udiv i8 %v2, 5
+ ret i8 %v3
+}
>From c9997810701d07f2c70d21445a7ca99e1250094c Mon Sep 17 00:00:00 2001
From: Gabor Spaits <gaborspaits1 at gmail.com>
Date: Wed, 24 Dec 2025 22:27:03 +0100
Subject: [PATCH 2/5] [InstCombine] Simplify associative binary ops when there
is a select between them
---
.../InstCombine/InstCombineAddSub.cpp | 3 +
.../InstCombine/InstCombineAndOrXor.cpp | 6 +
.../InstCombine/InstCombineInternal.h | 2 +
.../InstCombine/InstCombineMulDivRem.cpp | 3 +
.../InstCombine/InstructionCombining.cpp | 39 +++++
.../Transforms/InstCombine/binop-select.ll | 155 +++++++-----------
llvm/test/Transforms/PGOProfile/chr.ll | 24 +--
7 files changed, 128 insertions(+), 104 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index 9bee523c7b7e5..95e7cbed60a27 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -863,6 +863,9 @@ Instruction *InstCombinerImpl::foldAddWithConstant(BinaryOperator &Add) {
if (Instruction *NV = foldBinOpIntoSelectOrPhi(Add))
return NV;
+ if (Instruction *FoldedLogic = foldSelectIntoBinOp(Add))
+ return FoldedLogic;
+
Value *X;
Constant *Op00C;
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 9cf382f8020fa..5978e39ebb2b6 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -4077,6 +4077,9 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
return FoldedLogic;
+ if (Instruction *FoldedLogic = foldSelectIntoBinOp(I))
+ return FoldedLogic;
+
if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
/*MatchBitReversals*/ true))
return BitOp;
@@ -5383,6 +5386,9 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) {
if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
return FoldedLogic;
+ if (Instruction *FoldedLogic = foldSelectIntoBinOp(I))
+ return FoldedLogic;
+
// Y ^ (X | Y) --> X & ~Y
// Y ^ (Y | X) --> X & ~Y
if (match(Op1, m_OneUse(m_c_Or(m_Value(X), m_Specific(Op0)))))
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
index 9bdd8cb71f7f3..2bfb632c37a63 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
+++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
@@ -667,6 +667,8 @@ class LLVM_LIBRARY_VISIBILITY InstCombinerImpl final
bool FoldWithMultiUse = false,
bool SimplifyBothArms = false);
+ Instruction *foldSelectIntoBinOp(BinaryOperator &Op);
+
/// This is a convenience wrapper function for the above two functions.
Instruction *foldBinOpIntoSelectOrPhi(BinaryOperator &I);
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index a9aacc707cc20..303557520ee23 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -317,6 +317,9 @@ Instruction *InstCombinerImpl::visitMul(BinaryOperator &I) {
if (Instruction *FoldedMul = foldBinOpIntoSelectOrPhi(I))
return FoldedMul;
+ if (Instruction *FoldedLogic = foldSelectIntoBinOp(I))
+ return FoldedLogic;
+
if (Value *FoldedMul = foldMulSelectToNegate(I, Builder))
return replaceInstUsesWith(I, FoldedMul);
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index 14244236d75d5..df32ef7fd8450 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1876,6 +1876,45 @@ static Value *simplifyInstructionWithPHI(Instruction &I, PHINode *PN,
return nullptr;
}
+// In some cases it is beneficial to fold a select into a binary operator.
+// For example:
+// %1 = or %in, 4
+// %2 = select %cond, %1, %in
+// %3 = or %2, 1
+// =>
+// %1 = select i1 %cond, 5, 1
+// %2 = or %1, %in
+Instruction *InstCombinerImpl::foldSelectIntoBinOp(BinaryOperator &Op) {
+ SelectInst *SI = dyn_cast<SelectInst>(Op.getOperand(0));
+ ConstantInt *Const = dyn_cast<ConstantInt>(Op.getOperand(1));
+ if (!SI || !Const || !Op.hasOneUse() || !SI->hasOneUse())
+ return nullptr;
+
+ // TODO: Maybe hasOneUse the other bin op too?
+
+ Value *Input, *NewTV, *NewFV, *Cond;
+ ConstantInt *Const2;
+ if (match(SI, m_Select(m_Value(Cond),
+ m_c_BinOp(Op.getOpcode(), m_Value(Input),
+ m_ConstantInt(Const2)),
+ m_Deferred(Input)))) {
+ NewTV = simplifyBinOp(Op.getOpcode(), Const, Const2,
+ SQ.getWithInstruction(&Op));
+ NewFV = Const;
+ } else if (match(SI, m_Select(m_Value(Cond), m_Value(Input),
+ m_c_BinOp(Op.getOpcode(), m_Deferred(Input),
+ m_ConstantInt(Const2))))) {
+ NewTV = Const;
+ NewFV = simplifyBinOp(Op.getOpcode(), Const, Const2,
+ SQ.getWithInstruction(&Op));
+ } else
+ return nullptr;
+
+ SelectInst *NewSI = SelectInst::Create(Cond, NewTV, NewFV);
+ InsertNewInstBefore(NewSI, Op.getIterator());
+ return BinaryOperator::Create(Op.getOpcode(), NewSI, Input);
+}
+
Instruction *InstCombinerImpl::foldOpIntoPhi(Instruction &I, PHINode *PN,
bool AllowMultipleUses) {
unsigned NumPHIValues = PN->getNumIncomingValues();
diff --git a/llvm/test/Transforms/InstCombine/binop-select.ll b/llvm/test/Transforms/InstCombine/binop-select.ll
index f6af13ffabd7e..c5da60c316c50 100644
--- a/llvm/test/Transforms/InstCombine/binop-select.ll
+++ b/llvm/test/Transforms/InstCombine/binop-select.ll
@@ -576,8 +576,8 @@ define i8 @BinOpSelectBinOpMultiUseRegsWithSelect1(i8 %arg0, i8 %arg1, i1 %whatT
; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0]]
; CHECK-NEXT: [[USE:%.*]] = add i8 [[V1]], 42
; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 [[USE]], i8 [[V3]]
; CHECK-NEXT: ret i8 [[RETVAL]]
@@ -614,10 +614,9 @@ define i8 @BinOpSelectBinOpMultiUseRegsWithSelect2(i8 %arg0, i8 %arg1, i1 %whatT
define i8 @BinOpSelectBinOpMultiUseRegsWithSelect3(i8 %arg0, i8 %arg1, i1 %whatToReturn) {
; CHECK-LABEL: @BinOpSelectBinOpMultiUseRegsWithSelect3(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
-; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 [[V1]], i8 [[V3]]
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1
+; CHECK-NEXT: [[RETVAL_V:%.*]] = select i1 [[WHATTORETURN:%.*]], i8 4, i8 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = or i8 [[ARG0:%.*]], [[RETVAL_V]]
; CHECK-NEXT: ret i8 [[RETVAL]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -650,9 +649,8 @@ define i8 @BinOpSelectBinOpMultiUseRegsWithSelect4(i8 %arg0, i8 %arg1, i1 %whatT
define i8 @orSelectOrNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -680,9 +678,8 @@ define i8 @orSelectOrNoCommonBits2(i8 %arg0, i8 %arg1) {
define i8 @orSelectOrReserved(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrReserved(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 2
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[ARG0]], i8 [[V1]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 13
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 13, i8 15
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -695,9 +692,8 @@ define i8 @orSelectOrReserved(i8 %arg0, i8 %arg1) {
define i8 @orSelectOrSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 2
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 13
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 15, i8 13
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -710,9 +706,8 @@ define i8 @orSelectOrSubset1(i8 %arg0, i8 %arg1) {
define i8 @orSelectOrSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 15, i8 11
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -725,9 +720,8 @@ define i8 @orSelectOrSubset2(i8 %arg0, i8 %arg1) {
define i8 @orSelectOrSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 10
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 5
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 15, i8 5
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -740,9 +734,8 @@ define i8 @orSelectOrSomeCommon1(i8 %arg0, i8 %arg1) {
define i8 @orSelectOrSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 15, i8 11
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -865,9 +858,8 @@ define i8 @andSelectandSame(i8 %arg0, i8 %arg1) {
define i8 @xorSelectxorNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -895,9 +887,8 @@ define i8 @xorSelectxorNoCommonBits2(i8 %arg0, i8 %arg1) {
define i8 @xorSelectxorSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 11
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 13
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 6, i8 13
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -910,9 +901,8 @@ define i8 @xorSelectxorSubset1(i8 %arg0, i8 %arg1) {
define i8 @xorSelectxorSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 13
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 6, i8 11
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -925,9 +915,8 @@ define i8 @xorSelectxorSubset2(i8 %arg0, i8 %arg1) {
define i8 @xorSelectxorSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 11
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 5
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 14, i8 5
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -940,9 +929,8 @@ define i8 @xorSelectxorSomeCommon1(i8 %arg0, i8 %arg1) {
define i8 @xorSelectxorSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @xorSelectxorSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = xor i8 [[ARG0:%.*]], 5
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = xor i8 [[V2]], 11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 14, i8 11
+; CHECK-NEXT: [[V3:%.*]] = xor i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -970,9 +958,8 @@ define i8 @xorSelectxorSame(i8 %arg0, i8 %arg1) {
define i8 @addSelectaddNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1000,9 +987,8 @@ define i8 @addSelectaddNoCommonBits2(i8 %arg0, i8 %arg1) {
define i8 @addSelectaddSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 11
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 13
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 24, i8 13
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1015,9 +1001,8 @@ define i8 @addSelectaddSubset1(i8 %arg0, i8 %arg1) {
define i8 @addSelectaddSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 13
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 24, i8 11
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1030,9 +1015,8 @@ define i8 @addSelectaddSubset2(i8 %arg0, i8 %arg1) {
define i8 @addSelectaddSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 11
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 5
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 16, i8 5
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1045,9 +1029,8 @@ define i8 @addSelectaddSomeCommon1(i8 %arg0, i8 %arg1) {
define i8 @addSelectaddSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 5
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 16, i8 11
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1060,9 +1043,8 @@ define i8 @addSelectaddSomeCommon2(i8 %arg0, i8 %arg1) {
define i8 @addSelectaddSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @addSelectaddSame(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], 42
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 42
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 84, i8 42
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1121,9 +1103,8 @@ define i8 @subSelectsubNoCommonBitsConstOnLeft3(i8 %arg0, i8 %arg1) {
define i8 @subSelectsubNoCommonBits1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubNoCommonBits1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -5, i8 -1
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1151,9 +1132,8 @@ define i8 @subSelectsubNoCommonBits2(i8 %arg0, i8 %arg1) {
define i8 @subSelectsubSubset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSubset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -11
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -13
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -24, i8 -13
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1166,9 +1146,8 @@ define i8 @subSelectsubSubset1(i8 %arg0, i8 %arg1) {
define i8 @subSelectsubSubset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSubset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -13
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -24, i8 -11
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1181,9 +1160,8 @@ define i8 @subSelectsubSubset2(i8 %arg0, i8 %arg1) {
define i8 @subSelectsubSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -11
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -5
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -16, i8 -5
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1196,9 +1174,8 @@ define i8 @subSelectsubSomeCommon1(i8 %arg0, i8 %arg1) {
define i8 @subSelectsubSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -5
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -16, i8 -11
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1211,9 +1188,8 @@ define i8 @subSelectsubSomeCommon2(i8 %arg0, i8 %arg1) {
define i8 @subSelectsubSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @subSelectsubSame(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = add i8 [[ARG0:%.*]], -42
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], -42
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -84, i8 -42
+; CHECK-NEXT: [[V3:%.*]] = add i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1257,9 +1233,8 @@ define i8 @mulSelectmulNoCommonBits2(i8 %arg0, i8 %arg1) {
define i8 @mulSelectmulmulset1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulmulset1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 11
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 13
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -113, i8 13
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1272,9 +1247,8 @@ define i8 @mulSelectmulmulset1(i8 %arg0, i8 %arg1) {
define i8 @mulSelectmulmulset2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulmulset2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 13
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -113, i8 11
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1287,9 +1261,8 @@ define i8 @mulSelectmulmulset2(i8 %arg0, i8 %arg1) {
define i8 @mulSelectmulSomeCommon1(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulSomeCommon1(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 11
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 5
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 55, i8 5
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1302,9 +1275,8 @@ define i8 @mulSelectmulSomeCommon1(i8 %arg0, i8 %arg1) {
define i8 @mulSelectmulSomeCommon2(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulSomeCommon2(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 5
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 11
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 55, i8 11
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1317,9 +1289,8 @@ define i8 @mulSelectmulSomeCommon2(i8 %arg0, i8 %arg1) {
define i8 @mulSelectmulSame(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @mulSelectmulSame(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
-; CHECK-NEXT: [[V1:%.*]] = mul i8 [[ARG0:%.*]], 42
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = mul i8 [[V2]], 42
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 -28, i8 42
+; CHECK-NEXT: [[V3:%.*]] = mul i8 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = icmp eq i8 %arg1, -1
@@ -1333,8 +1304,8 @@ define i8 @orSelectOrUses(i8 %arg0, i8 %arg1) {
; CHECK-LABEL: @orSelectOrUses(
; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
; CHECK-NEXT: [[V1:%.*]] = or i8 [[ARG0:%.*]], 4
-; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], i8 [[V1]], i8 [[ARG0]]
-; CHECK-NEXT: [[V3:%.*]] = or i8 [[V2]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[V0]], i8 5, i8 1
+; CHECK-NEXT: [[V3:%.*]] = or i8 [[TMP1]], [[ARG0]]
; CHECK-NEXT: [[RES:%.*]] = add i8 [[V1]], [[V3]]
; CHECK-NEXT: ret i8 [[RES]]
;
diff --git a/llvm/test/Transforms/PGOProfile/chr.ll b/llvm/test/Transforms/PGOProfile/chr.ll
index 258af5c488997..6ed997edeb867 100644
--- a/llvm/test/Transforms/PGOProfile/chr.ll
+++ b/llvm/test/Transforms/PGOProfile/chr.ll
@@ -478,7 +478,7 @@ define i32 @test_chr_5(ptr %i, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP11]], 0
; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[DOTFR1]], 8
; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0
-; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP14]], i32 44, i32 88
+; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP14]], i32 44, i32 88, !prof [[PROF16]]
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP12]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]]
; CHECK-NEXT: br label [[BB3]]
@@ -579,7 +579,7 @@ define i32 @test_chr_5_1(ptr %i, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0
; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[DOTFR1]], 8
; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 0
-; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP17]], i32 44, i32 88
+; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP17]], i32 44, i32 88, !prof [[PROF16]]
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP15]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]]
; CHECK-NEXT: br label [[BB3]]
@@ -677,7 +677,7 @@ define i32 @test_chr_6(ptr %i, ptr %j, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[V10_NONCHR:%.*]] = icmp eq i32 [[V9_NONCHR]], 0
; CHECK-NEXT: [[V11_NONCHR:%.*]] = and i32 [[I0_FR]], 8
; CHECK-NEXT: [[V12_NONCHR:%.*]] = icmp eq i32 [[V11_NONCHR]], 0
-; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[V12_NONCHR]], i32 44, i32 88
+; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[V12_NONCHR]], i32 44, i32 88, !prof [[PROF16]]
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[V10_NONCHR]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]]
; CHECK-NEXT: br label [[BB3]]
@@ -1392,7 +1392,7 @@ define i32 @test_chr_15(ptr %i, ptr %j, i32 %sum0, i1 %pred, i32 %z) !prof !14 {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[I0:%.*]] = load i32, ptr [[I:%.*]], align 4
; CHECK-NEXT: [[V0:%.*]] = icmp eq i32 [[Z:%.*]], 0
-; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i1 [[PRED:%.*]], i1 false
+; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i1 [[PRED:%.*]], i1 false, !prof [[PROF19:![0-9]+]]
; CHECK-NEXT: br i1 [[V3]], label [[BB0:%.*]], label [[BB1:%.*]], !prof [[PROF16]]
; CHECK: bb0:
; CHECK-NEXT: call void @foo()
@@ -1670,15 +1670,15 @@ define i32 @test_chr_18(ptr %i, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[INC1:%.*]] = phi i32 [ [[TMP2:%.*]], [[BB2:%.*]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[LI:%.*]] = load i32, ptr [[I:%.*]], align 4
; CHECK-NEXT: [[LI_FR:%.*]] = freeze i32 [[LI]]
-; CHECK-NEXT: [[SUM1:%.*]] = add i32 [[SUM0:%.*]], 42
; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[LI_FR]], 5
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 5
; CHECK-NEXT: br i1 [[TMP1]], label [[BB1:%.*]], label [[BB0_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
; CHECK: bb1:
; CHECK-NEXT: [[INC2:%.*]] = add i32 [[INC1]], 1
-; CHECK-NEXT: [[SUM3:%.*]] = add i32 [[SUM0]], 86
+; CHECK-NEXT: [[SUM3:%.*]] = add i32 [[SUM0:%.*]], 86
; CHECK-NEXT: br label [[BB2]]
; CHECK: bb0.split.nonchr:
+; CHECK-NEXT: [[SUM1:%.*]] = add i32 [[SUM0]], 42
; CHECK-NEXT: [[A4_NONCHR:%.*]] = and i32 [[LI_FR]], 4
; CHECK-NEXT: [[CMP4_NONCHR:%.*]] = icmp eq i32 [[A4_NONCHR]], 0
; CHECK-NEXT: [[INC2_NONCHR:%.*]] = add i32 [[INC1]], 1
@@ -1686,8 +1686,8 @@ define i32 @test_chr_18(ptr %i, i32 %sum0) !prof !14 {
; CHECK: bb1.nonchr:
; CHECK-NEXT: [[A1:%.*]] = and i32 [[LI_FR]], 1
; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i32 [[A1]], 0
-; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[CMP1_NOT]], i32 [[SUM0]], i32 [[SUM1]], !prof [[PROF16]]
-; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], 44
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[CMP1_NOT]], i32 44, i32 86
+; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = add i32 [[TMP3]], [[SUM0]]
; CHECK-NEXT: br label [[BB2]]
; CHECK: bb2:
; CHECK-NEXT: [[TMP2]] = phi i32 [ [[INC2]], [[BB1]] ], [ [[INC2_NONCHR]], [[BB0_SPLIT_NONCHR]] ], [ [[INC2_NONCHR]], [[BB1_NONCHR]] ]
@@ -1777,7 +1777,7 @@ define i32 @test_chr_19(ptr %i, i32 %sum0) !prof !14 {
; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM0]], i32 [[TMP7]], !prof [[PROF16]]
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[DOTFR1]], 8
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0
-; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP9]], i32 44, i32 88
+; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP9]], i32 44, i32 88, !prof [[PROF16]]
; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]]
; CHECK-NEXT: br label [[BB3]]
@@ -1945,7 +1945,7 @@ define i32 @test_chr_21(i64 %i, i64 %k, i64 %j) "instcombine-no-verify-fixpoint"
; CHECK-NEXT: switch i64 [[I_FR]], label [[BB2:%.*]] [
; CHECK-NEXT: i64 2, label [[BB3_NONCHR2:%.*]]
; CHECK-NEXT: i64 86, label [[BB2_NONCHR1:%.*]]
-; CHECK-NEXT: ], !prof [[PROF19:![0-9]+]]
+; CHECK-NEXT: ], !prof [[PROF20:![0-9]+]]
; CHECK: bb2:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: call void @foo()
@@ -2527,14 +2527,14 @@ define void @test_chr_24(ptr %i) !prof !14 {
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF20:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF21:![0-9]+]]
; CHECK: bb0:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB1]]
; CHECK: bb1:
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 2
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
-; CHECK-NEXT: br i1 [[TMP4]], label [[BB3:%.*]], label [[BB2:%.*]], !prof [[PROF20]]
+; CHECK-NEXT: br i1 [[TMP4]], label [[BB3:%.*]], label [[BB2:%.*]], !prof [[PROF21]]
; CHECK: bb2:
; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label [[BB3]]
>From f40cd16c9fdb19df6892a8cd6039f167b0c0bf79 Mon Sep 17 00:00:00 2001
From: Gabor Spaits <gaborspaits1 at gmail.com>
Date: Thu, 25 Dec 2025 17:37:53 +0100
Subject: [PATCH 3/5] Don't forget to return if simplification fails and use
Builder
---
.../InstCombine/InstructionCombining.cpp | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index df32ef7fd8450..9d39f0d53f04a 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1895,23 +1895,25 @@ Instruction *InstCombinerImpl::foldSelectIntoBinOp(BinaryOperator &Op) {
Value *Input, *NewTV, *NewFV, *Cond;
ConstantInt *Const2;
if (match(SI, m_Select(m_Value(Cond),
- m_c_BinOp(Op.getOpcode(), m_Value(Input),
- m_ConstantInt(Const2)),
+ m_BinOp(Op.getOpcode(), m_Value(Input),
+ m_ConstantInt(Const2)),
m_Deferred(Input)))) {
NewTV = simplifyBinOp(Op.getOpcode(), Const, Const2,
SQ.getWithInstruction(&Op));
NewFV = Const;
} else if (match(SI, m_Select(m_Value(Cond), m_Value(Input),
- m_c_BinOp(Op.getOpcode(), m_Deferred(Input),
- m_ConstantInt(Const2))))) {
+ m_BinOp(Op.getOpcode(), m_Deferred(Input),
+ m_ConstantInt(Const2))))) {
NewTV = Const;
NewFV = simplifyBinOp(Op.getOpcode(), Const, Const2,
SQ.getWithInstruction(&Op));
} else
return nullptr;
- SelectInst *NewSI = SelectInst::Create(Cond, NewTV, NewFV);
- InsertNewInstBefore(NewSI, Op.getIterator());
+ if (!NewTV || !NewFV)
+ return nullptr;
+
+ Value *NewSI = Builder.CreateSelect(Cond, NewTV, NewFV);
return BinaryOperator::Create(Op.getOpcode(), NewSI, Input);
}
>From 0330e853fec700030133f501fb6368035b707793 Mon Sep 17 00:00:00 2001
From: Gabor Spaits <gaborspaits1 at gmail.com>
Date: Fri, 26 Dec 2025 10:35:30 +0100
Subject: [PATCH 4/5] Add a vector test, use , assert associativeness
---
.../InstCombine/InstructionCombining.cpp | 8 ++++----
.../test/Transforms/InstCombine/binop-select.ll | 17 +++++++++++++++++
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index 9d39f0d53f04a..ce7cc2e93bbe1 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1885,6 +1885,8 @@ static Value *simplifyInstructionWithPHI(Instruction &I, PHINode *PN,
// %1 = select i1 %cond, 5, 1
// %2 = or %1, %in
Instruction *InstCombinerImpl::foldSelectIntoBinOp(BinaryOperator &Op) {
+ assert(Op.isAssociative() && "The operation must be associative!");
+
SelectInst *SI = dyn_cast<SelectInst>(Op.getOperand(0));
ConstantInt *Const = dyn_cast<ConstantInt>(Op.getOperand(1));
if (!SI || !Const || !Op.hasOneUse() || !SI->hasOneUse())
@@ -1898,15 +1900,13 @@ Instruction *InstCombinerImpl::foldSelectIntoBinOp(BinaryOperator &Op) {
m_BinOp(Op.getOpcode(), m_Value(Input),
m_ConstantInt(Const2)),
m_Deferred(Input)))) {
- NewTV = simplifyBinOp(Op.getOpcode(), Const, Const2,
- SQ.getWithInstruction(&Op));
+ NewTV = ConstantFoldBinaryInstruction(Op.getOpcode(), Const, Const2);
NewFV = Const;
} else if (match(SI, m_Select(m_Value(Cond), m_Value(Input),
m_BinOp(Op.getOpcode(), m_Deferred(Input),
m_ConstantInt(Const2))))) {
NewTV = Const;
- NewFV = simplifyBinOp(Op.getOpcode(), Const, Const2,
- SQ.getWithInstruction(&Op));
+ NewFV = ConstantFoldBinaryInstruction(Op.getOpcode(), Const, Const2);
} else
return nullptr;
diff --git a/llvm/test/Transforms/InstCombine/binop-select.ll b/llvm/test/Transforms/InstCombine/binop-select.ll
index c5da60c316c50..28ea4cb36f2aa 100644
--- a/llvm/test/Transforms/InstCombine/binop-select.ll
+++ b/llvm/test/Transforms/InstCombine/binop-select.ll
@@ -1330,3 +1330,20 @@ define i8 @udivSelectudivSomeCommon1InfLoopRep(i8 %arg0, i8 %arg1, i1 %v0) {
%v3 = udiv i8 %v2, 5
ret i8 %v3
}
+
+; vector tests
+define <4 x i8> @orSelectOrVectors(<4 x i8> %arg0, i8 %arg1) {
+; CHECK-LABEL: @orSelectOrVectors(
+; CHECK-NEXT: [[V0:%.*]] = icmp eq i8 [[ARG1:%.*]], -1
+; CHECK-NEXT: [[V1:%.*]] = or <4 x i8> [[ARG0:%.*]], <i8 4, i8 2, i8 11, i8 21>
+; CHECK-NEXT: [[V2:%.*]] = select i1 [[V0]], <4 x i8> [[V1]], <4 x i8> [[ARG0]]
+; CHECK-NEXT: [[V3:%.*]] = or <4 x i8> [[V2]], <i8 1, i8 4, i8 17, i8 5>
+; CHECK-NEXT: ret <4 x i8> [[V3]]
+;
+ %v0 = icmp eq i8 %arg1, -1
+ %v1 = or <4 x i8> %arg0, <i8 4, i8 2, i8 11, i8 21>
+ %v2 = select i1 %v0, <4 x i8> %v1, <4 x i8> %arg0
+ %v3 = or <4 x i8> %v2, <i8 1, i8 4, i8 17, i8 5>
+ ret <4 x i8> %v3
+}
+
>From 19bda7c991679ad7f0f491369f61b5ca422979a1 Mon Sep 17 00:00:00 2001
From: Gabor Spaits <gaborspaits1 at gmail.com>
Date: Fri, 26 Dec 2025 10:37:27 +0100
Subject: [PATCH 5/5] Use m_ImmConstant
---
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index ce7cc2e93bbe1..96aec0310b6da 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1895,16 +1895,16 @@ Instruction *InstCombinerImpl::foldSelectIntoBinOp(BinaryOperator &Op) {
// TODO: Maybe hasOneUse the other bin op too?
Value *Input, *NewTV, *NewFV, *Cond;
- ConstantInt *Const2;
+ Constant *Const2;
if (match(SI, m_Select(m_Value(Cond),
m_BinOp(Op.getOpcode(), m_Value(Input),
- m_ConstantInt(Const2)),
+ m_ImmConstant(Const2)),
m_Deferred(Input)))) {
NewTV = ConstantFoldBinaryInstruction(Op.getOpcode(), Const, Const2);
NewFV = Const;
} else if (match(SI, m_Select(m_Value(Cond), m_Value(Input),
m_BinOp(Op.getOpcode(), m_Deferred(Input),
- m_ConstantInt(Const2))))) {
+ m_ImmConstant(Const2))))) {
NewTV = Const;
NewFV = ConstantFoldBinaryInstruction(Op.getOpcode(), Const, Const2);
} else
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