[llvm] a910b2e - [Mips] Mark function calls as possibly changing FCSR (FCR31) (#170314)

[via llvm-commits]

Author: Erik Enikeev
Date: 2025-12-26T16:32:03+08:00
New Revision: a910b2e28b71321287d9f8bb05af451ec7101b41

URL: https://github.com/llvm/llvm-project/commit/a910b2e28b71321287d9f8bb05af451ec7101b41
DIFF: https://github.com/llvm/llvm-project/commit/a910b2e28b71321287d9f8bb05af451ec7101b41.diff

LOG: [Mips] Mark function calls as possibly changing FCSR (FCR31) (#170314)

This patch does the same changes as D143001 for AArch64 and #160699 for
ARM.

Added: 
    llvm/test/CodeGen/Mips/strict-fp-func.ll

Modified: 
    llvm/lib/Target/Mips/MipsISelLowering.cpp
    llvm/lib/Target/Mips/MipsISelLowering.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 461a7b63de61b..ef1961a646eb7 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -2936,6 +2936,11 @@ SDValue MipsTargetLowering::lowerSTRICT_FP_TO_INT(SDValue Op,
   return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
 }
 
+ArrayRef<MCPhysReg> MipsTargetLowering::getRoundingControlRegisters() const {
+  static const MCPhysReg RCRegs[] = {Mips::FCR31};
+  return RCRegs;
+}
+
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index c58032812d8b1..8144b246663a4 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -507,6 +507,8 @@ class TargetRegisterClass;
 
     int getCPURegisterIndex(StringRef Name) const;
 
+    ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
+
     /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
     MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
                                                 MachineBasicBlock *BB,

diff  --git a/llvm/test/CodeGen/Mips/strict-fp-func.ll b/llvm/test/CodeGen/Mips/strict-fp-func.ll
new file mode 100644
index 0000000000000..a0918f9e1caef
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/strict-fp-func.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=mips -stop-after=finalize-isel %s -o - | FileCheck %s
+
+define float @func_02(float %x, float %y) strictfp nounwind {
+; CHECK-LABEL: name: func_02
+; CHECK:       JAL @func_01, {{.*}}, implicit-def $fcr31
+  %call = call float @func_01(float %x) strictfp
+  %res = call float @llvm.experimental.constrained.fadd.f32(float %call, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore") strictfp
+  ret float %res
+}
+
+declare float @func_01(float)