[llvm] [AArch64] Support lowering v4i16/f16 VECTOR_COMPRESS nodes to SVE (PR #173256)

[Paul Walker via llvm-commits]

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@@ -705,6 +707,32 @@ void VectorLegalizer::PromoteFloatVECREDUCE(SDNode *Node,
   Results.push_back(Res);
 }
 
+void VectorLegalizer::PromoteVECTOR_COMPRESS(
+    SDNode *Node, SmallVectorImpl<SDValue> &Results) {
+  SDLoc DL(Node);
+  EVT VT = Node->getValueType(0);
+  MVT PromotedVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT.getSimpleVT());
+  assert((VT.isInteger() || VT.getSizeInBits() == PromotedVT.getSizeInBits()) &&
+         "Only integer promotion or bitcasts between types is supported");
+
+  SDValue Vec = Node->getOperand(0);
+  SDValue Mask = TLI.promoteTargetBoolean(DAG, Node->getOperand(1), PromotedVT);
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paulwalker-arm wrote:

Perhaps move the `promoteTargetBoolean` call into the `VT.isInteger()` block because when bit casting, the mask should be unchanged?

https://github.com/llvm/llvm-project/pull/173256